atcspi200_spi.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Andestech ATCSPI200 SPI controller driver.
  4. *
  5. * Copyright 2017 Andes Technology, Inc.
  6. * Author: Rick Chen (rick@andestech.com)
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <malloc.h>
  11. #include <spi.h>
  12. #include <asm/io.h>
  13. #include <dm.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. #define MAX_TRANSFER_LEN 512
  16. #define CHUNK_SIZE 1
  17. #define SPI_TIMEOUT 0x100000
  18. #define SPI0_BUS 0
  19. #define SPI1_BUS 1
  20. #define SPI0_BASE 0xf0b00000
  21. #define SPI1_BASE 0xf0f00000
  22. #define NSPI_MAX_CS_NUM 1
  23. struct atcspi200_spi_regs {
  24. u32 rev;
  25. u32 reserve1[3];
  26. u32 format; /* 0x10 */
  27. #define DATA_LENGTH(x) ((x-1)<<8)
  28. u32 pio;
  29. u32 reserve2[2];
  30. u32 tctrl; /* 0x20 */
  31. #define TRAMODE_OFFSET 24
  32. #define TRAMODE_MASK (0x0F<<TRAMODE_OFFSET)
  33. #define TRAMODE_WR_SYNC (0<<TRAMODE_OFFSET)
  34. #define TRAMODE_WO (1<<TRAMODE_OFFSET)
  35. #define TRAMODE_RO (2<<TRAMODE_OFFSET)
  36. #define TRAMODE_WR (3<<TRAMODE_OFFSET)
  37. #define TRAMODE_RW (4<<TRAMODE_OFFSET)
  38. #define TRAMODE_WDR (5<<TRAMODE_OFFSET)
  39. #define TRAMODE_RDW (6<<TRAMODE_OFFSET)
  40. #define TRAMODE_NONE (7<<TRAMODE_OFFSET)
  41. #define TRAMODE_DW (8<<TRAMODE_OFFSET)
  42. #define TRAMODE_DR (9<<TRAMODE_OFFSET)
  43. #define WCNT_OFFSET 12
  44. #define WCNT_MASK (0x1FF<<WCNT_OFFSET)
  45. #define RCNT_OFFSET 0
  46. #define RCNT_MASK (0x1FF<<RCNT_OFFSET)
  47. u32 cmd;
  48. u32 addr;
  49. u32 data;
  50. u32 ctrl; /* 0x30 */
  51. #define TXFTH_OFFSET 16
  52. #define RXFTH_OFFSET 8
  53. #define TXDMAEN (1<<4)
  54. #define RXDMAEN (1<<3)
  55. #define TXFRST (1<<2)
  56. #define RXFRST (1<<1)
  57. #define SPIRST (1<<0)
  58. u32 status;
  59. #define TXFFL (1<<23)
  60. #define TXEPTY (1<<22)
  61. #define TXFVE_MASK (0x1F<<16)
  62. #define RXFEM (1<<14)
  63. #define RXFVE_OFFSET (8)
  64. #define RXFVE_MASK (0x1F<<RXFVE_OFFSET)
  65. #define SPIBSY (1<<0)
  66. u32 inten;
  67. u32 intsta;
  68. u32 timing; /* 0x40 */
  69. #define SCLK_DIV_MASK 0xFF
  70. };
  71. struct nds_spi_slave {
  72. volatile struct atcspi200_spi_regs *regs;
  73. int to;
  74. unsigned int freq;
  75. ulong clock;
  76. unsigned int mode;
  77. u8 num_cs;
  78. unsigned int mtiming;
  79. size_t cmd_len;
  80. u8 cmd_buf[16];
  81. size_t data_len;
  82. size_t tran_len;
  83. u8 *din;
  84. u8 *dout;
  85. unsigned int max_transfer_length;
  86. };
  87. static int __atcspi200_spi_set_speed(struct nds_spi_slave *ns)
  88. {
  89. u32 tm;
  90. u8 div;
  91. tm = ns->regs->timing;
  92. tm &= ~SCLK_DIV_MASK;
  93. if(ns->freq >= ns->clock)
  94. div =0xff;
  95. else{
  96. for (div = 0; div < 0xff; div++) {
  97. if (ns->freq >= ns->clock / (2 * (div + 1)))
  98. break;
  99. }
  100. }
  101. tm |= div;
  102. ns->regs->timing = tm;
  103. return 0;
  104. }
  105. static int __atcspi200_spi_claim_bus(struct nds_spi_slave *ns)
  106. {
  107. unsigned int format=0;
  108. ns->regs->ctrl |= (TXFRST|RXFRST|SPIRST);
  109. while((ns->regs->ctrl &(TXFRST|RXFRST|SPIRST))&&(ns->to--))
  110. if(!ns->to)
  111. return -EINVAL;
  112. ns->cmd_len = 0;
  113. format = ns->mode|DATA_LENGTH(8);
  114. ns->regs->format = format;
  115. __atcspi200_spi_set_speed(ns);
  116. return 0;
  117. }
  118. static int __atcspi200_spi_release_bus(struct nds_spi_slave *ns)
  119. {
  120. /* do nothing */
  121. return 0;
  122. }
  123. static int __atcspi200_spi_start(struct nds_spi_slave *ns)
  124. {
  125. int i,olen=0;
  126. int tc = ns->regs->tctrl;
  127. tc &= ~(WCNT_MASK|RCNT_MASK|TRAMODE_MASK);
  128. if ((ns->din)&&(ns->cmd_len))
  129. tc |= TRAMODE_WR;
  130. else if (ns->din)
  131. tc |= TRAMODE_RO;
  132. else
  133. tc |= TRAMODE_WO;
  134. if(ns->dout)
  135. olen = ns->tran_len;
  136. tc |= (ns->cmd_len+olen-1) << WCNT_OFFSET;
  137. if(ns->din)
  138. tc |= (ns->tran_len-1) << RCNT_OFFSET;
  139. ns->regs->tctrl = tc;
  140. ns->regs->cmd = 1;
  141. for (i=0;i<ns->cmd_len;i++)
  142. ns->regs->data = ns->cmd_buf[i];
  143. return 0;
  144. }
  145. static int __atcspi200_spi_stop(struct nds_spi_slave *ns)
  146. {
  147. ns->regs->timing = ns->mtiming;
  148. while ((ns->regs->status & SPIBSY)&&(ns->to--))
  149. if (!ns->to)
  150. return -EINVAL;
  151. return 0;
  152. }
  153. static void __nspi_espi_tx(struct nds_spi_slave *ns, const void *dout)
  154. {
  155. ns->regs->data = *(u8 *)dout;
  156. }
  157. static int __nspi_espi_rx(struct nds_spi_slave *ns, void *din, unsigned int bytes)
  158. {
  159. *(u8 *)din = ns->regs->data;
  160. return bytes;
  161. }
  162. static int __atcspi200_spi_xfer(struct nds_spi_slave *ns,
  163. unsigned int bitlen, const void *data_out, void *data_in,
  164. unsigned long flags)
  165. {
  166. unsigned int event, rx_bytes;
  167. const void *dout = NULL;
  168. void *din = NULL;
  169. int num_blks, num_chunks, max_tran_len, tran_len;
  170. int num_bytes;
  171. u8 *cmd_buf = ns->cmd_buf;
  172. size_t cmd_len = ns->cmd_len;
  173. unsigned long data_len = bitlen / 8;
  174. int rf_cnt;
  175. int ret = 0;
  176. max_tran_len = ns->max_transfer_length;
  177. switch (flags) {
  178. case SPI_XFER_BEGIN:
  179. cmd_len = ns->cmd_len = data_len;
  180. memcpy(cmd_buf, data_out, cmd_len);
  181. return 0;
  182. case 0:
  183. case SPI_XFER_END:
  184. if (bitlen == 0) {
  185. return 0;
  186. }
  187. ns->data_len = data_len;
  188. ns->din = (u8 *)data_in;
  189. ns->dout = (u8 *)data_out;
  190. break;
  191. case SPI_XFER_BEGIN | SPI_XFER_END:
  192. ns->data_len = 0;
  193. ns->din = 0;
  194. ns->dout = 0;
  195. cmd_len = ns->cmd_len = data_len;
  196. memcpy(cmd_buf, data_out, cmd_len);
  197. data_out = 0;
  198. data_len = 0;
  199. __atcspi200_spi_start(ns);
  200. break;
  201. }
  202. if (data_out)
  203. debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) data_len %lu\n",
  204. *(uint *)data_out, data_out, *(uint *)data_in,
  205. data_in, data_len);
  206. num_chunks = DIV_ROUND_UP(data_len, max_tran_len);
  207. din = data_in;
  208. dout = data_out;
  209. while (num_chunks--) {
  210. tran_len = min((size_t)data_len, (size_t)max_tran_len);
  211. ns->tran_len = tran_len;
  212. num_blks = DIV_ROUND_UP(tran_len , CHUNK_SIZE);
  213. num_bytes = (tran_len) % CHUNK_SIZE;
  214. if(num_bytes == 0)
  215. num_bytes = CHUNK_SIZE;
  216. __atcspi200_spi_start(ns);
  217. while (num_blks) {
  218. event = in_le32(&ns->regs->status);
  219. if ((event & TXEPTY) && (data_out)) {
  220. __nspi_espi_tx(ns, dout);
  221. num_blks -= CHUNK_SIZE;
  222. dout += CHUNK_SIZE;
  223. }
  224. if ((event & RXFVE_MASK) && (data_in)) {
  225. rf_cnt = ((event & RXFVE_MASK)>> RXFVE_OFFSET);
  226. if (rf_cnt >= CHUNK_SIZE)
  227. rx_bytes = CHUNK_SIZE;
  228. else if (num_blks == 1 && rf_cnt == num_bytes)
  229. rx_bytes = num_bytes;
  230. else
  231. continue;
  232. if (__nspi_espi_rx(ns, din, rx_bytes) == rx_bytes) {
  233. num_blks -= CHUNK_SIZE;
  234. din = (unsigned char *)din + rx_bytes;
  235. }
  236. }
  237. }
  238. data_len -= tran_len;
  239. if(data_len)
  240. {
  241. ns->cmd_buf[1] += ((tran_len>>16)&0xff);
  242. ns->cmd_buf[2] += ((tran_len>>8)&0xff);
  243. ns->cmd_buf[3] += ((tran_len)&0xff);
  244. ns->data_len = data_len;
  245. }
  246. ret = __atcspi200_spi_stop(ns);
  247. }
  248. ret = __atcspi200_spi_stop(ns);
  249. return ret;
  250. }
  251. static int atcspi200_spi_set_speed(struct udevice *bus, uint max_hz)
  252. {
  253. struct nds_spi_slave *ns = dev_get_priv(bus);
  254. debug("%s speed %u\n", __func__, max_hz);
  255. ns->freq = max_hz;
  256. __atcspi200_spi_set_speed(ns);
  257. return 0;
  258. }
  259. static int atcspi200_spi_set_mode(struct udevice *bus, uint mode)
  260. {
  261. struct nds_spi_slave *ns = dev_get_priv(bus);
  262. debug("%s mode %u\n", __func__, mode);
  263. ns->mode = mode;
  264. return 0;
  265. }
  266. static int atcspi200_spi_claim_bus(struct udevice *dev)
  267. {
  268. struct dm_spi_slave_platdata *slave_plat =
  269. dev_get_parent_platdata(dev);
  270. struct udevice *bus = dev->parent;
  271. struct nds_spi_slave *ns = dev_get_priv(bus);
  272. if (slave_plat->cs >= ns->num_cs) {
  273. printf("Invalid SPI chipselect\n");
  274. return -EINVAL;
  275. }
  276. return __atcspi200_spi_claim_bus(ns);
  277. }
  278. static int atcspi200_spi_release_bus(struct udevice *dev)
  279. {
  280. struct nds_spi_slave *ns = dev_get_priv(dev->parent);
  281. return __atcspi200_spi_release_bus(ns);
  282. }
  283. static int atcspi200_spi_xfer(struct udevice *dev, unsigned int bitlen,
  284. const void *dout, void *din,
  285. unsigned long flags)
  286. {
  287. struct udevice *bus = dev->parent;
  288. struct nds_spi_slave *ns = dev_get_priv(bus);
  289. return __atcspi200_spi_xfer(ns, bitlen, dout, din, flags);
  290. }
  291. static int atcspi200_spi_get_clk(struct udevice *bus)
  292. {
  293. struct nds_spi_slave *ns = dev_get_priv(bus);
  294. struct clk clk;
  295. ulong clk_rate;
  296. int ret;
  297. ret = clk_get_by_index(bus, 0, &clk);
  298. if (ret)
  299. return -EINVAL;
  300. clk_rate = clk_get_rate(&clk);
  301. if (!clk_rate)
  302. return -EINVAL;
  303. ns->clock = clk_rate;
  304. clk_free(&clk);
  305. return 0;
  306. }
  307. static int atcspi200_spi_probe(struct udevice *bus)
  308. {
  309. struct nds_spi_slave *ns = dev_get_priv(bus);
  310. ns->to = SPI_TIMEOUT;
  311. ns->max_transfer_length = MAX_TRANSFER_LEN;
  312. ns->mtiming = ns->regs->timing;
  313. atcspi200_spi_get_clk(bus);
  314. return 0;
  315. }
  316. static int atcspi200_ofdata_to_platadata(struct udevice *bus)
  317. {
  318. struct nds_spi_slave *ns = dev_get_priv(bus);
  319. const void *blob = gd->fdt_blob;
  320. int node = dev_of_offset(bus);
  321. ns->regs = map_physmem(devfdt_get_addr(bus),
  322. sizeof(struct atcspi200_spi_regs),
  323. MAP_NOCACHE);
  324. if (!ns->regs) {
  325. printf("%s: could not map device address\n", __func__);
  326. return -EINVAL;
  327. }
  328. ns->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
  329. return 0;
  330. }
  331. static const struct dm_spi_ops atcspi200_spi_ops = {
  332. .claim_bus = atcspi200_spi_claim_bus,
  333. .release_bus = atcspi200_spi_release_bus,
  334. .xfer = atcspi200_spi_xfer,
  335. .set_speed = atcspi200_spi_set_speed,
  336. .set_mode = atcspi200_spi_set_mode,
  337. };
  338. static const struct udevice_id atcspi200_spi_ids[] = {
  339. { .compatible = "andestech,atcspi200" },
  340. { }
  341. };
  342. U_BOOT_DRIVER(atcspi200_spi) = {
  343. .name = "atcspi200_spi",
  344. .id = UCLASS_SPI,
  345. .of_match = atcspi200_spi_ids,
  346. .ops = &atcspi200_spi_ops,
  347. .ofdata_to_platdata = atcspi200_ofdata_to_platadata,
  348. .priv_auto_alloc_size = sizeof(struct nds_spi_slave),
  349. .probe = atcspi200_spi_probe,
  350. };