serial_zynq.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
  4. * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
  5. */
  6. #include <clk.h>
  7. #include <common.h>
  8. #include <debug_uart.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <fdtdec.h>
  12. #include <watchdog.h>
  13. #include <asm/io.h>
  14. #include <dm/device_compat.h>
  15. #include <linux/compiler.h>
  16. #include <serial.h>
  17. #include <linux/err.h>
  18. #define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */
  19. #define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */
  20. #define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */
  21. #define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */
  22. #define ZYNQ_UART_CR_RX_EN BIT(2) /* RX enabled */
  23. #define ZYNQ_UART_CR_TXRST BIT(1) /* TX logic reset */
  24. #define ZYNQ_UART_CR_RXRST BIT(0) /* RX logic reset */
  25. #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
  26. struct uart_zynq {
  27. u32 control; /* 0x0 - Control Register [8:0] */
  28. u32 mode; /* 0x4 - Mode Register [10:0] */
  29. u32 reserved1[4];
  30. u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */
  31. u32 reserved2[4];
  32. u32 channel_sts; /* 0x2c - Channel Status [11:0] */
  33. u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */
  34. u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
  35. };
  36. struct zynq_uart_platdata {
  37. struct uart_zynq *regs;
  38. };
  39. /* Set up the baud rate */
  40. static void _uart_zynq_serial_setbrg(struct uart_zynq *regs,
  41. unsigned long clock, unsigned long baud)
  42. {
  43. /* Calculation results. */
  44. unsigned int calc_bauderror, bdiv, bgen;
  45. unsigned long calc_baud = 0;
  46. /* Covering case where input clock is so slow */
  47. if (clock < 1000000 && baud > 4800)
  48. baud = 4800;
  49. /* master clock
  50. * Baud rate = ------------------
  51. * bgen * (bdiv + 1)
  52. *
  53. * Find acceptable values for baud generation.
  54. */
  55. for (bdiv = 4; bdiv < 255; bdiv++) {
  56. bgen = clock / (baud * (bdiv + 1));
  57. if (bgen < 2 || bgen > 65535)
  58. continue;
  59. calc_baud = clock / (bgen * (bdiv + 1));
  60. /*
  61. * Use first calculated baudrate with
  62. * an acceptable (<3%) error
  63. */
  64. if (baud > calc_baud)
  65. calc_bauderror = baud - calc_baud;
  66. else
  67. calc_bauderror = calc_baud - baud;
  68. if (((calc_bauderror * 100) / baud) < 3)
  69. break;
  70. }
  71. writel(bdiv, &regs->baud_rate_divider);
  72. writel(bgen, &regs->baud_rate_gen);
  73. }
  74. /* Initialize the UART, with...some settings. */
  75. static void _uart_zynq_serial_init(struct uart_zynq *regs)
  76. {
  77. /* RX/TX enabled & reset */
  78. writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
  79. ZYNQ_UART_CR_RXRST, &regs->control);
  80. writel(ZYNQ_UART_MR_PARITY_NONE, &regs->mode); /* 8 bit, no parity */
  81. }
  82. static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
  83. {
  84. if (readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL)
  85. return -EAGAIN;
  86. writel(c, &regs->tx_rx_fifo);
  87. return 0;
  88. }
  89. static int zynq_serial_setbrg(struct udevice *dev, int baudrate)
  90. {
  91. struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
  92. unsigned long clock;
  93. int ret;
  94. struct clk clk;
  95. ret = clk_get_by_index(dev, 0, &clk);
  96. if (ret < 0) {
  97. dev_err(dev, "failed to get clock\n");
  98. return ret;
  99. }
  100. clock = clk_get_rate(&clk);
  101. if (IS_ERR_VALUE(clock)) {
  102. dev_err(dev, "failed to get rate\n");
  103. return clock;
  104. }
  105. debug("%s: CLK %ld\n", __func__, clock);
  106. ret = clk_enable(&clk);
  107. if (ret && ret != -ENOSYS) {
  108. dev_err(dev, "failed to enable clock\n");
  109. return ret;
  110. }
  111. _uart_zynq_serial_setbrg(platdata->regs, clock, baudrate);
  112. return 0;
  113. }
  114. static int zynq_serial_probe(struct udevice *dev)
  115. {
  116. struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
  117. struct uart_zynq *regs = platdata->regs;
  118. u32 val;
  119. /* No need to reinitialize the UART if TX already enabled */
  120. val = readl(&regs->control);
  121. if (val & ZYNQ_UART_CR_TX_EN)
  122. return 0;
  123. _uart_zynq_serial_init(platdata->regs);
  124. return 0;
  125. }
  126. static int zynq_serial_getc(struct udevice *dev)
  127. {
  128. struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
  129. struct uart_zynq *regs = platdata->regs;
  130. if (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY)
  131. return -EAGAIN;
  132. return readl(&regs->tx_rx_fifo);
  133. }
  134. static int zynq_serial_putc(struct udevice *dev, const char ch)
  135. {
  136. struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
  137. return _uart_zynq_serial_putc(platdata->regs, ch);
  138. }
  139. static int zynq_serial_pending(struct udevice *dev, bool input)
  140. {
  141. struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
  142. struct uart_zynq *regs = platdata->regs;
  143. if (input)
  144. return !(readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY);
  145. else
  146. return !!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXACTIVE);
  147. }
  148. static int zynq_serial_ofdata_to_platdata(struct udevice *dev)
  149. {
  150. struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
  151. platdata->regs = (struct uart_zynq *)dev_read_addr(dev);
  152. if (IS_ERR(platdata->regs))
  153. return PTR_ERR(platdata->regs);
  154. return 0;
  155. }
  156. static const struct dm_serial_ops zynq_serial_ops = {
  157. .putc = zynq_serial_putc,
  158. .pending = zynq_serial_pending,
  159. .getc = zynq_serial_getc,
  160. .setbrg = zynq_serial_setbrg,
  161. };
  162. static const struct udevice_id zynq_serial_ids[] = {
  163. { .compatible = "xlnx,xuartps" },
  164. { .compatible = "cdns,uart-r1p8" },
  165. { .compatible = "cdns,uart-r1p12" },
  166. { }
  167. };
  168. U_BOOT_DRIVER(serial_zynq) = {
  169. .name = "serial_zynq",
  170. .id = UCLASS_SERIAL,
  171. .of_match = zynq_serial_ids,
  172. .ofdata_to_platdata = zynq_serial_ofdata_to_platdata,
  173. .platdata_auto_alloc_size = sizeof(struct zynq_uart_platdata),
  174. .probe = zynq_serial_probe,
  175. .ops = &zynq_serial_ops,
  176. };
  177. #ifdef CONFIG_DEBUG_UART_ZYNQ
  178. static inline void _debug_uart_init(void)
  179. {
  180. struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
  181. _uart_zynq_serial_init(regs);
  182. _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
  183. CONFIG_BAUDRATE);
  184. }
  185. static inline void _debug_uart_putc(int ch)
  186. {
  187. struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
  188. while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)
  189. WATCHDOG_RESET();
  190. }
  191. DEBUG_UART_FUNCS
  192. #endif