serial_pl01x.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000
  4. * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
  5. *
  6. * (C) Copyright 2004
  7. * ARM Ltd.
  8. * Philippe Robin, <philippe.robin@arm.com>
  9. */
  10. /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <errno.h>
  14. #include <watchdog.h>
  15. #include <asm/io.h>
  16. #include <serial.h>
  17. #include <dm/platform_data/serial_pl01x.h>
  18. #include <linux/compiler.h>
  19. #include "serial_pl01x_internal.h"
  20. DECLARE_GLOBAL_DATA_PTR;
  21. #ifndef CONFIG_DM_SERIAL
  22. static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
  23. static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
  24. static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
  25. #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
  26. #endif
  27. static int pl01x_putc(struct pl01x_regs *regs, char c)
  28. {
  29. /* Wait until there is space in the FIFO */
  30. if (readl(&regs->fr) & UART_PL01x_FR_TXFF)
  31. return -EAGAIN;
  32. /* Send the character */
  33. writel(c, &regs->dr);
  34. return 0;
  35. }
  36. static int pl01x_getc(struct pl01x_regs *regs)
  37. {
  38. unsigned int data;
  39. /* Wait until there is data in the FIFO */
  40. if (readl(&regs->fr) & UART_PL01x_FR_RXFE)
  41. return -EAGAIN;
  42. data = readl(&regs->dr);
  43. /* Check for an error flag */
  44. if (data & 0xFFFFFF00) {
  45. /* Clear the error */
  46. writel(0xFFFFFFFF, &regs->ecr);
  47. return -1;
  48. }
  49. return (int) data;
  50. }
  51. static int pl01x_tstc(struct pl01x_regs *regs)
  52. {
  53. WATCHDOG_RESET();
  54. return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
  55. }
  56. static int pl01x_generic_serial_init(struct pl01x_regs *regs,
  57. enum pl01x_type type)
  58. {
  59. switch (type) {
  60. case TYPE_PL010:
  61. /* disable everything */
  62. writel(0, &regs->pl010_cr);
  63. break;
  64. case TYPE_PL011:
  65. /* disable everything */
  66. writel(0, &regs->pl011_cr);
  67. break;
  68. default:
  69. return -EINVAL;
  70. }
  71. return 0;
  72. }
  73. static int pl011_set_line_control(struct pl01x_regs *regs)
  74. {
  75. unsigned int lcr;
  76. /*
  77. * Internal update of baud rate register require line
  78. * control register write
  79. */
  80. lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
  81. writel(lcr, &regs->pl011_lcrh);
  82. return 0;
  83. }
  84. static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
  85. int clock, int baudrate)
  86. {
  87. switch (type) {
  88. case TYPE_PL010: {
  89. unsigned int divisor;
  90. /* disable everything */
  91. writel(0, &regs->pl010_cr);
  92. switch (baudrate) {
  93. case 9600:
  94. divisor = UART_PL010_BAUD_9600;
  95. break;
  96. case 19200:
  97. divisor = UART_PL010_BAUD_19200;
  98. break;
  99. case 38400:
  100. divisor = UART_PL010_BAUD_38400;
  101. break;
  102. case 57600:
  103. divisor = UART_PL010_BAUD_57600;
  104. break;
  105. case 115200:
  106. divisor = UART_PL010_BAUD_115200;
  107. break;
  108. default:
  109. divisor = UART_PL010_BAUD_38400;
  110. }
  111. writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
  112. writel(divisor & 0xff, &regs->pl010_lcrl);
  113. /*
  114. * Set line control for the PL010 to be 8 bits, 1 stop bit,
  115. * no parity, fifo enabled
  116. */
  117. writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN,
  118. &regs->pl010_lcrh);
  119. /* Finally, enable the UART */
  120. writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
  121. break;
  122. }
  123. case TYPE_PL011: {
  124. unsigned int temp;
  125. unsigned int divider;
  126. unsigned int remainder;
  127. unsigned int fraction;
  128. /*
  129. * Set baud rate
  130. *
  131. * IBRD = UART_CLK / (16 * BAUD_RATE)
  132. * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
  133. * / (16 * BAUD_RATE))
  134. */
  135. temp = 16 * baudrate;
  136. divider = clock / temp;
  137. remainder = clock % temp;
  138. temp = (8 * remainder) / baudrate;
  139. fraction = (temp >> 1) + (temp & 1);
  140. writel(divider, &regs->pl011_ibrd);
  141. writel(fraction, &regs->pl011_fbrd);
  142. pl011_set_line_control(regs);
  143. /* Finally, enable the UART */
  144. writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
  145. UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
  146. break;
  147. }
  148. default:
  149. return -EINVAL;
  150. }
  151. return 0;
  152. }
  153. #ifndef CONFIG_DM_SERIAL
  154. static void pl01x_serial_init_baud(int baudrate)
  155. {
  156. int clock = 0;
  157. #if defined(CONFIG_PL010_SERIAL)
  158. pl01x_type = TYPE_PL010;
  159. #elif defined(CONFIG_PL011_SERIAL)
  160. pl01x_type = TYPE_PL011;
  161. clock = CONFIG_PL011_CLOCK;
  162. #endif
  163. base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
  164. pl01x_generic_serial_init(base_regs, pl01x_type);
  165. pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
  166. }
  167. /*
  168. * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
  169. * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
  170. * Versatile PB has four UARTs.
  171. */
  172. int pl01x_serial_init(void)
  173. {
  174. pl01x_serial_init_baud(CONFIG_BAUDRATE);
  175. return 0;
  176. }
  177. static void pl01x_serial_putc(const char c)
  178. {
  179. if (c == '\n')
  180. while (pl01x_putc(base_regs, '\r') == -EAGAIN);
  181. while (pl01x_putc(base_regs, c) == -EAGAIN);
  182. }
  183. static int pl01x_serial_getc(void)
  184. {
  185. while (1) {
  186. int ch = pl01x_getc(base_regs);
  187. if (ch == -EAGAIN) {
  188. WATCHDOG_RESET();
  189. continue;
  190. }
  191. return ch;
  192. }
  193. }
  194. static int pl01x_serial_tstc(void)
  195. {
  196. return pl01x_tstc(base_regs);
  197. }
  198. static void pl01x_serial_setbrg(void)
  199. {
  200. /*
  201. * Flush FIFO and wait for non-busy before changing baudrate to avoid
  202. * crap in console
  203. */
  204. while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
  205. WATCHDOG_RESET();
  206. while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
  207. WATCHDOG_RESET();
  208. pl01x_serial_init_baud(gd->baudrate);
  209. }
  210. static struct serial_device pl01x_serial_drv = {
  211. .name = "pl01x_serial",
  212. .start = pl01x_serial_init,
  213. .stop = NULL,
  214. .setbrg = pl01x_serial_setbrg,
  215. .putc = pl01x_serial_putc,
  216. .puts = default_serial_puts,
  217. .getc = pl01x_serial_getc,
  218. .tstc = pl01x_serial_tstc,
  219. };
  220. void pl01x_serial_initialize(void)
  221. {
  222. serial_register(&pl01x_serial_drv);
  223. }
  224. __weak struct serial_device *default_serial_console(void)
  225. {
  226. return &pl01x_serial_drv;
  227. }
  228. #endif /* nCONFIG_DM_SERIAL */
  229. #ifdef CONFIG_DM_SERIAL
  230. int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
  231. {
  232. struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
  233. struct pl01x_priv *priv = dev_get_priv(dev);
  234. if (!plat->skip_init) {
  235. pl01x_generic_setbrg(priv->regs, priv->type, plat->clock,
  236. baudrate);
  237. }
  238. return 0;
  239. }
  240. int pl01x_serial_probe(struct udevice *dev)
  241. {
  242. struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
  243. struct pl01x_priv *priv = dev_get_priv(dev);
  244. priv->regs = (struct pl01x_regs *)plat->base;
  245. priv->type = plat->type;
  246. if (!plat->skip_init)
  247. return pl01x_generic_serial_init(priv->regs, priv->type);
  248. else
  249. return 0;
  250. }
  251. int pl01x_serial_getc(struct udevice *dev)
  252. {
  253. struct pl01x_priv *priv = dev_get_priv(dev);
  254. return pl01x_getc(priv->regs);
  255. }
  256. int pl01x_serial_putc(struct udevice *dev, const char ch)
  257. {
  258. struct pl01x_priv *priv = dev_get_priv(dev);
  259. return pl01x_putc(priv->regs, ch);
  260. }
  261. int pl01x_serial_pending(struct udevice *dev, bool input)
  262. {
  263. struct pl01x_priv *priv = dev_get_priv(dev);
  264. unsigned int fr = readl(&priv->regs->fr);
  265. if (input)
  266. return pl01x_tstc(priv->regs);
  267. else
  268. return fr & UART_PL01x_FR_TXFF ? 0 : 1;
  269. }
  270. static const struct dm_serial_ops pl01x_serial_ops = {
  271. .putc = pl01x_serial_putc,
  272. .pending = pl01x_serial_pending,
  273. .getc = pl01x_serial_getc,
  274. .setbrg = pl01x_serial_setbrg,
  275. };
  276. #if CONFIG_IS_ENABLED(OF_CONTROL)
  277. static const struct udevice_id pl01x_serial_id[] ={
  278. {.compatible = "arm,pl011", .data = TYPE_PL011},
  279. {.compatible = "arm,pl010", .data = TYPE_PL010},
  280. {}
  281. };
  282. int pl01x_serial_ofdata_to_platdata(struct udevice *dev)
  283. {
  284. struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
  285. fdt_addr_t addr;
  286. addr = devfdt_get_addr(dev);
  287. if (addr == FDT_ADDR_T_NONE)
  288. return -EINVAL;
  289. plat->base = addr;
  290. plat->clock = dev_read_u32_default(dev, "clock", 1);
  291. plat->type = dev_get_driver_data(dev);
  292. plat->skip_init = dev_read_bool(dev, "skip-init");
  293. return 0;
  294. }
  295. #endif
  296. U_BOOT_DRIVER(serial_pl01x) = {
  297. .name = "serial_pl01x",
  298. .id = UCLASS_SERIAL,
  299. .of_match = of_match_ptr(pl01x_serial_id),
  300. .ofdata_to_platdata = of_match_ptr(pl01x_serial_ofdata_to_platdata),
  301. .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
  302. .probe = pl01x_serial_probe,
  303. .ops = &pl01x_serial_ops,
  304. .flags = DM_FLAG_PRE_RELOC,
  305. .priv_auto_alloc_size = sizeof(struct pl01x_priv),
  306. };
  307. #endif
  308. #if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011)
  309. #include <debug_uart.h>
  310. static void _debug_uart_init(void)
  311. {
  312. #ifndef CONFIG_DEBUG_UART_SKIP_INIT
  313. struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
  314. enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ?
  315. TYPE_PL011 : TYPE_PL010;
  316. pl01x_generic_serial_init(regs, type);
  317. pl01x_generic_setbrg(regs, type,
  318. CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
  319. #endif
  320. }
  321. static inline void _debug_uart_putc(int ch)
  322. {
  323. struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
  324. pl01x_putc(regs, ch);
  325. }
  326. DEBUG_UART_FUNCS
  327. #endif