serial_mtk.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MediaTek High-speed UART driver
  4. *
  5. * Copyright (C) 2018 MediaTek Inc.
  6. * Author: Weijie Gao <weijie.gao@mediatek.com>
  7. */
  8. #include <clk.h>
  9. #include <common.h>
  10. #include <div64.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <serial.h>
  14. #include <watchdog.h>
  15. #include <asm/io.h>
  16. #include <asm/types.h>
  17. #include <linux/err.h>
  18. struct mtk_serial_regs {
  19. u32 rbr;
  20. u32 ier;
  21. u32 fcr;
  22. u32 lcr;
  23. u32 mcr;
  24. u32 lsr;
  25. u32 msr;
  26. u32 spr;
  27. u32 mdr1;
  28. u32 highspeed;
  29. u32 sample_count;
  30. u32 sample_point;
  31. u32 fracdiv_l;
  32. u32 fracdiv_m;
  33. u32 escape_en;
  34. u32 guard;
  35. u32 rx_sel;
  36. };
  37. #define thr rbr
  38. #define iir fcr
  39. #define dll rbr
  40. #define dlm ier
  41. #define UART_LCR_WLS_8 0x03 /* 8 bit character length */
  42. #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
  43. #define UART_LSR_DR 0x01 /* Data ready */
  44. #define UART_LSR_THRE 0x20 /* Xmit holding register empty */
  45. #define UART_LSR_TEMT 0x40 /* Xmitter empty */
  46. #define UART_MCR_DTR 0x01 /* DTR */
  47. #define UART_MCR_RTS 0x02 /* RTS */
  48. #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
  49. #define UART_FCR_RXSR 0x02 /* Receiver soft reset */
  50. #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
  51. #define UART_MCRVAL (UART_MCR_DTR | \
  52. UART_MCR_RTS)
  53. /* Clear & enable FIFOs */
  54. #define UART_FCRVAL (UART_FCR_FIFO_EN | \
  55. UART_FCR_RXSR | \
  56. UART_FCR_TXSR)
  57. /* the data is correct if the real baud is within 3%. */
  58. #define BAUD_ALLOW_MAX(baud) ((baud) + (baud) * 3 / 100)
  59. #define BAUD_ALLOW_MIX(baud) ((baud) - (baud) * 3 / 100)
  60. struct mtk_serial_priv {
  61. struct mtk_serial_regs __iomem *regs;
  62. u32 clock;
  63. };
  64. static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud)
  65. {
  66. bool support_clk12m_baud115200;
  67. u32 quot, samplecount, realbaud;
  68. if ((baud <= 115200) && (priv->clock == 12000000))
  69. support_clk12m_baud115200 = true;
  70. else
  71. support_clk12m_baud115200 = false;
  72. if (baud <= 115200) {
  73. writel(0, &priv->regs->highspeed);
  74. quot = DIV_ROUND_CLOSEST(priv->clock, 16 * baud);
  75. if (support_clk12m_baud115200) {
  76. writel(3, &priv->regs->highspeed);
  77. quot = DIV_ROUND_CLOSEST(priv->clock, 256 * baud);
  78. if (quot == 0)
  79. quot = 1;
  80. samplecount = DIV_ROUND_CLOSEST(priv->clock,
  81. quot * baud);
  82. if (samplecount != 0) {
  83. realbaud = priv->clock / samplecount / quot;
  84. if ((realbaud > BAUD_ALLOW_MAX(baud)) ||
  85. (realbaud < BAUD_ALLOW_MIX(baud))) {
  86. pr_info("baud %d can't be handled\n",
  87. baud);
  88. }
  89. } else {
  90. pr_info("samplecount is 0\n");
  91. }
  92. }
  93. } else if (baud <= 576000) {
  94. writel(2, &priv->regs->highspeed);
  95. /* Set to next lower baudrate supported */
  96. if ((baud == 500000) || (baud == 576000))
  97. baud = 460800;
  98. quot = DIV_ROUND_UP(priv->clock, 4 * baud);
  99. } else {
  100. writel(3, &priv->regs->highspeed);
  101. quot = DIV_ROUND_UP(priv->clock, 256 * baud);
  102. }
  103. /* set divisor */
  104. writel(UART_LCR_WLS_8 | UART_LCR_DLAB, &priv->regs->lcr);
  105. writel(quot & 0xff, &priv->regs->dll);
  106. writel((quot >> 8) & 0xff, &priv->regs->dlm);
  107. writel(UART_LCR_WLS_8, &priv->regs->lcr);
  108. if (baud > 460800) {
  109. u32 tmp;
  110. tmp = DIV_ROUND_CLOSEST(priv->clock, quot * baud);
  111. writel(tmp - 1, &priv->regs->sample_count);
  112. writel((tmp - 2) >> 1, &priv->regs->sample_point);
  113. } else {
  114. writel(0, &priv->regs->sample_count);
  115. writel(0xff, &priv->regs->sample_point);
  116. }
  117. if (support_clk12m_baud115200) {
  118. writel(samplecount - 1, &priv->regs->sample_count);
  119. writel((samplecount - 2) >> 1, &priv->regs->sample_point);
  120. }
  121. }
  122. static int _mtk_serial_putc(struct mtk_serial_priv *priv, const char ch)
  123. {
  124. if (!(readl(&priv->regs->lsr) & UART_LSR_THRE))
  125. return -EAGAIN;
  126. writel(ch, &priv->regs->thr);
  127. if (ch == '\n')
  128. WATCHDOG_RESET();
  129. return 0;
  130. }
  131. static int _mtk_serial_getc(struct mtk_serial_priv *priv)
  132. {
  133. if (!(readl(&priv->regs->lsr) & UART_LSR_DR))
  134. return -EAGAIN;
  135. return readl(&priv->regs->rbr);
  136. }
  137. static int _mtk_serial_pending(struct mtk_serial_priv *priv, bool input)
  138. {
  139. if (input)
  140. return (readl(&priv->regs->lsr) & UART_LSR_DR) ? 1 : 0;
  141. else
  142. return (readl(&priv->regs->lsr) & UART_LSR_THRE) ? 0 : 1;
  143. }
  144. #if defined(CONFIG_DM_SERIAL) && \
  145. (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_DM))
  146. static int mtk_serial_setbrg(struct udevice *dev, int baudrate)
  147. {
  148. struct mtk_serial_priv *priv = dev_get_priv(dev);
  149. _mtk_serial_setbrg(priv, baudrate);
  150. return 0;
  151. }
  152. static int mtk_serial_putc(struct udevice *dev, const char ch)
  153. {
  154. struct mtk_serial_priv *priv = dev_get_priv(dev);
  155. return _mtk_serial_putc(priv, ch);
  156. }
  157. static int mtk_serial_getc(struct udevice *dev)
  158. {
  159. struct mtk_serial_priv *priv = dev_get_priv(dev);
  160. return _mtk_serial_getc(priv);
  161. }
  162. static int mtk_serial_pending(struct udevice *dev, bool input)
  163. {
  164. struct mtk_serial_priv *priv = dev_get_priv(dev);
  165. return _mtk_serial_pending(priv, input);
  166. }
  167. static int mtk_serial_probe(struct udevice *dev)
  168. {
  169. struct mtk_serial_priv *priv = dev_get_priv(dev);
  170. /* Disable interrupt */
  171. writel(0, &priv->regs->ier);
  172. writel(UART_MCRVAL, &priv->regs->mcr);
  173. writel(UART_FCRVAL, &priv->regs->fcr);
  174. return 0;
  175. }
  176. static int mtk_serial_ofdata_to_platdata(struct udevice *dev)
  177. {
  178. struct mtk_serial_priv *priv = dev_get_priv(dev);
  179. fdt_addr_t addr;
  180. struct clk clk;
  181. int err;
  182. addr = dev_read_addr(dev);
  183. if (addr == FDT_ADDR_T_NONE)
  184. return -EINVAL;
  185. priv->regs = map_physmem(addr, 0, MAP_NOCACHE);
  186. err = clk_get_by_index(dev, 0, &clk);
  187. if (!err) {
  188. err = clk_get_rate(&clk);
  189. if (!IS_ERR_VALUE(err))
  190. priv->clock = err;
  191. } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
  192. debug("mtk_serial: failed to get clock\n");
  193. return err;
  194. }
  195. if (!priv->clock)
  196. priv->clock = dev_read_u32_default(dev, "clock-frequency", 0);
  197. if (!priv->clock) {
  198. debug("mtk_serial: clock not defined\n");
  199. return -EINVAL;
  200. }
  201. return 0;
  202. }
  203. static const struct dm_serial_ops mtk_serial_ops = {
  204. .putc = mtk_serial_putc,
  205. .pending = mtk_serial_pending,
  206. .getc = mtk_serial_getc,
  207. .setbrg = mtk_serial_setbrg,
  208. };
  209. static const struct udevice_id mtk_serial_ids[] = {
  210. { .compatible = "mediatek,hsuart" },
  211. { .compatible = "mediatek,mt6577-uart" },
  212. { }
  213. };
  214. U_BOOT_DRIVER(serial_mtk) = {
  215. .name = "serial_mtk",
  216. .id = UCLASS_SERIAL,
  217. .of_match = mtk_serial_ids,
  218. .ofdata_to_platdata = mtk_serial_ofdata_to_platdata,
  219. .priv_auto_alloc_size = sizeof(struct mtk_serial_priv),
  220. .probe = mtk_serial_probe,
  221. .ops = &mtk_serial_ops,
  222. .flags = DM_FLAG_PRE_RELOC,
  223. };
  224. #else
  225. DECLARE_GLOBAL_DATA_PTR;
  226. #define DECLARE_HSUART_PRIV(port) \
  227. static struct mtk_serial_priv mtk_hsuart##port = { \
  228. .regs = (struct mtk_serial_regs *)CONFIG_SYS_NS16550_COM##port, \
  229. .clock = CONFIG_SYS_NS16550_CLK \
  230. };
  231. #define DECLARE_HSUART_FUNCTIONS(port) \
  232. static int mtk_serial##port##_init(void) \
  233. { \
  234. writel(0, &mtk_hsuart##port.regs->ier); \
  235. writel(UART_MCRVAL, &mtk_hsuart##port.regs->mcr); \
  236. writel(UART_FCRVAL, &mtk_hsuart##port.regs->fcr); \
  237. _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \
  238. return 0 ; \
  239. } \
  240. static void mtk_serial##port##_setbrg(void) \
  241. { \
  242. _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \
  243. } \
  244. static int mtk_serial##port##_getc(void) \
  245. { \
  246. int err; \
  247. do { \
  248. err = _mtk_serial_getc(&mtk_hsuart##port); \
  249. if (err == -EAGAIN) \
  250. WATCHDOG_RESET(); \
  251. } while (err == -EAGAIN); \
  252. return err >= 0 ? err : 0; \
  253. } \
  254. static int mtk_serial##port##_tstc(void) \
  255. { \
  256. return _mtk_serial_pending(&mtk_hsuart##port, true); \
  257. } \
  258. static void mtk_serial##port##_putc(const char c) \
  259. { \
  260. int err; \
  261. if (c == '\n') \
  262. mtk_serial##port##_putc('\r'); \
  263. do { \
  264. err = _mtk_serial_putc(&mtk_hsuart##port, c); \
  265. } while (err == -EAGAIN); \
  266. } \
  267. static void mtk_serial##port##_puts(const char *s) \
  268. { \
  269. while (*s) { \
  270. mtk_serial##port##_putc(*s++); \
  271. } \
  272. }
  273. /* Serial device descriptor */
  274. #define INIT_HSUART_STRUCTURE(port, __name) { \
  275. .name = __name, \
  276. .start = mtk_serial##port##_init, \
  277. .stop = NULL, \
  278. .setbrg = mtk_serial##port##_setbrg, \
  279. .getc = mtk_serial##port##_getc, \
  280. .tstc = mtk_serial##port##_tstc, \
  281. .putc = mtk_serial##port##_putc, \
  282. .puts = mtk_serial##port##_puts, \
  283. }
  284. #define DECLARE_HSUART(port, __name) \
  285. DECLARE_HSUART_PRIV(port); \
  286. DECLARE_HSUART_FUNCTIONS(port); \
  287. struct serial_device mtk_hsuart##port##_device = \
  288. INIT_HSUART_STRUCTURE(port, __name);
  289. #if !defined(CONFIG_CONS_INDEX)
  290. #elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 6)
  291. #error "Invalid console index value."
  292. #endif
  293. #if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1)
  294. #error "Console port 1 defined but not configured."
  295. #elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2)
  296. #error "Console port 2 defined but not configured."
  297. #elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3)
  298. #error "Console port 3 defined but not configured."
  299. #elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4)
  300. #error "Console port 4 defined but not configured."
  301. #elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5)
  302. #error "Console port 5 defined but not configured."
  303. #elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6)
  304. #error "Console port 6 defined but not configured."
  305. #endif
  306. #if defined(CONFIG_SYS_NS16550_COM1)
  307. DECLARE_HSUART(1, "mtk-hsuart0");
  308. #endif
  309. #if defined(CONFIG_SYS_NS16550_COM2)
  310. DECLARE_HSUART(2, "mtk-hsuart1");
  311. #endif
  312. #if defined(CONFIG_SYS_NS16550_COM3)
  313. DECLARE_HSUART(3, "mtk-hsuart2");
  314. #endif
  315. #if defined(CONFIG_SYS_NS16550_COM4)
  316. DECLARE_HSUART(4, "mtk-hsuart3");
  317. #endif
  318. #if defined(CONFIG_SYS_NS16550_COM5)
  319. DECLARE_HSUART(5, "mtk-hsuart4");
  320. #endif
  321. #if defined(CONFIG_SYS_NS16550_COM6)
  322. DECLARE_HSUART(6, "mtk-hsuart5");
  323. #endif
  324. __weak struct serial_device *default_serial_console(void)
  325. {
  326. #if CONFIG_CONS_INDEX == 1
  327. return &mtk_hsuart1_device;
  328. #elif CONFIG_CONS_INDEX == 2
  329. return &mtk_hsuart2_device;
  330. #elif CONFIG_CONS_INDEX == 3
  331. return &mtk_hsuart3_device;
  332. #elif CONFIG_CONS_INDEX == 4
  333. return &mtk_hsuart4_device;
  334. #elif CONFIG_CONS_INDEX == 5
  335. return &mtk_hsuart5_device;
  336. #elif CONFIG_CONS_INDEX == 6
  337. return &mtk_hsuart6_device;
  338. #else
  339. #error "Bad CONFIG_CONS_INDEX."
  340. #endif
  341. }
  342. void mtk_serial_initialize(void)
  343. {
  344. #if defined(CONFIG_SYS_NS16550_COM1)
  345. serial_register(&mtk_hsuart1_device);
  346. #endif
  347. #if defined(CONFIG_SYS_NS16550_COM2)
  348. serial_register(&mtk_hsuart2_device);
  349. #endif
  350. #if defined(CONFIG_SYS_NS16550_COM3)
  351. serial_register(&mtk_hsuart3_device);
  352. #endif
  353. #if defined(CONFIG_SYS_NS16550_COM4)
  354. serial_register(&mtk_hsuart4_device);
  355. #endif
  356. #if defined(CONFIG_SYS_NS16550_COM5)
  357. serial_register(&mtk_hsuart5_device);
  358. #endif
  359. #if defined(CONFIG_SYS_NS16550_COM6)
  360. serial_register(&mtk_hsuart6_device);
  361. #endif
  362. }
  363. #endif
  364. #ifdef CONFIG_DEBUG_UART_MTK
  365. #include <debug_uart.h>
  366. static inline void _debug_uart_init(void)
  367. {
  368. struct mtk_serial_priv priv;
  369. priv.regs = (void *) CONFIG_DEBUG_UART_BASE;
  370. priv.clock = CONFIG_DEBUG_UART_CLOCK;
  371. writel(0, &priv.regs->ier);
  372. writel(UART_MCRVAL, &priv.regs->mcr);
  373. writel(UART_FCRVAL, &priv.regs->fcr);
  374. _mtk_serial_setbrg(&priv, CONFIG_BAUDRATE);
  375. }
  376. static inline void _debug_uart_putc(int ch)
  377. {
  378. struct mtk_serial_regs __iomem *regs =
  379. (void *) CONFIG_DEBUG_UART_BASE;
  380. while (!(readl(&regs->lsr) & UART_LSR_THRE))
  381. ;
  382. writel(ch, &regs->thr);
  383. }
  384. DEBUG_UART_FUNCS
  385. #endif