serial_mpc8xx.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <dm.h>
  9. #include <serial.h>
  10. #include <watchdog.h>
  11. #include <asm/cpm_8xx.h>
  12. #include <linux/compiler.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
  15. #define SMC_INDEX 0
  16. #define PROFF_SMC PROFF_SMC1
  17. #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
  18. #define IOPINS 0xc0
  19. #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
  20. #define SMC_INDEX 1
  21. #define PROFF_SMC PROFF_SMC2
  22. #define CPM_CR_CH_SMC CPM_CR_CH_SMC2
  23. #define IOPINS 0xc00
  24. #endif /* CONFIG_8xx_CONS_SMCx */
  25. struct serialbuffer {
  26. cbd_t rxbd; /* Rx BD */
  27. cbd_t txbd; /* Tx BD */
  28. uint rxindex; /* index for next character to read */
  29. uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
  30. uchar txbuf; /* tx buffers */
  31. };
  32. static void serial_setdivisor(cpm8xx_t __iomem *cp, int baudrate)
  33. {
  34. int divisor = (gd->cpu_clk + 8 * baudrate) / 16 / baudrate;
  35. if (divisor / 16 > 0x1000) {
  36. /* bad divisor, assume 50MHz clock and 9600 baud */
  37. divisor = (50 * 1000 * 1000 + 8 * 9600) / 16 / 9600;
  38. }
  39. divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
  40. if (divisor <= 0x1000)
  41. out_be32(&cp->cp_brgc1, ((divisor - 1) << 1) | CPM_BRG_EN);
  42. else
  43. out_be32(&cp->cp_brgc1, ((divisor / 16 - 1) << 1) | CPM_BRG_EN |
  44. CPM_BRG_DIV16);
  45. }
  46. /*
  47. * Minimal serial functions needed to use one of the SMC ports
  48. * as serial console interface.
  49. */
  50. static int serial_mpc8xx_setbrg(struct udevice *dev, int baudrate)
  51. {
  52. immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
  53. cpm8xx_t __iomem *cp = &(im->im_cpm);
  54. /* Set up the baud rate generator.
  55. * See 8xx_io/commproc.c for details.
  56. *
  57. * Wire BRG1 to SMCx
  58. */
  59. out_be32(&cp->cp_simode, 0);
  60. serial_setdivisor(cp, baudrate);
  61. return 0;
  62. }
  63. static int serial_mpc8xx_probe(struct udevice *dev)
  64. {
  65. immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
  66. smc_t __iomem *sp;
  67. smc_uart_t __iomem *up;
  68. cpm8xx_t __iomem *cp = &(im->im_cpm);
  69. struct serialbuffer __iomem *rtx;
  70. /* initialize pointers to SMC */
  71. sp = cp->cp_smc + SMC_INDEX;
  72. up = (smc_uart_t __iomem *)&cp->cp_dparam[PROFF_SMC];
  73. /* Disable relocation */
  74. out_be16(&up->smc_rpbase, 0);
  75. /* Disable transmitter/receiver. */
  76. clrbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
  77. /* Enable SDMA. */
  78. out_be32(&im->im_siu_conf.sc_sdcr, 1);
  79. /* clear error conditions */
  80. out_8(&im->im_sdma.sdma_sdsr, CONFIG_SYS_SDSR);
  81. /* clear SDMA interrupt mask */
  82. out_8(&im->im_sdma.sdma_sdmr, CONFIG_SYS_SDMR);
  83. /* Use Port B for SMCx instead of other functions. */
  84. setbits_be32(&cp->cp_pbpar, IOPINS);
  85. clrbits_be32(&cp->cp_pbdir, IOPINS);
  86. clrbits_be16(&cp->cp_pbodr, IOPINS);
  87. /* Set the physical address of the host memory buffers in
  88. * the buffer descriptors.
  89. */
  90. rtx = (struct serialbuffer __iomem *)&cp->cp_dpmem[CPM_SERIAL_BASE];
  91. /* Allocate space for two buffer descriptors in the DP ram.
  92. * For now, this address seems OK, but it may have to
  93. * change with newer versions of the firmware.
  94. * damm: allocating space after the two buffers for rx/tx data
  95. */
  96. out_be32(&rtx->rxbd.cbd_bufaddr, (__force uint)&rtx->rxbuf);
  97. out_be16(&rtx->rxbd.cbd_sc, 0);
  98. out_be32(&rtx->txbd.cbd_bufaddr, (__force uint)&rtx->txbuf);
  99. out_be16(&rtx->txbd.cbd_sc, 0);
  100. /* Set up the uart parameters in the parameter ram. */
  101. out_be16(&up->smc_rbase, CPM_SERIAL_BASE);
  102. out_be16(&up->smc_tbase, CPM_SERIAL_BASE + sizeof(cbd_t));
  103. out_8(&up->smc_rfcr, SMC_EB);
  104. out_8(&up->smc_tfcr, SMC_EB);
  105. /* Set UART mode, 8 bit, no parity, one stop.
  106. * Enable receive and transmit.
  107. */
  108. out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);
  109. /* Mask all interrupts and remove anything pending.
  110. */
  111. out_8(&sp->smc_smcm, 0);
  112. out_8(&sp->smc_smce, 0xff);
  113. /* Set up the baud rate generator */
  114. serial_mpc8xx_setbrg(dev, gd->baudrate);
  115. /* Make the first buffer the only buffer. */
  116. setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP);
  117. setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
  118. /* single/multi character receive. */
  119. out_be16(&up->smc_mrblr, CONFIG_SYS_SMC_RXBUFLEN);
  120. out_be16(&up->smc_maxidl, CONFIG_SYS_MAXIDLE);
  121. out_be32(&rtx->rxindex, 0);
  122. /* Initialize Tx/Rx parameters. */
  123. while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) /* wait if cp is busy */
  124. ;
  125. out_be16(&cp->cp_cpcr,
  126. mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG);
  127. while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) /* wait if cp is busy */
  128. ;
  129. /* Enable transmitter/receiver. */
  130. setbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
  131. return 0;
  132. }
  133. static int serial_mpc8xx_putc(struct udevice *dev, const char c)
  134. {
  135. immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
  136. cpm8xx_t __iomem *cpmp = &(im->im_cpm);
  137. struct serialbuffer __iomem *rtx;
  138. if (c == '\n')
  139. serial_mpc8xx_putc(dev, '\r');
  140. rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
  141. /* Wait for last character to go. */
  142. out_8(&rtx->txbuf, c);
  143. out_be16(&rtx->txbd.cbd_datlen, 1);
  144. setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY);
  145. while (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
  146. WATCHDOG_RESET();
  147. return 0;
  148. }
  149. static int serial_mpc8xx_getc(struct udevice *dev)
  150. {
  151. immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
  152. cpm8xx_t __iomem *cpmp = &(im->im_cpm);
  153. struct serialbuffer __iomem *rtx;
  154. unsigned char c;
  155. uint rxindex;
  156. rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
  157. /* Wait for character to show up. */
  158. while (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
  159. WATCHDOG_RESET();
  160. /* the characters are read one by one,
  161. * use the rxindex to know the next char to deliver
  162. */
  163. rxindex = in_be32(&rtx->rxindex);
  164. c = in_8(rtx->rxbuf + rxindex);
  165. rxindex++;
  166. /* check if all char are readout, then make prepare for next receive */
  167. if (rxindex >= in_be16(&rtx->rxbd.cbd_datlen)) {
  168. rxindex = 0;
  169. setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY);
  170. }
  171. out_be32(&rtx->rxindex, rxindex);
  172. return c;
  173. }
  174. static int serial_mpc8xx_pending(struct udevice *dev, bool input)
  175. {
  176. immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
  177. cpm8xx_t __iomem *cpmp = &(im->im_cpm);
  178. struct serialbuffer __iomem *rtx;
  179. if (!input)
  180. return 0;
  181. rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
  182. return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY);
  183. }
  184. static const struct dm_serial_ops serial_mpc8xx_ops = {
  185. .putc = serial_mpc8xx_putc,
  186. .pending = serial_mpc8xx_pending,
  187. .getc = serial_mpc8xx_getc,
  188. .setbrg = serial_mpc8xx_setbrg,
  189. };
  190. static const struct udevice_id serial_mpc8xx_ids[] = {
  191. { .compatible = "fsl,pq1-smc" },
  192. { }
  193. };
  194. U_BOOT_DRIVER(serial_mpc8xx) = {
  195. .name = "serial_mpc8xx",
  196. .id = UCLASS_SERIAL,
  197. .of_match = serial_mpc8xx_ids,
  198. .probe = serial_mpc8xx_probe,
  199. .ops = &serial_mpc8xx_ops,
  200. .flags = DM_FLAG_PRE_RELOC,
  201. };