mpc83xx_sdram.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018
  4. * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <init.h>
  9. #include <ram.h>
  10. #include <dt-bindings/memory/mpc83xx-sdram.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. /* Masks for the CS config register */
  13. static const u32 CSCONFIG_ENABLE = 0x80000000;
  14. static const u32 BANK_BITS_2;
  15. static const u32 BANK_BITS_3 = 0x00004000;
  16. static const u32 ROW_BITS_12;
  17. static const u32 ROW_BITS_13 = 0x00000100;
  18. static const u32 ROW_BITS_14 = 0x00000200;
  19. static const u32 COL_BITS_8;
  20. static const u32 COL_BITS_9 = 0x00000001;
  21. static const u32 COL_BITS_10 = 0x00000002;
  22. static const u32 COL_BITS_11 = 0x00000003;
  23. /* Shifts for the DDR SDRAM Timing Configuration 3 register */
  24. static const uint TIMING_CFG3_EXT_REFREC_SHIFT = (31 - 15);
  25. /* Shifts for the DDR SDRAM Timing Configuration 0 register */
  26. static const uint TIMING_CFG0_RWT_SHIFT = (31 - 1);
  27. static const uint TIMING_CFG0_WRT_SHIFT = (31 - 3);
  28. static const uint TIMING_CFG0_RRT_SHIFT = (31 - 5);
  29. static const uint TIMING_CFG0_WWT_SHIFT = (31 - 7);
  30. static const uint TIMING_CFG0_ACT_PD_EXIT_SHIFT = (31 - 11);
  31. static const uint TIMING_CFG0_PRE_PD_EXIT_SHIFT = (31 - 15);
  32. static const uint TIMING_CFG0_ODT_PD_EXIT_SHIFT = (31 - 23);
  33. static const uint TIMING_CFG0_MRS_CYC_SHIFT = (31 - 31);
  34. /* Shifts for the DDR SDRAM Timing Configuration 1 register */
  35. static const uint TIMING_CFG1_PRETOACT_SHIFT = (31 - 3);
  36. static const uint TIMING_CFG1_ACTTOPRE_SHIFT = (31 - 7);
  37. static const uint TIMING_CFG1_ACTTORW_SHIFT = (31 - 11);
  38. static const uint TIMING_CFG1_CASLAT_SHIFT = (31 - 15);
  39. static const uint TIMING_CFG1_REFREC_SHIFT = (31 - 19);
  40. static const uint TIMING_CFG1_WRREC_SHIFT = (31 - 23);
  41. static const uint TIMING_CFG1_ACTTOACT_SHIFT = (31 - 27);
  42. static const uint TIMING_CFG1_WRTORD_SHIFT = (31 - 31);
  43. /* Shifts for the DDR SDRAM Timing Configuration 2 register */
  44. static const uint TIMING_CFG2_CPO_SHIFT = (31 - 8);
  45. static const uint TIMING_CFG2_WR_DATA_DELAY_SHIFT = (31 - 21);
  46. static const uint TIMING_CFG2_ADD_LAT_SHIFT = (31 - 3);
  47. static const uint TIMING_CFG2_WR_LAT_DELAY_SHIFT = (31 - 12);
  48. static const uint TIMING_CFG2_RD_TO_PRE_SHIFT = (31 - 18);
  49. static const uint TIMING_CFG2_CKE_PLS_SHIFT = (31 - 25);
  50. static const uint TIMING_CFG2_FOUR_ACT_SHIFT;
  51. /* Shifts for the DDR SDRAM Control Configuration register */
  52. static const uint SDRAM_CFG_SREN_SHIFT = (31 - 1);
  53. static const uint SDRAM_CFG_ECC_EN_SHIFT = (31 - 2);
  54. static const uint SDRAM_CFG_RD_EN_SHIFT = (31 - 3);
  55. static const uint SDRAM_CFG_SDRAM_TYPE_SHIFT = (31 - 7);
  56. static const uint SDRAM_CFG_DYN_PWR_SHIFT = (31 - 10);
  57. static const uint SDRAM_CFG_DBW_SHIFT = (31 - 12);
  58. static const uint SDRAM_CFG_NCAP_SHIFT = (31 - 14);
  59. static const uint SDRAM_CFG_2T_EN_SHIFT = (31 - 16);
  60. static const uint SDRAM_CFG_BA_INTLV_CTL_SHIFT = (31 - 23);
  61. static const uint SDRAM_CFG_PCHB8_SHIFT = (31 - 27);
  62. static const uint SDRAM_CFG_HSE_SHIFT = (31 - 28);
  63. static const uint SDRAM_CFG_BI_SHIFT = (31 - 31);
  64. /* Shifts for the DDR SDRAM Control Configuration 2 register */
  65. static const uint SDRAM_CFG2_FRC_SR_SHIFT = (31 - 0);
  66. static const uint SDRAM_CFG2_DLL_RST_DIS = (31 - 2);
  67. static const uint SDRAM_CFG2_DQS_CFG = (31 - 5);
  68. static const uint SDRAM_CFG2_ODT_CFG = (31 - 10);
  69. static const uint SDRAM_CFG2_NUM_PR = (31 - 19);
  70. /* Shifts for the DDR SDRAM Mode register */
  71. static const uint SDRAM_MODE_ESD_SHIFT = (31 - 15);
  72. static const uint SDRAM_MODE_SD_SHIFT = (31 - 31);
  73. /* Shifts for the DDR SDRAM Mode 2 register */
  74. static const uint SDRAM_MODE2_ESD2_SHIFT = (31 - 15);
  75. static const uint SDRAM_MODE2_ESD3_SHIFT = (31 - 31);
  76. /* Shifts for the DDR SDRAM Interval Configuration register */
  77. static const uint SDRAM_INTERVAL_REFINT_SHIFT = (31 - 15);
  78. static const uint SDRAM_INTERVAL_BSTOPRE_SHIFT = (31 - 31);
  79. /* Mask for the DDR SDRAM Mode Control register */
  80. static const u32 SDRAM_CFG_MEM_EN = 0x80000000;
  81. int dram_init(void)
  82. {
  83. struct udevice *ram_ctrl;
  84. int ret;
  85. /* Current assumption: There is only one RAM controller */
  86. ret = uclass_first_device_err(UCLASS_RAM, &ram_ctrl);
  87. if (ret) {
  88. debug("%s: uclass_first_device_err failed: %d\n",
  89. __func__, ret);
  90. return ret;
  91. }
  92. /* FIXME(mario.six@gdsys.cc): Set gd->ram_size? */
  93. return 0;
  94. }
  95. phys_size_t get_effective_memsize(void)
  96. {
  97. if (!IS_ENABLED(CONFIG_VERY_BIG_RAM))
  98. return gd->ram_size;
  99. /* Limit stack to what we can reasonable map */
  100. return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
  101. CONFIG_MAX_MEM_MAPPED : gd->ram_size);
  102. }
  103. /**
  104. * struct mpc83xx_sdram_priv - Private data for MPC83xx RAM controllers
  105. * @total_size: The total size of all RAM modules associated with this RAM
  106. * controller in bytes
  107. */
  108. struct mpc83xx_sdram_priv {
  109. ulong total_size;
  110. };
  111. /**
  112. * mpc83xx_sdram_static_init() - Statically initialize a RAM module.
  113. * @node: Device tree node associated with ths module in question
  114. * @cs: The chip select to use for this RAM module
  115. * @mapaddr: The address where the RAM module should be mapped
  116. * @size: The size of the RAM module to be mapped in bytes
  117. *
  118. * Return: 0 if OK, -ve on error
  119. */
  120. static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
  121. {
  122. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  123. u32 msize = size;
  124. u32 msize_log2 = __ilog2(msize);
  125. u32 auto_precharge, odt_rd_cfg, odt_wr_cfg, bank_bits, row_bits,
  126. col_bits;
  127. u32 bank_bits_mask, row_bits_mask, col_bits_mask;
  128. /* Configure the DDR local access window */
  129. out_be32(&im->sysconf.ddrlaw[cs].bar, mapaddr & 0xfffff000);
  130. out_be32(&im->sysconf.ddrlaw[cs].ar, LBLAWAR_EN | (msize_log2 - 1));
  131. out_be32(&im->ddr.csbnds[cs].csbnds, (msize - 1) >> 24);
  132. auto_precharge = ofnode_read_u32_default(node, "auto_precharge", 0);
  133. switch (auto_precharge) {
  134. case AUTO_PRECHARGE_ENABLE:
  135. case AUTO_PRECHARGE_DISABLE:
  136. break;
  137. default:
  138. debug("%s: auto_precharge value %d invalid.\n",
  139. ofnode_get_name(node), auto_precharge);
  140. return -EINVAL;
  141. }
  142. odt_rd_cfg = ofnode_read_u32_default(node, "odt_rd_cfg", 0);
  143. switch (odt_rd_cfg) {
  144. case ODT_RD_ONLY_OTHER_DIMM:
  145. if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
  146. !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
  147. debug("%s: odt_rd_cfg value %d invalid.\n",
  148. ofnode_get_name(node), odt_rd_cfg);
  149. return -EINVAL;
  150. }
  151. /* fall through */
  152. case ODT_RD_NEVER:
  153. case ODT_RD_ONLY_CURRENT:
  154. case ODT_RD_ONLY_OTHER_CS:
  155. if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
  156. !IS_ENABLED(CONFIG_ARCH_MPC831X) &&
  157. !IS_ENABLED(CONFIG_ARCH_MPC8360) &&
  158. !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
  159. debug("%s: odt_rd_cfg value %d invalid.\n",
  160. ofnode_get_name(node), odt_rd_cfg);
  161. return -EINVAL;
  162. }
  163. /* fall through */
  164. /* Only MPC832x knows this value */
  165. case ODT_RD_ALL:
  166. break;
  167. default:
  168. debug("%s: odt_rd_cfg value %d invalid.\n",
  169. ofnode_get_name(node), odt_rd_cfg);
  170. return -EINVAL;
  171. }
  172. odt_wr_cfg = ofnode_read_u32_default(node, "odt_wr_cfg", 0);
  173. switch (odt_wr_cfg) {
  174. case ODT_WR_ONLY_OTHER_DIMM:
  175. if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
  176. !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
  177. debug("%s: odt_wr_cfg value %d invalid.\n",
  178. ofnode_get_name(node), odt_wr_cfg);
  179. return -EINVAL;
  180. }
  181. /* fall through */
  182. case ODT_WR_NEVER:
  183. case ODT_WR_ONLY_CURRENT:
  184. case ODT_WR_ONLY_OTHER_CS:
  185. if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
  186. !IS_ENABLED(CONFIG_ARCH_MPC831X) &&
  187. !IS_ENABLED(CONFIG_ARCH_MPC8360) &&
  188. !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
  189. debug("%s: odt_wr_cfg value %d invalid.\n",
  190. ofnode_get_name(node), odt_wr_cfg);
  191. return -EINVAL;
  192. }
  193. /* fall through */
  194. /* MPC832x only knows this value */
  195. case ODT_WR_ALL:
  196. break;
  197. default:
  198. debug("%s: odt_wr_cfg value %d invalid.\n",
  199. ofnode_get_name(node), odt_wr_cfg);
  200. return -EINVAL;
  201. }
  202. bank_bits = ofnode_read_u32_default(node, "bank_bits", 0);
  203. switch (bank_bits) {
  204. case 2:
  205. bank_bits_mask = BANK_BITS_2;
  206. break;
  207. case 3:
  208. bank_bits_mask = BANK_BITS_3;
  209. break;
  210. default:
  211. debug("%s: bank_bits value %d invalid.\n",
  212. ofnode_get_name(node), bank_bits);
  213. return -EINVAL;
  214. }
  215. row_bits = ofnode_read_u32_default(node, "row_bits", 0);
  216. switch (row_bits) {
  217. case 12:
  218. row_bits_mask = ROW_BITS_12;
  219. break;
  220. case 13:
  221. row_bits_mask = ROW_BITS_13;
  222. break;
  223. case 14:
  224. row_bits_mask = ROW_BITS_14;
  225. break;
  226. default:
  227. debug("%s: row_bits value %d invalid.\n",
  228. ofnode_get_name(node), row_bits);
  229. return -EINVAL;
  230. }
  231. col_bits = ofnode_read_u32_default(node, "col_bits", 0);
  232. switch (col_bits) {
  233. case 8:
  234. col_bits_mask = COL_BITS_8;
  235. break;
  236. case 9:
  237. col_bits_mask = COL_BITS_9;
  238. break;
  239. case 10:
  240. col_bits_mask = COL_BITS_10;
  241. break;
  242. case 11:
  243. col_bits_mask = COL_BITS_11;
  244. break;
  245. default:
  246. debug("%s: col_bits value %d invalid.\n",
  247. ofnode_get_name(node), col_bits);
  248. return -EINVAL;
  249. }
  250. /* Write CS config value */
  251. out_be32(&im->ddr.cs_config[cs], CSCONFIG_ENABLE | auto_precharge |
  252. odt_rd_cfg | odt_wr_cfg |
  253. bank_bits_mask | row_bits_mask |
  254. col_bits_mask);
  255. return 0;
  256. }
  257. /**
  258. * mpc83xx_sdram_spd_init() - Initialize a RAM module using a SPD flash.
  259. * @node: Device tree node associated with ths module in question
  260. * @cs: The chip select to use for this RAM module
  261. * @mapaddr: The address where the RAM module should be mapped
  262. * @size: The size of the RAM module to be mapped in bytes
  263. *
  264. * Return: 0 if OK, -ve on error
  265. */
  266. static int mpc83xx_sdram_spd_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
  267. {
  268. /* TODO(mario.six@gdsys.cc): Implement */
  269. return 0;
  270. }
  271. static int mpc83xx_sdram_ofdata_to_platdata(struct udevice *dev)
  272. {
  273. return 0;
  274. }
  275. static int mpc83xx_sdram_probe(struct udevice *dev)
  276. {
  277. struct mpc83xx_sdram_priv *priv = dev_get_priv(dev);
  278. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  279. int ret = 0;
  280. ofnode subnode;
  281. /* DDR control driver register values */
  282. u32 dso, pz_override, nz_override, odt_term, ddr_type, mvref_sel, m_odr;
  283. u32 ddrcdr;
  284. /* DDR SDRAM Clock Control register values */
  285. u32 clock_adjust;
  286. /* DDR SDRAM Timing Configuration 3 register values */
  287. u32 ext_refresh_rec, ext_refresh_rec_mask;
  288. /* DDR SDRAM Timing Configuration 0 register values */
  289. u32 read_to_write, write_to_read, read_to_read, write_to_write,
  290. active_powerdown_exit, precharge_powerdown_exit,
  291. odt_powerdown_exit, mode_reg_set_cycle;
  292. u32 timing_cfg_0;
  293. /* DDR SDRAM Timing Configuration 1 register values */
  294. u32 precharge_to_activate, activate_to_precharge,
  295. activate_to_readwrite, mcas_latency, refresh_recovery,
  296. last_data_to_precharge, activate_to_activate,
  297. last_write_data_to_read;
  298. u32 timing_cfg_1;
  299. /* DDR SDRAM Timing Configuration 2 register values */
  300. u32 additive_latency, mcas_to_preamble_override, write_latency,
  301. read_to_precharge, write_cmd_to_write_data,
  302. minimum_cke_pulse_width, four_activates_window;
  303. u32 timing_cfg_2;
  304. /* DDR SDRAM Control Configuration register values */
  305. u32 self_refresh, ecc, registered_dram, sdram_type,
  306. dynamic_power_management, databus_width, nc_auto_precharge,
  307. timing_2t, bank_interleaving_ctrl, precharge_bit_8, half_strength,
  308. bypass_initialization;
  309. u32 sdram_cfg;
  310. /* DDR SDRAM Control Configuration 2 register values */
  311. u32 force_self_refresh, dll_reset, dqs_config, odt_config,
  312. posted_refreshes;
  313. u32 sdram_cfg2;
  314. /* DDR SDRAM Mode Configuration register values */
  315. u32 sdmode, esdmode;
  316. u32 sdram_mode;
  317. /* DDR SDRAM Mode Configuration 2 register values */
  318. u32 esdmode2, esdmode3;
  319. u32 sdram_mode2;
  320. /* DDR SDRAM Interval Configuration register values */
  321. u32 refresh_interval, precharge_interval;
  322. u32 sdram_interval;
  323. priv->total_size = 0;
  324. /* Disable both banks initially (might be re-enabled in loop below) */
  325. out_be32(&im->ddr.cs_config[0], 0);
  326. out_be32(&im->ddr.cs_config[1], 0);
  327. dso = dev_read_u32_default(dev, "driver_software_override", 0);
  328. if (dso > 1) {
  329. debug("%s: driver_software_override value %d invalid.\n",
  330. dev->name, dso);
  331. return -EINVAL;
  332. }
  333. pz_override = dev_read_u32_default(dev, "p_impedance_override", 0);
  334. switch (pz_override) {
  335. case DSO_P_IMPEDANCE_HIGHEST_Z:
  336. case DSO_P_IMPEDANCE_MUCH_HIGHER_Z:
  337. case DSO_P_IMPEDANCE_HIGHER_Z:
  338. case DSO_P_IMPEDANCE_NOMINAL:
  339. case DSO_P_IMPEDANCE_LOWER_Z:
  340. break;
  341. default:
  342. debug("%s: p_impedance_override value %d invalid.\n",
  343. dev->name, pz_override);
  344. return -EINVAL;
  345. }
  346. nz_override = dev_read_u32_default(dev, "n_impedance_override", 0);
  347. switch (nz_override) {
  348. case DSO_N_IMPEDANCE_HIGHEST_Z:
  349. case DSO_N_IMPEDANCE_MUCH_HIGHER_Z:
  350. case DSO_N_IMPEDANCE_HIGHER_Z:
  351. case DSO_N_IMPEDANCE_NOMINAL:
  352. case DSO_N_IMPEDANCE_LOWER_Z:
  353. break;
  354. default:
  355. debug("%s: n_impedance_override value %d invalid.\n",
  356. dev->name, nz_override);
  357. return -EINVAL;
  358. }
  359. odt_term = dev_read_u32_default(dev, "odt_termination_value", 0);
  360. if (odt_term > 1) {
  361. debug("%s: odt_termination_value value %d invalid.\n",
  362. dev->name, odt_term);
  363. return -EINVAL;
  364. }
  365. ddr_type = dev_read_u32_default(dev, "ddr_type", 0);
  366. if (ddr_type > 1) {
  367. debug("%s: ddr_type value %d invalid.\n",
  368. dev->name, ddr_type);
  369. return -EINVAL;
  370. }
  371. mvref_sel = dev_read_u32_default(dev, "mvref_sel", 0);
  372. if (mvref_sel > 1) {
  373. debug("%s: mvref_sel value %d invalid.\n",
  374. dev->name, mvref_sel);
  375. return -EINVAL;
  376. }
  377. m_odr = dev_read_u32_default(dev, "m_odr", 0);
  378. if (mvref_sel > 1) {
  379. debug("%s: m_odr value %d invalid.\n",
  380. dev->name, m_odr);
  381. return -EINVAL;
  382. }
  383. ddrcdr = dso << (31 - 1) |
  384. pz_override << (31 - 5) |
  385. nz_override << (31 - 9) |
  386. odt_term << (31 - 12) |
  387. ddr_type << (31 - 13) |
  388. mvref_sel << (31 - 29) |
  389. m_odr << (31 - 30) | 1;
  390. /* Configure the DDR control driver register */
  391. out_be32(&im->sysconf.ddrcdr, ddrcdr);
  392. dev_for_each_subnode(subnode, dev) {
  393. u32 val[3];
  394. u32 cs, addr, size;
  395. /* CS, map address, size -> three values */
  396. ofnode_read_u32_array(subnode, "reg", val, 3);
  397. cs = val[0];
  398. addr = val[1];
  399. size = val[2];
  400. if (cs > 1) {
  401. debug("%s: chip select value %d invalid.\n",
  402. dev->name, cs);
  403. return -EINVAL;
  404. }
  405. /* TODO(mario.six@gdsys.cc): Sanity check for size. */
  406. if (ofnode_read_bool(subnode, "read-spd"))
  407. ret = mpc83xx_sdram_spd_init(subnode, cs, addr, size);
  408. else
  409. ret = mpc83xx_sdram_static_init(subnode, cs, addr,
  410. size);
  411. if (ret) {
  412. debug("%s: RAM init failed.\n", dev->name);
  413. return ret;
  414. }
  415. };
  416. /*
  417. * TODO(mario.six@gdsys.cc): This should only occur for static
  418. * configuration
  419. */
  420. clock_adjust = dev_read_u32_default(dev, "clock_adjust", 0);
  421. switch (clock_adjust) {
  422. case CLOCK_ADJUST_025:
  423. case CLOCK_ADJUST_05:
  424. case CLOCK_ADJUST_075:
  425. case CLOCK_ADJUST_1:
  426. break;
  427. default:
  428. debug("%s: clock_adjust value %d invalid.\n",
  429. dev->name, clock_adjust);
  430. return -EINVAL;
  431. }
  432. /* Configure the DDR SDRAM Clock Control register */
  433. out_be32(&im->ddr.sdram_clk_cntl, clock_adjust);
  434. ext_refresh_rec = dev_read_u32_default(dev, "ext_refresh_rec", 0);
  435. switch (ext_refresh_rec) {
  436. case 0:
  437. ext_refresh_rec_mask = 0 << TIMING_CFG3_EXT_REFREC_SHIFT;
  438. break;
  439. case 16:
  440. ext_refresh_rec_mask = 1 << TIMING_CFG3_EXT_REFREC_SHIFT;
  441. break;
  442. case 32:
  443. ext_refresh_rec_mask = 2 << TIMING_CFG3_EXT_REFREC_SHIFT;
  444. break;
  445. case 48:
  446. ext_refresh_rec_mask = 3 << TIMING_CFG3_EXT_REFREC_SHIFT;
  447. break;
  448. case 64:
  449. ext_refresh_rec_mask = 4 << TIMING_CFG3_EXT_REFREC_SHIFT;
  450. break;
  451. case 80:
  452. ext_refresh_rec_mask = 5 << TIMING_CFG3_EXT_REFREC_SHIFT;
  453. break;
  454. case 96:
  455. ext_refresh_rec_mask = 6 << TIMING_CFG3_EXT_REFREC_SHIFT;
  456. break;
  457. case 112:
  458. ext_refresh_rec_mask = 7 << TIMING_CFG3_EXT_REFREC_SHIFT;
  459. break;
  460. default:
  461. debug("%s: ext_refresh_rec value %d invalid.\n",
  462. dev->name, ext_refresh_rec);
  463. return -EINVAL;
  464. }
  465. /* Configure the DDR SDRAM Timing Configuration 3 register */
  466. out_be32(&im->ddr.timing_cfg_3, ext_refresh_rec_mask);
  467. read_to_write = dev_read_u32_default(dev, "read_to_write", 0);
  468. if (read_to_write > 3) {
  469. debug("%s: read_to_write value %d invalid.\n",
  470. dev->name, read_to_write);
  471. return -EINVAL;
  472. }
  473. write_to_read = dev_read_u32_default(dev, "write_to_read", 0);
  474. if (write_to_read > 3) {
  475. debug("%s: write_to_read value %d invalid.\n",
  476. dev->name, write_to_read);
  477. return -EINVAL;
  478. }
  479. read_to_read = dev_read_u32_default(dev, "read_to_read", 0);
  480. if (read_to_read > 3) {
  481. debug("%s: read_to_read value %d invalid.\n",
  482. dev->name, read_to_read);
  483. return -EINVAL;
  484. }
  485. write_to_write = dev_read_u32_default(dev, "write_to_write", 0);
  486. if (write_to_write > 3) {
  487. debug("%s: write_to_write value %d invalid.\n",
  488. dev->name, write_to_write);
  489. return -EINVAL;
  490. }
  491. active_powerdown_exit =
  492. dev_read_u32_default(dev, "active_powerdown_exit", 0);
  493. if (active_powerdown_exit > 7) {
  494. debug("%s: active_powerdown_exit value %d invalid.\n",
  495. dev->name, active_powerdown_exit);
  496. return -EINVAL;
  497. }
  498. precharge_powerdown_exit =
  499. dev_read_u32_default(dev, "precharge_powerdown_exit", 0);
  500. if (precharge_powerdown_exit > 7) {
  501. debug("%s: precharge_powerdown_exit value %d invalid.\n",
  502. dev->name, precharge_powerdown_exit);
  503. return -EINVAL;
  504. }
  505. odt_powerdown_exit = dev_read_u32_default(dev, "odt_powerdown_exit", 0);
  506. if (odt_powerdown_exit > 15) {
  507. debug("%s: odt_powerdown_exit value %d invalid.\n",
  508. dev->name, odt_powerdown_exit);
  509. return -EINVAL;
  510. }
  511. mode_reg_set_cycle = dev_read_u32_default(dev, "mode_reg_set_cycle", 0);
  512. if (mode_reg_set_cycle > 15) {
  513. debug("%s: mode_reg_set_cycle value %d invalid.\n",
  514. dev->name, mode_reg_set_cycle);
  515. return -EINVAL;
  516. }
  517. timing_cfg_0 = read_to_write << TIMING_CFG0_RWT_SHIFT |
  518. write_to_read << TIMING_CFG0_WRT_SHIFT |
  519. read_to_read << TIMING_CFG0_RRT_SHIFT |
  520. write_to_write << TIMING_CFG0_WWT_SHIFT |
  521. active_powerdown_exit << TIMING_CFG0_ACT_PD_EXIT_SHIFT |
  522. precharge_powerdown_exit << TIMING_CFG0_PRE_PD_EXIT_SHIFT |
  523. odt_powerdown_exit << TIMING_CFG0_ODT_PD_EXIT_SHIFT |
  524. mode_reg_set_cycle << TIMING_CFG0_MRS_CYC_SHIFT;
  525. out_be32(&im->ddr.timing_cfg_0, timing_cfg_0);
  526. precharge_to_activate =
  527. dev_read_u32_default(dev, "precharge_to_activate", 0);
  528. if (precharge_to_activate > 7 || precharge_to_activate == 0) {
  529. debug("%s: precharge_to_activate value %d invalid.\n",
  530. dev->name, precharge_to_activate);
  531. return -EINVAL;
  532. }
  533. activate_to_precharge =
  534. dev_read_u32_default(dev, "activate_to_precharge", 0);
  535. if (activate_to_precharge > 19) {
  536. debug("%s: activate_to_precharge value %d invalid.\n",
  537. dev->name, activate_to_precharge);
  538. return -EINVAL;
  539. }
  540. activate_to_readwrite =
  541. dev_read_u32_default(dev, "activate_to_readwrite", 0);
  542. if (activate_to_readwrite > 7 || activate_to_readwrite == 0) {
  543. debug("%s: activate_to_readwrite value %d invalid.\n",
  544. dev->name, activate_to_readwrite);
  545. return -EINVAL;
  546. }
  547. mcas_latency = dev_read_u32_default(dev, "mcas_latency", 0);
  548. switch (mcas_latency) {
  549. case CASLAT_20:
  550. case CASLAT_25:
  551. if (!IS_ENABLED(CONFIG_ARCH_MPC8308)) {
  552. debug("%s: MCAS latency < 3.0 unsupported on MPC8308\n",
  553. dev->name);
  554. return -EINVAL;
  555. }
  556. /* fall through */
  557. case CASLAT_30:
  558. case CASLAT_35:
  559. case CASLAT_40:
  560. case CASLAT_45:
  561. case CASLAT_50:
  562. case CASLAT_55:
  563. case CASLAT_60:
  564. case CASLAT_65:
  565. case CASLAT_70:
  566. case CASLAT_75:
  567. case CASLAT_80:
  568. break;
  569. default:
  570. debug("%s: mcas_latency value %d invalid.\n",
  571. dev->name, mcas_latency);
  572. return -EINVAL;
  573. }
  574. refresh_recovery = dev_read_u32_default(dev, "refresh_recovery", 0);
  575. if (refresh_recovery > 23 || refresh_recovery < 8) {
  576. debug("%s: refresh_recovery value %d invalid.\n",
  577. dev->name, refresh_recovery);
  578. return -EINVAL;
  579. }
  580. last_data_to_precharge =
  581. dev_read_u32_default(dev, "last_data_to_precharge", 0);
  582. if (last_data_to_precharge > 7 || last_data_to_precharge == 0) {
  583. debug("%s: last_data_to_precharge value %d invalid.\n",
  584. dev->name, last_data_to_precharge);
  585. return -EINVAL;
  586. }
  587. activate_to_activate =
  588. dev_read_u32_default(dev, "activate_to_activate", 0);
  589. if (activate_to_activate > 7 || activate_to_activate == 0) {
  590. debug("%s: activate_to_activate value %d invalid.\n",
  591. dev->name, activate_to_activate);
  592. return -EINVAL;
  593. }
  594. last_write_data_to_read =
  595. dev_read_u32_default(dev, "last_write_data_to_read", 0);
  596. if (last_write_data_to_read > 7 || last_write_data_to_read == 0) {
  597. debug("%s: last_write_data_to_read value %d invalid.\n",
  598. dev->name, last_write_data_to_read);
  599. return -EINVAL;
  600. }
  601. timing_cfg_1 = precharge_to_activate << TIMING_CFG1_PRETOACT_SHIFT |
  602. (activate_to_precharge > 15 ?
  603. activate_to_precharge - 16 :
  604. activate_to_precharge) << TIMING_CFG1_ACTTOPRE_SHIFT |
  605. activate_to_readwrite << TIMING_CFG1_ACTTORW_SHIFT |
  606. mcas_latency << TIMING_CFG1_CASLAT_SHIFT |
  607. (refresh_recovery - 8) << TIMING_CFG1_REFREC_SHIFT |
  608. last_data_to_precharge << TIMING_CFG1_WRREC_SHIFT |
  609. activate_to_activate << TIMING_CFG1_ACTTOACT_SHIFT |
  610. last_write_data_to_read << TIMING_CFG1_WRTORD_SHIFT;
  611. /* Configure the DDR SDRAM Timing Configuration 1 register */
  612. out_be32(&im->ddr.timing_cfg_1, timing_cfg_1);
  613. additive_latency = dev_read_u32_default(dev, "additive_latency", 0);
  614. if (additive_latency > 5) {
  615. debug("%s: additive_latency value %d invalid.\n",
  616. dev->name, additive_latency);
  617. return -EINVAL;
  618. }
  619. mcas_to_preamble_override =
  620. dev_read_u32_default(dev, "mcas_to_preamble_override", 0);
  621. switch (mcas_to_preamble_override) {
  622. case READ_LAT_PLUS_1:
  623. case READ_LAT:
  624. case READ_LAT_PLUS_1_4:
  625. case READ_LAT_PLUS_1_2:
  626. case READ_LAT_PLUS_3_4:
  627. case READ_LAT_PLUS_5_4:
  628. case READ_LAT_PLUS_3_2:
  629. case READ_LAT_PLUS_7_4:
  630. case READ_LAT_PLUS_2:
  631. case READ_LAT_PLUS_9_4:
  632. case READ_LAT_PLUS_5_2:
  633. case READ_LAT_PLUS_11_4:
  634. case READ_LAT_PLUS_3:
  635. case READ_LAT_PLUS_13_4:
  636. case READ_LAT_PLUS_7_2:
  637. case READ_LAT_PLUS_15_4:
  638. case READ_LAT_PLUS_4:
  639. case READ_LAT_PLUS_17_4:
  640. case READ_LAT_PLUS_9_2:
  641. case READ_LAT_PLUS_19_4:
  642. break;
  643. default:
  644. debug("%s: mcas_to_preamble_override value %d invalid.\n",
  645. dev->name, mcas_to_preamble_override);
  646. return -EINVAL;
  647. }
  648. write_latency = dev_read_u32_default(dev, "write_latency", 0);
  649. if (write_latency > 7 || write_latency == 0) {
  650. debug("%s: write_latency value %d invalid.\n",
  651. dev->name, write_latency);
  652. return -EINVAL;
  653. }
  654. read_to_precharge = dev_read_u32_default(dev, "read_to_precharge", 0);
  655. if (read_to_precharge > 4 || read_to_precharge == 0) {
  656. debug("%s: read_to_precharge value %d invalid.\n",
  657. dev->name, read_to_precharge);
  658. return -EINVAL;
  659. }
  660. write_cmd_to_write_data =
  661. dev_read_u32_default(dev, "write_cmd_to_write_data", 0);
  662. switch (write_cmd_to_write_data) {
  663. case CLOCK_DELAY_0:
  664. case CLOCK_DELAY_1_4:
  665. case CLOCK_DELAY_1_2:
  666. case CLOCK_DELAY_3_4:
  667. case CLOCK_DELAY_1:
  668. case CLOCK_DELAY_5_4:
  669. case CLOCK_DELAY_3_2:
  670. break;
  671. default:
  672. debug("%s: write_cmd_to_write_data value %d invalid.\n",
  673. dev->name, write_cmd_to_write_data);
  674. return -EINVAL;
  675. }
  676. minimum_cke_pulse_width =
  677. dev_read_u32_default(dev, "minimum_cke_pulse_width", 0);
  678. if (minimum_cke_pulse_width > 4 || minimum_cke_pulse_width == 0) {
  679. debug("%s: minimum_cke_pulse_width value %d invalid.\n",
  680. dev->name, minimum_cke_pulse_width);
  681. return -EINVAL;
  682. }
  683. four_activates_window =
  684. dev_read_u32_default(dev, "four_activates_window", 0);
  685. if (four_activates_window > 20 || four_activates_window == 0) {
  686. debug("%s: four_activates_window value %d invalid.\n",
  687. dev->name, four_activates_window);
  688. return -EINVAL;
  689. }
  690. timing_cfg_2 = additive_latency << TIMING_CFG2_ADD_LAT_SHIFT |
  691. mcas_to_preamble_override << TIMING_CFG2_CPO_SHIFT |
  692. write_latency << TIMING_CFG2_WR_LAT_DELAY_SHIFT |
  693. read_to_precharge << TIMING_CFG2_RD_TO_PRE_SHIFT |
  694. write_cmd_to_write_data << TIMING_CFG2_WR_DATA_DELAY_SHIFT |
  695. minimum_cke_pulse_width << TIMING_CFG2_CKE_PLS_SHIFT |
  696. four_activates_window << TIMING_CFG2_FOUR_ACT_SHIFT;
  697. out_be32(&im->ddr.timing_cfg_2, timing_cfg_2);
  698. self_refresh = dev_read_u32_default(dev, "self_refresh", 0);
  699. switch (self_refresh) {
  700. case SREN_DISABLE:
  701. case SREN_ENABLE:
  702. break;
  703. default:
  704. debug("%s: self_refresh value %d invalid.\n",
  705. dev->name, self_refresh);
  706. return -EINVAL;
  707. }
  708. ecc = dev_read_u32_default(dev, "ecc", 0);
  709. switch (ecc) {
  710. case ECC_DISABLE:
  711. case ECC_ENABLE:
  712. break;
  713. default:
  714. debug("%s: ecc value %d invalid.\n", dev->name, ecc);
  715. return -EINVAL;
  716. }
  717. registered_dram = dev_read_u32_default(dev, "registered_dram", 0);
  718. switch (registered_dram) {
  719. case RD_DISABLE:
  720. case RD_ENABLE:
  721. break;
  722. default:
  723. debug("%s: registered_dram value %d invalid.\n",
  724. dev->name, registered_dram);
  725. return -EINVAL;
  726. }
  727. sdram_type = dev_read_u32_default(dev, "sdram_type", 0);
  728. switch (sdram_type) {
  729. case TYPE_DDR1:
  730. case TYPE_DDR2:
  731. break;
  732. default:
  733. debug("%s: sdram_type value %d invalid.\n",
  734. dev->name, sdram_type);
  735. return -EINVAL;
  736. }
  737. dynamic_power_management =
  738. dev_read_u32_default(dev, "dynamic_power_management", 0);
  739. switch (dynamic_power_management) {
  740. case DYN_PWR_DISABLE:
  741. case DYN_PWR_ENABLE:
  742. break;
  743. default:
  744. debug("%s: dynamic_power_management value %d invalid.\n",
  745. dev->name, dynamic_power_management);
  746. return -EINVAL;
  747. }
  748. databus_width = dev_read_u32_default(dev, "databus_width", 0);
  749. switch (databus_width) {
  750. case DATA_BUS_WIDTH_16:
  751. case DATA_BUS_WIDTH_32:
  752. break;
  753. default:
  754. debug("%s: databus_width value %d invalid.\n",
  755. dev->name, databus_width);
  756. return -EINVAL;
  757. }
  758. nc_auto_precharge = dev_read_u32_default(dev, "nc_auto_precharge", 0);
  759. switch (nc_auto_precharge) {
  760. case NCAP_DISABLE:
  761. case NCAP_ENABLE:
  762. break;
  763. default:
  764. debug("%s: nc_auto_precharge value %d invalid.\n",
  765. dev->name, nc_auto_precharge);
  766. return -EINVAL;
  767. }
  768. timing_2t = dev_read_u32_default(dev, "timing_2t", 0);
  769. switch (timing_2t) {
  770. case TIMING_1T:
  771. case TIMING_2T:
  772. break;
  773. default:
  774. debug("%s: timing_2t value %d invalid.\n",
  775. dev->name, timing_2t);
  776. return -EINVAL;
  777. }
  778. bank_interleaving_ctrl =
  779. dev_read_u32_default(dev, "bank_interleaving_ctrl", 0);
  780. switch (bank_interleaving_ctrl) {
  781. case INTERLEAVE_NONE:
  782. case INTERLEAVE_1_AND_2:
  783. break;
  784. default:
  785. debug("%s: bank_interleaving_ctrl value %d invalid.\n",
  786. dev->name, bank_interleaving_ctrl);
  787. return -EINVAL;
  788. }
  789. precharge_bit_8 = dev_read_u32_default(dev, "precharge_bit_8", 0);
  790. switch (precharge_bit_8) {
  791. case PRECHARGE_MA_10:
  792. case PRECHARGE_MA_8:
  793. break;
  794. default:
  795. debug("%s: precharge_bit_8 value %d invalid.\n",
  796. dev->name, precharge_bit_8);
  797. return -EINVAL;
  798. }
  799. half_strength = dev_read_u32_default(dev, "half_strength", 0);
  800. switch (half_strength) {
  801. case STRENGTH_FULL:
  802. case STRENGTH_HALF:
  803. break;
  804. default:
  805. debug("%s: half_strength value %d invalid.\n",
  806. dev->name, half_strength);
  807. return -EINVAL;
  808. }
  809. bypass_initialization =
  810. dev_read_u32_default(dev, "bypass_initialization", 0);
  811. switch (bypass_initialization) {
  812. case INITIALIZATION_DONT_BYPASS:
  813. case INITIALIZATION_BYPASS:
  814. break;
  815. default:
  816. debug("%s: bypass_initialization value %d invalid.\n",
  817. dev->name, bypass_initialization);
  818. return -EINVAL;
  819. }
  820. sdram_cfg = self_refresh << SDRAM_CFG_SREN_SHIFT |
  821. ecc << SDRAM_CFG_ECC_EN_SHIFT |
  822. registered_dram << SDRAM_CFG_RD_EN_SHIFT |
  823. sdram_type << SDRAM_CFG_SDRAM_TYPE_SHIFT |
  824. dynamic_power_management << SDRAM_CFG_DYN_PWR_SHIFT |
  825. databus_width << SDRAM_CFG_DBW_SHIFT |
  826. nc_auto_precharge << SDRAM_CFG_NCAP_SHIFT |
  827. timing_2t << SDRAM_CFG_2T_EN_SHIFT |
  828. bank_interleaving_ctrl << SDRAM_CFG_BA_INTLV_CTL_SHIFT |
  829. precharge_bit_8 << SDRAM_CFG_PCHB8_SHIFT |
  830. half_strength << SDRAM_CFG_HSE_SHIFT |
  831. bypass_initialization << SDRAM_CFG_BI_SHIFT;
  832. out_be32(&im->ddr.sdram_cfg, sdram_cfg);
  833. force_self_refresh = dev_read_u32_default(dev, "force_self_refresh", 0);
  834. switch (force_self_refresh) {
  835. case MODE_NORMAL:
  836. case MODE_REFRESH:
  837. break;
  838. default:
  839. debug("%s: force_self_refresh value %d invalid.\n",
  840. dev->name, force_self_refresh);
  841. return -EINVAL;
  842. }
  843. dll_reset = dev_read_u32_default(dev, "dll_reset", 0);
  844. switch (dll_reset) {
  845. case DLL_RESET_ENABLE:
  846. case DLL_RESET_DISABLE:
  847. break;
  848. default:
  849. debug("%s: dll_reset value %d invalid.\n",
  850. dev->name, dll_reset);
  851. return -EINVAL;
  852. }
  853. dqs_config = dev_read_u32_default(dev, "dqs_config", 0);
  854. switch (dqs_config) {
  855. case DQS_TRUE:
  856. break;
  857. default:
  858. debug("%s: dqs_config value %d invalid.\n",
  859. dev->name, dqs_config);
  860. return -EINVAL;
  861. }
  862. odt_config = dev_read_u32_default(dev, "odt_config", 0);
  863. switch (odt_config) {
  864. case ODT_ASSERT_NEVER:
  865. case ODT_ASSERT_WRITES:
  866. case ODT_ASSERT_READS:
  867. case ODT_ASSERT_ALWAYS:
  868. break;
  869. default:
  870. debug("%s: odt_config value %d invalid.\n",
  871. dev->name, odt_config);
  872. return -EINVAL;
  873. }
  874. posted_refreshes = dev_read_u32_default(dev, "posted_refreshes", 0);
  875. if (posted_refreshes > 8 || posted_refreshes == 0) {
  876. debug("%s: posted_refreshes value %d invalid.\n",
  877. dev->name, posted_refreshes);
  878. return -EINVAL;
  879. }
  880. sdram_cfg2 = force_self_refresh << SDRAM_CFG2_FRC_SR_SHIFT |
  881. dll_reset << SDRAM_CFG2_DLL_RST_DIS |
  882. dqs_config << SDRAM_CFG2_DQS_CFG |
  883. odt_config << SDRAM_CFG2_ODT_CFG |
  884. posted_refreshes << SDRAM_CFG2_NUM_PR;
  885. out_be32(&im->ddr.sdram_cfg2, sdram_cfg2);
  886. sdmode = dev_read_u32_default(dev, "sdmode", 0);
  887. if (sdmode > 0xFFFF) {
  888. debug("%s: sdmode value %d invalid.\n",
  889. dev->name, sdmode);
  890. return -EINVAL;
  891. }
  892. esdmode = dev_read_u32_default(dev, "esdmode", 0);
  893. if (esdmode > 0xFFFF) {
  894. debug("%s: esdmode value %d invalid.\n", dev->name, esdmode);
  895. return -EINVAL;
  896. }
  897. sdram_mode = sdmode << SDRAM_MODE_SD_SHIFT |
  898. esdmode << SDRAM_MODE_ESD_SHIFT;
  899. out_be32(&im->ddr.sdram_mode, sdram_mode);
  900. esdmode2 = dev_read_u32_default(dev, "esdmode2", 0);
  901. if (esdmode2 > 0xFFFF) {
  902. debug("%s: esdmode2 value %d invalid.\n", dev->name, esdmode2);
  903. return -EINVAL;
  904. }
  905. esdmode3 = dev_read_u32_default(dev, "esdmode3", 0);
  906. if (esdmode3 > 0xFFFF) {
  907. debug("%s: esdmode3 value %d invalid.\n", dev->name, esdmode3);
  908. return -EINVAL;
  909. }
  910. sdram_mode2 = esdmode2 << SDRAM_MODE2_ESD2_SHIFT |
  911. esdmode3 << SDRAM_MODE2_ESD3_SHIFT;
  912. out_be32(&im->ddr.sdram_mode2, sdram_mode2);
  913. refresh_interval = dev_read_u32_default(dev, "refresh_interval", 0);
  914. if (refresh_interval > 0xFFFF) {
  915. debug("%s: refresh_interval value %d invalid.\n",
  916. dev->name, refresh_interval);
  917. return -EINVAL;
  918. }
  919. precharge_interval = dev_read_u32_default(dev, "precharge_interval", 0);
  920. if (precharge_interval > 0x3FFF) {
  921. debug("%s: precharge_interval value %d invalid.\n",
  922. dev->name, precharge_interval);
  923. return -EINVAL;
  924. }
  925. sdram_interval = refresh_interval << SDRAM_INTERVAL_REFINT_SHIFT |
  926. precharge_interval << SDRAM_INTERVAL_BSTOPRE_SHIFT;
  927. out_be32(&im->ddr.sdram_interval, sdram_interval);
  928. sync();
  929. /* Enable DDR controller */
  930. setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
  931. sync();
  932. dev_for_each_subnode(subnode, dev) {
  933. u32 val[3];
  934. u32 addr, size;
  935. /* CS, map address, size -> three values */
  936. ofnode_read_u32_array(subnode, "reg", val, 3);
  937. addr = val[1];
  938. size = val[2];
  939. priv->total_size += get_ram_size((long int *)addr, size);
  940. };
  941. gd->ram_size = priv->total_size;
  942. return 0;
  943. }
  944. static int mpc83xx_sdram_get_info(struct udevice *dev, struct ram_info *info)
  945. {
  946. /* TODO(mario.six@gdsys.cc): Implement */
  947. return 0;
  948. }
  949. static struct ram_ops mpc83xx_sdram_ops = {
  950. .get_info = mpc83xx_sdram_get_info,
  951. };
  952. static const struct udevice_id mpc83xx_sdram_ids[] = {
  953. { .compatible = "fsl,mpc83xx-mem-controller" },
  954. { /* sentinel */ }
  955. };
  956. U_BOOT_DRIVER(mpc83xx_sdram) = {
  957. .name = "mpc83xx_sdram",
  958. .id = UCLASS_RAM,
  959. .of_match = mpc83xx_sdram_ids,
  960. .ops = &mpc83xx_sdram_ops,
  961. .ofdata_to_platdata = mpc83xx_sdram_ofdata_to_platdata,
  962. .probe = mpc83xx_sdram_probe,
  963. .priv_auto_alloc_size = sizeof(struct mpc83xx_sdram_priv),
  964. };