uec_phy.h 7.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2005, 2011 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Shlomi Gridish <gridish@freescale.com>
  6. *
  7. * Description: UCC ethernet driver -- PHY handling
  8. * Driver for UEC on QE
  9. * Based on 8260_io/fcc_enet.c
  10. */
  11. #ifndef __UEC_PHY_H__
  12. #define __UEC_PHY_H__
  13. #define MII_end ((u32)-2)
  14. #define MII_read ((u32)-1)
  15. #define MIIMIND_BUSY 0x00000001
  16. #define MIIMIND_NOTVALID 0x00000004
  17. #define UGETH_AN_TIMEOUT 2000
  18. /* Cicada Extended Control Register 1 */
  19. #define MII_CIS8201_EXT_CON1 0x17
  20. #define MII_CIS8201_EXTCON1_INIT 0x0000
  21. /* Cicada Interrupt Mask Register */
  22. #define MII_CIS8201_IMASK 0x19
  23. #define MII_CIS8201_IMASK_IEN 0x8000
  24. #define MII_CIS8201_IMASK_SPEED 0x4000
  25. #define MII_CIS8201_IMASK_LINK 0x2000
  26. #define MII_CIS8201_IMASK_DUPLEX 0x1000
  27. #define MII_CIS8201_IMASK_MASK 0xf000
  28. /* Cicada Interrupt Status Register */
  29. #define MII_CIS8201_ISTAT 0x1a
  30. #define MII_CIS8201_ISTAT_STATUS 0x8000
  31. #define MII_CIS8201_ISTAT_SPEED 0x4000
  32. #define MII_CIS8201_ISTAT_LINK 0x2000
  33. #define MII_CIS8201_ISTAT_DUPLEX 0x1000
  34. /* Cicada Auxiliary Control/Status Register */
  35. #define MII_CIS8201_AUX_CONSTAT 0x1c
  36. #define MII_CIS8201_AUXCONSTAT_INIT 0x0004
  37. #define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020
  38. #define MII_CIS8201_AUXCONSTAT_SPEED 0x0018
  39. #define MII_CIS8201_AUXCONSTAT_GBIT 0x0010
  40. #define MII_CIS8201_AUXCONSTAT_100 0x0008
  41. /* 88E1011 PHY Status Register */
  42. #define MII_M1011_PHY_SPEC_STATUS 0x11
  43. #define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
  44. #define MII_M1011_PHY_SPEC_STATUS_100 0x4000
  45. #define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
  46. #define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
  47. #define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
  48. #define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400
  49. #define MII_M1011_IEVENT 0x13
  50. #define MII_M1011_IEVENT_CLEAR 0x0000
  51. #define MII_M1011_IMASK 0x12
  52. #define MII_M1011_IMASK_INIT 0x6400
  53. #define MII_M1011_IMASK_CLEAR 0x0000
  54. /* 88E1111 PHY Register */
  55. #define MII_M1111_PHY_EXT_CR 0x14
  56. #define MII_M1111_RX_DELAY 0x80
  57. #define MII_M1111_TX_DELAY 0x2
  58. #define MII_M1111_PHY_EXT_SR 0x1b
  59. #define MII_M1111_HWCFG_MODE_MASK 0xf
  60. #define MII_M1111_HWCFG_MODE_RGMII 0xb
  61. #define MII_DM9161_SCR 0x10
  62. #define MII_DM9161_SCR_INIT 0x0610
  63. #define MII_DM9161_SCR_RMII_INIT 0x0710
  64. /* DM9161 Specified Configuration and Status Register */
  65. #define MII_DM9161_SCSR 0x11
  66. #define MII_DM9161_SCSR_100F 0x8000
  67. #define MII_DM9161_SCSR_100H 0x4000
  68. #define MII_DM9161_SCSR_10F 0x2000
  69. #define MII_DM9161_SCSR_10H 0x1000
  70. /* DM9161 Interrupt Register */
  71. #define MII_DM9161_INTR 0x15
  72. #define MII_DM9161_INTR_PEND 0x8000
  73. #define MII_DM9161_INTR_DPLX_MASK 0x0800
  74. #define MII_DM9161_INTR_SPD_MASK 0x0400
  75. #define MII_DM9161_INTR_LINK_MASK 0x0200
  76. #define MII_DM9161_INTR_MASK 0x0100
  77. #define MII_DM9161_INTR_DPLX_CHANGE 0x0010
  78. #define MII_DM9161_INTR_SPD_CHANGE 0x0008
  79. #define MII_DM9161_INTR_LINK_CHANGE 0x0004
  80. #define MII_DM9161_INTR_INIT 0x0000
  81. #define MII_DM9161_INTR_STOP \
  82. (MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
  83. | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
  84. /* DM9161 10BT Configuration/Status */
  85. #define MII_DM9161_10BTCSR 0x12
  86. #define MII_DM9161_10BTCSR_INIT 0x7800
  87. #define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
  88. SUPPORTED_10baseT_Full | \
  89. SUPPORTED_100baseT_Half | \
  90. SUPPORTED_100baseT_Full | \
  91. SUPPORTED_Autoneg | \
  92. SUPPORTED_TP | \
  93. SUPPORTED_MII)
  94. #define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \
  95. SUPPORTED_1000baseT_Half | \
  96. SUPPORTED_1000baseT_Full)
  97. #define MII_READ_COMMAND 0x00000001
  98. #define MII_INTERRUPT_DISABLED 0x0
  99. #define MII_INTERRUPT_ENABLED 0x1
  100. #define SPEED_10 10
  101. #define SPEED_100 100
  102. #define SPEED_1000 1000
  103. /* Duplex, half or full. */
  104. #define DUPLEX_HALF 0x00
  105. #define DUPLEX_FULL 0x01
  106. /* Indicates what features are supported by the interface. */
  107. #define SUPPORTED_10baseT_Half (1 << 0)
  108. #define SUPPORTED_10baseT_Full (1 << 1)
  109. #define SUPPORTED_100baseT_Half (1 << 2)
  110. #define SUPPORTED_100baseT_Full (1 << 3)
  111. #define SUPPORTED_1000baseT_Half (1 << 4)
  112. #define SUPPORTED_1000baseT_Full (1 << 5)
  113. #define SUPPORTED_Autoneg (1 << 6)
  114. #define SUPPORTED_TP (1 << 7)
  115. #define SUPPORTED_AUI (1 << 8)
  116. #define SUPPORTED_MII (1 << 9)
  117. #define SUPPORTED_FIBRE (1 << 10)
  118. #define SUPPORTED_BNC (1 << 11)
  119. #define SUPPORTED_10000baseT_Full (1 << 12)
  120. #define ADVERTISED_10baseT_Half (1 << 0)
  121. #define ADVERTISED_10baseT_Full (1 << 1)
  122. #define ADVERTISED_100baseT_Half (1 << 2)
  123. #define ADVERTISED_100baseT_Full (1 << 3)
  124. #define ADVERTISED_1000baseT_Half (1 << 4)
  125. #define ADVERTISED_1000baseT_Full (1 << 5)
  126. #define ADVERTISED_Autoneg (1 << 6)
  127. #define ADVERTISED_TP (1 << 7)
  128. #define ADVERTISED_AUI (1 << 8)
  129. #define ADVERTISED_MII (1 << 9)
  130. #define ADVERTISED_FIBRE (1 << 10)
  131. #define ADVERTISED_BNC (1 << 11)
  132. #define ADVERTISED_10000baseT_Full (1 << 12)
  133. /* Taken from mii_if_info and sungem_phy.h */
  134. struct uec_mii_info {
  135. /* Information about the PHY type */
  136. /* And management functions */
  137. struct phy_info *phyinfo;
  138. struct eth_device *dev;
  139. /* forced speed & duplex (no autoneg)
  140. * partner speed & duplex & pause (autoneg)
  141. */
  142. int speed;
  143. int duplex;
  144. int pause;
  145. /* The most recently read link state */
  146. int link;
  147. /* Enabled Interrupts */
  148. u32 interrupts;
  149. u32 advertising;
  150. int autoneg;
  151. int mii_id;
  152. /* private data pointer */
  153. /* For use by PHYs to maintain extra state */
  154. void *priv;
  155. /* Provided by ethernet driver */
  156. int (*mdio_read) (struct eth_device * dev, int mii_id, int reg);
  157. void (*mdio_write) (struct eth_device * dev, int mii_id, int reg,
  158. int val);
  159. };
  160. /* struct phy_info: a structure which defines attributes for a PHY
  161. *
  162. * id will contain a number which represents the PHY. During
  163. * startup, the driver will poll the PHY to find out what its
  164. * UID--as defined by registers 2 and 3--is. The 32-bit result
  165. * gotten from the PHY will be ANDed with phy_id_mask to
  166. * discard any bits which may change based on revision numbers
  167. * unimportant to functionality
  168. *
  169. * There are 6 commands which take a ugeth_mii_info structure.
  170. * Each PHY must declare config_aneg, and read_status.
  171. */
  172. struct phy_info {
  173. u32 phy_id;
  174. char *name;
  175. unsigned int phy_id_mask;
  176. u32 features;
  177. /* Called to initialize the PHY */
  178. int (*init) (struct uec_mii_info * mii_info);
  179. /* Called to suspend the PHY for power */
  180. int (*suspend) (struct uec_mii_info * mii_info);
  181. /* Reconfigures autonegotiation (or disables it) */
  182. int (*config_aneg) (struct uec_mii_info * mii_info);
  183. /* Determines the negotiated speed and duplex */
  184. int (*read_status) (struct uec_mii_info * mii_info);
  185. /* Clears any pending interrupts */
  186. int (*ack_interrupt) (struct uec_mii_info * mii_info);
  187. /* Enables or disables interrupts */
  188. int (*config_intr) (struct uec_mii_info * mii_info);
  189. /* Clears up any memory if needed */
  190. void (*close) (struct uec_mii_info * mii_info);
  191. };
  192. struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info);
  193. void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
  194. int value);
  195. int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
  196. void mii_clear_phy_interrupt (struct uec_mii_info *mii_info);
  197. void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
  198. u32 interrupts);
  199. #endif /* __UEC_PHY_H__ */