uec.h 24 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
  4. *
  5. * Dave Liu <daveliu@freescale.com>
  6. * based on source code of Shlomi Gridish
  7. */
  8. #ifndef __UEC_H__
  9. #define __UEC_H__
  10. #include "uccf.h"
  11. #include <fsl_qe.h>
  12. #include <phy.h>
  13. #define MAX_TX_THREADS 8
  14. #define MAX_RX_THREADS 8
  15. #define MAX_TX_QUEUES 8
  16. #define MAX_RX_QUEUES 8
  17. #define MAX_PREFETCHED_BDS 4
  18. #define MAX_IPH_OFFSET_ENTRY 8
  19. #define MAX_ENET_INIT_PARAM_ENTRIES_RX 9
  20. #define MAX_ENET_INIT_PARAM_ENTRIES_TX 8
  21. /* UEC UPSMR (Protocol Specific Mode Register)
  22. */
  23. #define UPSMR_ECM 0x04000000 /* Enable CAM Miss */
  24. #define UPSMR_HSE 0x02000000 /* Hardware Statistics Enable */
  25. #define UPSMR_PRO 0x00400000 /* Promiscuous */
  26. #define UPSMR_CAP 0x00200000 /* CAM polarity */
  27. #define UPSMR_RSH 0x00100000 /* Receive Short Frames */
  28. #define UPSMR_RPM 0x00080000 /* Reduced Pin Mode interfaces */
  29. #define UPSMR_R10M 0x00040000 /* RGMII/RMII 10 Mode */
  30. #define UPSMR_RLPB 0x00020000 /* RMII Loopback Mode */
  31. #define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */
  32. #define UPSMR_RMM 0x00001000 /* RMII/RGMII Mode */
  33. #define UPSMR_CAM 0x00000400 /* CAM Address Matching */
  34. #define UPSMR_BRO 0x00000200 /* Broadcast Address */
  35. #define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */
  36. #define UPSMR_SGMM 0x00000020 /* SGMII mode */
  37. #define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1)
  38. /* UEC MACCFG1 (MAC Configuration 1 Register)
  39. */
  40. #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */
  41. #define MACCFG1_FLOW_TX 0x00000010 /* Flow Control Tx */
  42. #define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Enable Rx Sync */
  43. #define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */
  44. #define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Enable Tx Sync */
  45. #define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */
  46. #define MACCFG1_INIT_VALUE (0)
  47. /* UEC MACCFG2 (MAC Configuration 2 Register)
  48. */
  49. #define MACCFG2_PREL 0x00007000
  50. #define MACCFG2_PREL_SHIFT (31 - 19)
  51. #define MACCFG2_PREL_MASK 0x0000f000
  52. #define MACCFG2_SRP 0x00000080
  53. #define MACCFG2_STP 0x00000040
  54. #define MACCFG2_RESERVED_1 0x00000020 /* must be set */
  55. #define MACCFG2_LC 0x00000010 /* Length Check */
  56. #define MACCFG2_MPE 0x00000008
  57. #define MACCFG2_FDX 0x00000001 /* Full Duplex */
  58. #define MACCFG2_FDX_MASK 0x00000001
  59. #define MACCFG2_PAD_CRC 0x00000004
  60. #define MACCFG2_CRC_EN 0x00000002
  61. #define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000
  62. #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002
  63. #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004
  64. #define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100
  65. #define MACCFG2_INTERFACE_MODE_BYTE 0x00000200
  66. #define MACCFG2_INTERFACE_MODE_MASK 0x00000300
  67. #define MACCFG2_INIT_VALUE (MACCFG2_PREL | MACCFG2_RESERVED_1 | \
  68. MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX)
  69. /* UEC Event Register
  70. */
  71. #define UCCE_MPD 0x80000000
  72. #define UCCE_SCAR 0x40000000
  73. #define UCCE_GRA 0x20000000
  74. #define UCCE_CBPR 0x10000000
  75. #define UCCE_BSY 0x08000000
  76. #define UCCE_RXC 0x04000000
  77. #define UCCE_TXC 0x02000000
  78. #define UCCE_TXE 0x01000000
  79. #define UCCE_TXB7 0x00800000
  80. #define UCCE_TXB6 0x00400000
  81. #define UCCE_TXB5 0x00200000
  82. #define UCCE_TXB4 0x00100000
  83. #define UCCE_TXB3 0x00080000
  84. #define UCCE_TXB2 0x00040000
  85. #define UCCE_TXB1 0x00020000
  86. #define UCCE_TXB0 0x00010000
  87. #define UCCE_RXB7 0x00008000
  88. #define UCCE_RXB6 0x00004000
  89. #define UCCE_RXB5 0x00002000
  90. #define UCCE_RXB4 0x00001000
  91. #define UCCE_RXB3 0x00000800
  92. #define UCCE_RXB2 0x00000400
  93. #define UCCE_RXB1 0x00000200
  94. #define UCCE_RXB0 0x00000100
  95. #define UCCE_RXF7 0x00000080
  96. #define UCCE_RXF6 0x00000040
  97. #define UCCE_RXF5 0x00000020
  98. #define UCCE_RXF4 0x00000010
  99. #define UCCE_RXF3 0x00000008
  100. #define UCCE_RXF2 0x00000004
  101. #define UCCE_RXF1 0x00000002
  102. #define UCCE_RXF0 0x00000001
  103. #define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \
  104. UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
  105. #define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \
  106. UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
  107. #define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \
  108. UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
  109. #define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY | \
  110. UCCE_RXC | UCCE_TXC | UCCE_TXE)
  111. /* UEC TEMODR Register
  112. */
  113. #define TEMODER_SCHEDULER_ENABLE 0x2000
  114. #define TEMODER_IP_CHECKSUM_GENERATE 0x0400
  115. #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200
  116. #define TEMODER_RMON_STATISTICS 0x0100
  117. #define TEMODER_NUM_OF_QUEUES_SHIFT (15-15)
  118. #define TEMODER_INIT_VALUE 0xc000
  119. /* UEC REMODR Register
  120. */
  121. #define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000
  122. #define REMODER_RX_EXTENDED_FEATURES 0x80000000
  123. #define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 )
  124. #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10)
  125. #define REMODER_RX_QOS_MODE_SHIFT (31-15)
  126. #define REMODER_RMON_STATISTICS 0x00001000
  127. #define REMODER_RX_EXTENDED_FILTERING 0x00000800
  128. #define REMODER_NUM_OF_QUEUES_SHIFT (31-23)
  129. #define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008
  130. #define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004
  131. #define REMODER_IP_CHECKSUM_CHECK 0x00000002
  132. #define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001
  133. #define REMODER_INIT_VALUE 0
  134. /* BMRx - Bus Mode Register */
  135. #define BMR_GLB 0x20
  136. #define BMR_BO_BE 0x10
  137. #define BMR_DTB_SECONDARY_BUS 0x02
  138. #define BMR_BDB_SECONDARY_BUS 0x01
  139. #define BMR_SHIFT 24
  140. #define BMR_INIT_VALUE (BMR_GLB | BMR_BO_BE)
  141. /* UEC UCCS (Ethernet Status Register)
  142. */
  143. #define UCCS_BPR 0x02
  144. #define UCCS_PAU 0x02
  145. #define UCCS_MPD 0x01
  146. /* UEC MIIMCFG (MII Management Configuration Register)
  147. */
  148. #define MIIMCFG_RESET_MANAGEMENT 0x80000000
  149. #define MIIMCFG_NO_PREAMBLE 0x00000010
  150. #define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31)
  151. #define MIIMCFG_CLOCK_DIVIDE_MASK 0x0000000f
  152. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001
  153. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002
  154. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003
  155. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004
  156. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005
  157. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006
  158. #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007
  159. #define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE \
  160. MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10
  161. /* UEC MIIMCOM (MII Management Command Register)
  162. */
  163. #define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */
  164. #define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */
  165. /* UEC MIIMADD (MII Management Address Register)
  166. */
  167. #define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23)
  168. #define MIIMADD_PHY_REGISTER_SHIFT (31 - 31)
  169. /* UEC MIIMCON (MII Management Control Register)
  170. */
  171. #define MIIMCON_PHY_CONTROL_SHIFT (31 - 31)
  172. #define MIIMCON_PHY_STATUS_SHIFT (31 - 31)
  173. /* UEC MIIMIND (MII Management Indicator Register)
  174. */
  175. #define MIIMIND_NOT_VALID 0x00000004
  176. #define MIIMIND_SCAN 0x00000002
  177. #define MIIMIND_BUSY 0x00000001
  178. /* UEC UTBIPAR (Ten Bit Interface Physical Address Register)
  179. */
  180. #define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31)
  181. #define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f
  182. /* UEC UESCR (Ethernet Statistics Control Register)
  183. */
  184. #define UESCR_AUTOZ 0x8000
  185. #define UESCR_CLRCNT 0x4000
  186. #define UESCR_MAXCOV_SHIFT (15 - 7)
  187. #define UESCR_SCOV_SHIFT (15 - 15)
  188. /****** Tx data struct collection ******/
  189. /* Tx thread data, each Tx thread has one this struct.
  190. */
  191. typedef struct uec_thread_data_tx {
  192. u8 res0[136];
  193. } __attribute__ ((packed)) uec_thread_data_tx_t;
  194. /* Tx thread parameter, each Tx thread has one this struct.
  195. */
  196. typedef struct uec_thread_tx_pram {
  197. u8 res0[64];
  198. } __attribute__ ((packed)) uec_thread_tx_pram_t;
  199. /* Send queue queue-descriptor, each Tx queue has one this QD
  200. */
  201. typedef struct uec_send_queue_qd {
  202. u32 bd_ring_base; /* pointer to BD ring base address */
  203. u8 res0[0x8];
  204. u32 last_bd_completed_address; /* last entry in BD ring */
  205. u8 res1[0x30];
  206. } __attribute__ ((packed)) uec_send_queue_qd_t;
  207. /* Send queue memory region */
  208. typedef struct uec_send_queue_mem_region {
  209. uec_send_queue_qd_t sqqd[MAX_TX_QUEUES];
  210. } __attribute__ ((packed)) uec_send_queue_mem_region_t;
  211. /* Scheduler struct
  212. */
  213. typedef struct uec_scheduler {
  214. u16 cpucount0; /* CPU packet counter */
  215. u16 cpucount1; /* CPU packet counter */
  216. u16 cecount0; /* QE packet counter */
  217. u16 cecount1; /* QE packet counter */
  218. u16 cpucount2; /* CPU packet counter */
  219. u16 cpucount3; /* CPU packet counter */
  220. u16 cecount2; /* QE packet counter */
  221. u16 cecount3; /* QE packet counter */
  222. u16 cpucount4; /* CPU packet counter */
  223. u16 cpucount5; /* CPU packet counter */
  224. u16 cecount4; /* QE packet counter */
  225. u16 cecount5; /* QE packet counter */
  226. u16 cpucount6; /* CPU packet counter */
  227. u16 cpucount7; /* CPU packet counter */
  228. u16 cecount6; /* QE packet counter */
  229. u16 cecount7; /* QE packet counter */
  230. u32 weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */
  231. u32 rtsrshadow; /* temporary variable handled by QE */
  232. u32 time; /* temporary variable handled by QE */
  233. u32 ttl; /* temporary variable handled by QE */
  234. u32 mblinterval; /* max burst length interval */
  235. u16 nortsrbytetime; /* normalized value of byte time in tsr units */
  236. u8 fracsiz;
  237. u8 res0[1];
  238. u8 strictpriorityq; /* Strict Priority Mask register */
  239. u8 txasap; /* Transmit ASAP register */
  240. u8 extrabw; /* Extra BandWidth register */
  241. u8 oldwfqmask; /* temporary variable handled by QE */
  242. u8 weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */
  243. u32 minw; /* temporary variable handled by QE */
  244. u8 res1[0x70-0x64];
  245. } __attribute__ ((packed)) uec_scheduler_t;
  246. /* Tx firmware counters
  247. */
  248. typedef struct uec_tx_firmware_statistics_pram {
  249. u32 sicoltx; /* single collision */
  250. u32 mulcoltx; /* multiple collision */
  251. u32 latecoltxfr; /* late collision */
  252. u32 frabortduecol; /* frames aborted due to tx collision */
  253. u32 frlostinmactxer; /* frames lost due to internal MAC error tx */
  254. u32 carriersenseertx; /* carrier sense error */
  255. u32 frtxok; /* frames transmitted OK */
  256. u32 txfrexcessivedefer;
  257. u32 txpkts256; /* total packets(including bad) 256~511 B */
  258. u32 txpkts512; /* total packets(including bad) 512~1023B */
  259. u32 txpkts1024; /* total packets(including bad) 1024~1518B */
  260. u32 txpktsjumbo; /* total packets(including bad) >1024 */
  261. } __attribute__ ((packed)) uec_tx_firmware_statistics_pram_t;
  262. /* Tx global parameter table
  263. */
  264. typedef struct uec_tx_global_pram {
  265. u16 temoder;
  266. u8 res0[0x38-0x02];
  267. u32 sqptr;
  268. u32 schedulerbasepointer;
  269. u32 txrmonbaseptr;
  270. u32 tstate;
  271. u8 iphoffset[MAX_IPH_OFFSET_ENTRY];
  272. u32 vtagtable[0x8];
  273. u32 tqptr;
  274. u8 res2[0x80-0x74];
  275. } __attribute__ ((packed)) uec_tx_global_pram_t;
  276. /****** Rx data struct collection ******/
  277. /* Rx thread data, each Rx thread has one this struct.
  278. */
  279. typedef struct uec_thread_data_rx {
  280. u8 res0[40];
  281. } __attribute__ ((packed)) uec_thread_data_rx_t;
  282. /* Rx thread parameter, each Rx thread has one this struct.
  283. */
  284. typedef struct uec_thread_rx_pram {
  285. u8 res0[128];
  286. } __attribute__ ((packed)) uec_thread_rx_pram_t;
  287. /* Rx firmware counters
  288. */
  289. typedef struct uec_rx_firmware_statistics_pram {
  290. u32 frrxfcser; /* frames with crc error */
  291. u32 fraligner; /* frames with alignment error */
  292. u32 inrangelenrxer; /* in range length error */
  293. u32 outrangelenrxer; /* out of range length error */
  294. u32 frtoolong; /* frame too long */
  295. u32 runt; /* runt */
  296. u32 verylongevent; /* very long event */
  297. u32 symbolerror; /* symbol error */
  298. u32 dropbsy; /* drop because of BD not ready */
  299. u8 res0[0x8];
  300. u32 mismatchdrop; /* drop because of MAC filtering */
  301. u32 underpkts; /* total frames less than 64 octets */
  302. u32 pkts256; /* total frames(including bad)256~511 B */
  303. u32 pkts512; /* total frames(including bad)512~1023 B */
  304. u32 pkts1024; /* total frames(including bad)1024~1518 B */
  305. u32 pktsjumbo; /* total frames(including bad) >1024 B */
  306. u32 frlossinmacer;
  307. u32 pausefr; /* pause frames */
  308. u8 res1[0x4];
  309. u32 removevlan;
  310. u32 replacevlan;
  311. u32 insertvlan;
  312. } __attribute__ ((packed)) uec_rx_firmware_statistics_pram_t;
  313. /* Rx interrupt coalescing entry, each Rx queue has one this entry.
  314. */
  315. typedef struct uec_rx_interrupt_coalescing_entry {
  316. u32 maxvalue;
  317. u32 counter;
  318. } __attribute__ ((packed)) uec_rx_interrupt_coalescing_entry_t;
  319. typedef struct uec_rx_interrupt_coalescing_table {
  320. uec_rx_interrupt_coalescing_entry_t entry[MAX_RX_QUEUES];
  321. } __attribute__ ((packed)) uec_rx_interrupt_coalescing_table_t;
  322. /* RxBD queue entry, each Rx queue has one this entry.
  323. */
  324. typedef struct uec_rx_bd_queues_entry {
  325. u32 bdbaseptr; /* BD base pointer */
  326. u32 bdptr; /* BD pointer */
  327. u32 externalbdbaseptr; /* external BD base pointer */
  328. u32 externalbdptr; /* external BD pointer */
  329. } __attribute__ ((packed)) uec_rx_bd_queues_entry_t;
  330. /* Rx global paramter table
  331. */
  332. typedef struct uec_rx_global_pram {
  333. u32 remoder; /* ethernet mode reg. */
  334. u32 rqptr; /* base pointer to the Rx Queues */
  335. u32 res0[0x1];
  336. u8 res1[0x20-0xC];
  337. u16 typeorlen;
  338. u8 res2[0x1];
  339. u8 rxgstpack; /* ack on GRACEFUL STOP RX command */
  340. u32 rxrmonbaseptr; /* Rx RMON statistics base */
  341. u8 res3[0x30-0x28];
  342. u32 intcoalescingptr; /* Interrupt coalescing table pointer */
  343. u8 res4[0x36-0x34];
  344. u8 rstate;
  345. u8 res5[0x46-0x37];
  346. u16 mrblr; /* max receive buffer length reg. */
  347. u32 rbdqptr; /* RxBD parameter table description */
  348. u16 mflr; /* max frame length reg. */
  349. u16 minflr; /* min frame length reg. */
  350. u16 maxd1; /* max dma1 length reg. */
  351. u16 maxd2; /* max dma2 length reg. */
  352. u32 ecamptr; /* external CAM address */
  353. u32 l2qt; /* VLAN priority mapping table. */
  354. u32 l3qt[0x8]; /* IP priority mapping table. */
  355. u16 vlantype; /* vlan type */
  356. u16 vlantci; /* default vlan tci */
  357. u8 addressfiltering[64];/* address filtering data structure */
  358. u32 exfGlobalParam; /* extended filtering global parameters */
  359. u8 res6[0x100-0xC4]; /* Initialize to zero */
  360. } __attribute__ ((packed)) uec_rx_global_pram_t;
  361. #define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01
  362. /****** UEC common ******/
  363. /* UCC statistics - hardware counters
  364. */
  365. typedef struct uec_hardware_statistics {
  366. u32 tx64;
  367. u32 tx127;
  368. u32 tx255;
  369. u32 rx64;
  370. u32 rx127;
  371. u32 rx255;
  372. u32 txok;
  373. u16 txcf;
  374. u32 tmca;
  375. u32 tbca;
  376. u32 rxfok;
  377. u32 rxbok;
  378. u32 rbyt;
  379. u32 rmca;
  380. u32 rbca;
  381. } __attribute__ ((packed)) uec_hardware_statistics_t;
  382. /* InitEnet command parameter
  383. */
  384. typedef struct uec_init_cmd_pram {
  385. u8 resinit0;
  386. u8 resinit1;
  387. u8 resinit2;
  388. u8 resinit3;
  389. u16 resinit4;
  390. u8 res1[0x1];
  391. u8 largestexternallookupkeysize;
  392. u32 rgftgfrxglobal;
  393. u32 rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */
  394. u8 res2[0x38 - 0x30];
  395. u32 txglobal; /* tx global */
  396. u32 txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */
  397. u8 res3[0x1];
  398. } __attribute__ ((packed)) uec_init_cmd_pram_t;
  399. #define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)
  400. #define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)
  401. #define ENET_INIT_PARAM_RISC_MASK 0x0000003f
  402. #define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0
  403. #define ENET_INIT_PARAM_SNUM_MASK 0xff000000
  404. #define ENET_INIT_PARAM_SNUM_SHIFT 24
  405. #define ENET_INIT_PARAM_MAGIC_RES_INIT0 0x06
  406. #define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x30
  407. #define ENET_INIT_PARAM_MAGIC_RES_INIT2 0xff
  408. #define ENET_INIT_PARAM_MAGIC_RES_INIT3 0x00
  409. #define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x0400
  410. /* structure representing 82xx Address Filtering Enet Address in PRAM
  411. */
  412. typedef struct uec_82xx_enet_address {
  413. u8 res1[0x2];
  414. u16 h; /* address (MSB) */
  415. u16 m; /* address */
  416. u16 l; /* address (LSB) */
  417. } __attribute__ ((packed)) uec_82xx_enet_address_t;
  418. /* structure representing 82xx Address Filtering PRAM
  419. */
  420. typedef struct uec_82xx_address_filtering_pram {
  421. u32 iaddr_h; /* individual address filter, high */
  422. u32 iaddr_l; /* individual address filter, low */
  423. u32 gaddr_h; /* group address filter, high */
  424. u32 gaddr_l; /* group address filter, low */
  425. uec_82xx_enet_address_t taddr;
  426. uec_82xx_enet_address_t paddr[4];
  427. u8 res0[0x40-0x38];
  428. } __attribute__ ((packed)) uec_82xx_address_filtering_pram_t;
  429. /* Buffer Descriptor
  430. */
  431. typedef struct buffer_descriptor {
  432. u16 status;
  433. u16 len;
  434. u32 data;
  435. } __attribute__ ((packed)) qe_bd_t, *p_bd_t;
  436. #define SIZEOFBD sizeof(qe_bd_t)
  437. /* Common BD flags
  438. */
  439. #define BD_WRAP 0x2000
  440. #define BD_INT 0x1000
  441. #define BD_LAST 0x0800
  442. #define BD_CLEAN 0x3000
  443. /* TxBD status flags
  444. */
  445. #define TxBD_READY 0x8000
  446. #define TxBD_PADCRC 0x4000
  447. #define TxBD_WRAP BD_WRAP
  448. #define TxBD_INT BD_INT
  449. #define TxBD_LAST BD_LAST
  450. #define TxBD_TXCRC 0x0400
  451. #define TxBD_DEF 0x0200
  452. #define TxBD_PP 0x0100
  453. #define TxBD_LC 0x0080
  454. #define TxBD_RL 0x0040
  455. #define TxBD_RC 0x003C
  456. #define TxBD_UNDERRUN 0x0002
  457. #define TxBD_TRUNC 0x0001
  458. #define TxBD_ERROR (TxBD_UNDERRUN | TxBD_TRUNC)
  459. /* RxBD status flags
  460. */
  461. #define RxBD_EMPTY 0x8000
  462. #define RxBD_OWNER 0x4000
  463. #define RxBD_WRAP BD_WRAP
  464. #define RxBD_INT BD_INT
  465. #define RxBD_LAST BD_LAST
  466. #define RxBD_FIRST 0x0400
  467. #define RxBD_CMR 0x0200
  468. #define RxBD_MISS 0x0100
  469. #define RxBD_BCAST 0x0080
  470. #define RxBD_MCAST 0x0040
  471. #define RxBD_LG 0x0020
  472. #define RxBD_NO 0x0010
  473. #define RxBD_SHORT 0x0008
  474. #define RxBD_CRCERR 0x0004
  475. #define RxBD_OVERRUN 0x0002
  476. #define RxBD_IPCH 0x0001
  477. #define RxBD_ERROR (RxBD_LG | RxBD_NO | RxBD_SHORT | \
  478. RxBD_CRCERR | RxBD_OVERRUN)
  479. /* BD access macros
  480. */
  481. #define BD_STATUS(_bd) (((p_bd_t)(_bd))->status)
  482. #define BD_STATUS_SET(_bd, _val) (((p_bd_t)(_bd))->status = _val)
  483. #define BD_LENGTH(_bd) (((p_bd_t)(_bd))->len)
  484. #define BD_LENGTH_SET(_bd, _val) (((p_bd_t)(_bd))->len = _val)
  485. #define BD_DATA_CLEAR(_bd) (((p_bd_t)(_bd))->data = 0)
  486. #define BD_IS_DATA(_bd) (((p_bd_t)(_bd))->data)
  487. #define BD_DATA(_bd) ((u8 *)(((p_bd_t)(_bd))->data))
  488. #define BD_DATA_SET(_bd, _data) (((p_bd_t)(_bd))->data = (u32)(_data))
  489. #define BD_ADVANCE(_bd,_status,_base) \
  490. (((_status) & BD_WRAP) ? (_bd) = ((p_bd_t)(_base)) : ++(_bd))
  491. /* Rx Prefetched BDs
  492. */
  493. typedef struct uec_rx_prefetched_bds {
  494. qe_bd_t bd[MAX_PREFETCHED_BDS]; /* prefetched bd */
  495. } __attribute__ ((packed)) uec_rx_prefetched_bds_t;
  496. /* Alignments
  497. */
  498. #define UEC_RX_GLOBAL_PRAM_ALIGNMENT 64
  499. #define UEC_TX_GLOBAL_PRAM_ALIGNMENT 64
  500. #define UEC_THREAD_RX_PRAM_ALIGNMENT 128
  501. #define UEC_THREAD_TX_PRAM_ALIGNMENT 64
  502. #define UEC_THREAD_DATA_ALIGNMENT 256
  503. #define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32
  504. #define UEC_SCHEDULER_ALIGNMENT 4
  505. #define UEC_TX_STATISTICS_ALIGNMENT 4
  506. #define UEC_RX_STATISTICS_ALIGNMENT 4
  507. #define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT 4
  508. #define UEC_RX_BD_QUEUES_ALIGNMENT 8
  509. #define UEC_RX_PREFETCHED_BDS_ALIGNMENT 128
  510. #define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4
  511. #define UEC_RX_BD_RING_ALIGNMENT 32
  512. #define UEC_TX_BD_RING_ALIGNMENT 32
  513. #define UEC_MRBLR_ALIGNMENT 128
  514. #define UEC_RX_BD_RING_SIZE_ALIGNMENT 4
  515. #define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32
  516. #define UEC_RX_DATA_BUF_ALIGNMENT 64
  517. #define UEC_VLAN_PRIORITY_MAX 8
  518. #define UEC_IP_PRIORITY_MAX 64
  519. #define UEC_TX_VTAG_TABLE_ENTRY_MAX 8
  520. #define UEC_RX_BD_RING_SIZE_MIN 8
  521. #define UEC_TX_BD_RING_SIZE_MIN 2
  522. /* Ethernet speed
  523. */
  524. typedef enum enet_speed {
  525. ENET_SPEED_10BT, /* 10 Base T */
  526. ENET_SPEED_100BT, /* 100 Base T */
  527. ENET_SPEED_1000BT /* 1000 Base T */
  528. } enet_speed_e;
  529. /* Ethernet Address Type.
  530. */
  531. typedef enum enet_addr_type {
  532. ENET_ADDR_TYPE_INDIVIDUAL,
  533. ENET_ADDR_TYPE_GROUP,
  534. ENET_ADDR_TYPE_BROADCAST
  535. } enet_addr_type_e;
  536. /* TBI / MII Set Register
  537. */
  538. typedef enum enet_tbi_mii_reg {
  539. ENET_TBI_MII_CR = 0x00,
  540. ENET_TBI_MII_SR = 0x01,
  541. ENET_TBI_MII_ANA = 0x04,
  542. ENET_TBI_MII_ANLPBPA = 0x05,
  543. ENET_TBI_MII_ANEX = 0x06,
  544. ENET_TBI_MII_ANNPT = 0x07,
  545. ENET_TBI_MII_ANLPANP = 0x08,
  546. ENET_TBI_MII_EXST = 0x0F,
  547. ENET_TBI_MII_JD = 0x10,
  548. ENET_TBI_MII_TBICON = 0x11
  549. } enet_tbi_mii_reg_e;
  550. /* TBI MDIO register bit fields*/
  551. #define TBICON_CLK_SELECT 0x0020
  552. #define TBIANA_ASYMMETRIC_PAUSE 0x0100
  553. #define TBIANA_SYMMETRIC_PAUSE 0x0080
  554. #define TBIANA_HALF_DUPLEX 0x0040
  555. #define TBIANA_FULL_DUPLEX 0x0020
  556. #define TBICR_PHY_RESET 0x8000
  557. #define TBICR_ANEG_ENABLE 0x1000
  558. #define TBICR_RESTART_ANEG 0x0200
  559. #define TBICR_FULL_DUPLEX 0x0100
  560. #define TBICR_SPEED1_SET 0x0040
  561. #define TBIANA_SETTINGS ( \
  562. TBIANA_ASYMMETRIC_PAUSE \
  563. | TBIANA_SYMMETRIC_PAUSE \
  564. | TBIANA_FULL_DUPLEX \
  565. )
  566. #define TBICR_SETTINGS ( \
  567. TBICR_PHY_RESET \
  568. | TBICR_ANEG_ENABLE \
  569. | TBICR_FULL_DUPLEX \
  570. | TBICR_SPEED1_SET \
  571. )
  572. /* UEC number of threads
  573. */
  574. typedef enum uec_num_of_threads {
  575. UEC_NUM_OF_THREADS_1 = 0x1, /* 1 */
  576. UEC_NUM_OF_THREADS_2 = 0x2, /* 2 */
  577. UEC_NUM_OF_THREADS_4 = 0x0, /* 4 */
  578. UEC_NUM_OF_THREADS_6 = 0x3, /* 6 */
  579. UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */
  580. } uec_num_of_threads_e;
  581. /* UEC initialization info struct
  582. */
  583. #define STD_UEC_INFO(num) \
  584. { \
  585. .uf_info = { \
  586. .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\
  587. .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \
  588. .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \
  589. .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\
  590. }, \
  591. .num_threads_tx = UEC_NUM_OF_THREADS_1, \
  592. .num_threads_rx = UEC_NUM_OF_THREADS_1, \
  593. .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
  594. .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
  595. .tx_bd_ring_len = 16, \
  596. .rx_bd_ring_len = 16, \
  597. .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \
  598. .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \
  599. .speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \
  600. }
  601. typedef struct uec_info {
  602. ucc_fast_info_t uf_info;
  603. uec_num_of_threads_e num_threads_tx;
  604. uec_num_of_threads_e num_threads_rx;
  605. unsigned int risc_tx;
  606. unsigned int risc_rx;
  607. u16 rx_bd_ring_len;
  608. u16 tx_bd_ring_len;
  609. u8 phy_address;
  610. phy_interface_t enet_interface_type;
  611. int speed;
  612. } uec_info_t;
  613. /* UEC driver initialized info
  614. */
  615. #define MAX_RXBUF_LEN 1536
  616. #define MAX_FRAME_LEN 1518
  617. #define MIN_FRAME_LEN 64
  618. #define MAX_DMA1_LEN 1520
  619. #define MAX_DMA2_LEN 1520
  620. /* UEC driver private struct
  621. */
  622. typedef struct uec_private {
  623. uec_info_t *uec_info;
  624. ucc_fast_private_t *uccf;
  625. struct eth_device *dev;
  626. uec_t *uec_regs;
  627. uec_mii_t *uec_mii_regs;
  628. /* enet init command parameter */
  629. uec_init_cmd_pram_t *p_init_enet_param;
  630. u32 init_enet_param_offset;
  631. /* Rx and Tx paramter */
  632. uec_rx_global_pram_t *p_rx_glbl_pram;
  633. u32 rx_glbl_pram_offset;
  634. uec_tx_global_pram_t *p_tx_glbl_pram;
  635. u32 tx_glbl_pram_offset;
  636. uec_send_queue_mem_region_t *p_send_q_mem_reg;
  637. u32 send_q_mem_reg_offset;
  638. uec_thread_data_tx_t *p_thread_data_tx;
  639. u32 thread_dat_tx_offset;
  640. uec_thread_data_rx_t *p_thread_data_rx;
  641. u32 thread_dat_rx_offset;
  642. uec_rx_bd_queues_entry_t *p_rx_bd_qs_tbl;
  643. u32 rx_bd_qs_tbl_offset;
  644. /* BDs specific */
  645. u8 *p_tx_bd_ring;
  646. u32 tx_bd_ring_offset;
  647. u8 *p_rx_bd_ring;
  648. u32 rx_bd_ring_offset;
  649. u8 *p_rx_buf;
  650. u32 rx_buf_offset;
  651. volatile qe_bd_t *txBd;
  652. volatile qe_bd_t *rxBd;
  653. /* Status */
  654. int mac_tx_enabled;
  655. int mac_rx_enabled;
  656. int grace_stopped_tx;
  657. int grace_stopped_rx;
  658. int the_first_run;
  659. /* PHY specific */
  660. struct uec_mii_info *mii_info;
  661. int oldspeed;
  662. int oldduplex;
  663. int oldlink;
  664. } uec_private_t;
  665. int uec_initialize(bd_t *bis, uec_info_t *uec_info);
  666. int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num);
  667. int uec_standard_init(bd_t *bis);
  668. #endif /* __UEC_H__ */