uec.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2006-2011 Freescale Semiconductor, Inc.
  4. *
  5. * Dave Liu <daveliu@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <net.h>
  9. #include <malloc.h>
  10. #include <linux/errno.h>
  11. #include <asm/io.h>
  12. #include <linux/immap_qe.h>
  13. #include "uccf.h"
  14. #include "uec.h"
  15. #include "uec_phy.h"
  16. #include "miiphy.h"
  17. #include <fsl_qe.h>
  18. #include <phy.h>
  19. /* Default UTBIPAR SMI address */
  20. #ifndef CONFIG_UTBIPAR_INIT_TBIPA
  21. #define CONFIG_UTBIPAR_INIT_TBIPA 0x1F
  22. #endif
  23. static uec_info_t uec_info[] = {
  24. #ifdef CONFIG_UEC_ETH1
  25. STD_UEC_INFO(1), /* UEC1 */
  26. #endif
  27. #ifdef CONFIG_UEC_ETH2
  28. STD_UEC_INFO(2), /* UEC2 */
  29. #endif
  30. #ifdef CONFIG_UEC_ETH3
  31. STD_UEC_INFO(3), /* UEC3 */
  32. #endif
  33. #ifdef CONFIG_UEC_ETH4
  34. STD_UEC_INFO(4), /* UEC4 */
  35. #endif
  36. #ifdef CONFIG_UEC_ETH5
  37. STD_UEC_INFO(5), /* UEC5 */
  38. #endif
  39. #ifdef CONFIG_UEC_ETH6
  40. STD_UEC_INFO(6), /* UEC6 */
  41. #endif
  42. #ifdef CONFIG_UEC_ETH7
  43. STD_UEC_INFO(7), /* UEC7 */
  44. #endif
  45. #ifdef CONFIG_UEC_ETH8
  46. STD_UEC_INFO(8), /* UEC8 */
  47. #endif
  48. };
  49. #define MAXCONTROLLERS (8)
  50. static struct eth_device *devlist[MAXCONTROLLERS];
  51. static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
  52. {
  53. uec_t *uec_regs;
  54. u32 maccfg1;
  55. if (!uec) {
  56. printf("%s: uec not initial\n", __FUNCTION__);
  57. return -EINVAL;
  58. }
  59. uec_regs = uec->uec_regs;
  60. maccfg1 = in_be32(&uec_regs->maccfg1);
  61. if (mode & COMM_DIR_TX) {
  62. maccfg1 |= MACCFG1_ENABLE_TX;
  63. out_be32(&uec_regs->maccfg1, maccfg1);
  64. uec->mac_tx_enabled = 1;
  65. }
  66. if (mode & COMM_DIR_RX) {
  67. maccfg1 |= MACCFG1_ENABLE_RX;
  68. out_be32(&uec_regs->maccfg1, maccfg1);
  69. uec->mac_rx_enabled = 1;
  70. }
  71. return 0;
  72. }
  73. static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
  74. {
  75. uec_t *uec_regs;
  76. u32 maccfg1;
  77. if (!uec) {
  78. printf("%s: uec not initial\n", __FUNCTION__);
  79. return -EINVAL;
  80. }
  81. uec_regs = uec->uec_regs;
  82. maccfg1 = in_be32(&uec_regs->maccfg1);
  83. if (mode & COMM_DIR_TX) {
  84. maccfg1 &= ~MACCFG1_ENABLE_TX;
  85. out_be32(&uec_regs->maccfg1, maccfg1);
  86. uec->mac_tx_enabled = 0;
  87. }
  88. if (mode & COMM_DIR_RX) {
  89. maccfg1 &= ~MACCFG1_ENABLE_RX;
  90. out_be32(&uec_regs->maccfg1, maccfg1);
  91. uec->mac_rx_enabled = 0;
  92. }
  93. return 0;
  94. }
  95. static int uec_graceful_stop_tx(uec_private_t *uec)
  96. {
  97. ucc_fast_t *uf_regs;
  98. u32 cecr_subblock;
  99. u32 ucce;
  100. if (!uec || !uec->uccf) {
  101. printf("%s: No handle passed.\n", __FUNCTION__);
  102. return -EINVAL;
  103. }
  104. uf_regs = uec->uccf->uf_regs;
  105. /* Clear the grace stop event */
  106. out_be32(&uf_regs->ucce, UCCE_GRA);
  107. /* Issue host command */
  108. cecr_subblock =
  109. ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
  110. qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
  111. (u8)QE_CR_PROTOCOL_ETHERNET, 0);
  112. /* Wait for command to complete */
  113. do {
  114. ucce = in_be32(&uf_regs->ucce);
  115. } while (! (ucce & UCCE_GRA));
  116. uec->grace_stopped_tx = 1;
  117. return 0;
  118. }
  119. static int uec_graceful_stop_rx(uec_private_t *uec)
  120. {
  121. u32 cecr_subblock;
  122. u8 ack;
  123. if (!uec) {
  124. printf("%s: No handle passed.\n", __FUNCTION__);
  125. return -EINVAL;
  126. }
  127. if (!uec->p_rx_glbl_pram) {
  128. printf("%s: No init rx global parameter\n", __FUNCTION__);
  129. return -EINVAL;
  130. }
  131. /* Clear acknowledge bit */
  132. ack = uec->p_rx_glbl_pram->rxgstpack;
  133. ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
  134. uec->p_rx_glbl_pram->rxgstpack = ack;
  135. /* Keep issuing cmd and checking ack bit until it is asserted */
  136. do {
  137. /* Issue host command */
  138. cecr_subblock =
  139. ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
  140. qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
  141. (u8)QE_CR_PROTOCOL_ETHERNET, 0);
  142. ack = uec->p_rx_glbl_pram->rxgstpack;
  143. } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
  144. uec->grace_stopped_rx = 1;
  145. return 0;
  146. }
  147. static int uec_restart_tx(uec_private_t *uec)
  148. {
  149. u32 cecr_subblock;
  150. if (!uec || !uec->uec_info) {
  151. printf("%s: No handle passed.\n", __FUNCTION__);
  152. return -EINVAL;
  153. }
  154. cecr_subblock =
  155. ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
  156. qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
  157. (u8)QE_CR_PROTOCOL_ETHERNET, 0);
  158. uec->grace_stopped_tx = 0;
  159. return 0;
  160. }
  161. static int uec_restart_rx(uec_private_t *uec)
  162. {
  163. u32 cecr_subblock;
  164. if (!uec || !uec->uec_info) {
  165. printf("%s: No handle passed.\n", __FUNCTION__);
  166. return -EINVAL;
  167. }
  168. cecr_subblock =
  169. ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
  170. qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
  171. (u8)QE_CR_PROTOCOL_ETHERNET, 0);
  172. uec->grace_stopped_rx = 0;
  173. return 0;
  174. }
  175. static int uec_open(uec_private_t *uec, comm_dir_e mode)
  176. {
  177. ucc_fast_private_t *uccf;
  178. if (!uec || !uec->uccf) {
  179. printf("%s: No handle passed.\n", __FUNCTION__);
  180. return -EINVAL;
  181. }
  182. uccf = uec->uccf;
  183. /* check if the UCC number is in range. */
  184. if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
  185. printf("%s: ucc_num out of range.\n", __FUNCTION__);
  186. return -EINVAL;
  187. }
  188. /* Enable MAC */
  189. uec_mac_enable(uec, mode);
  190. /* Enable UCC fast */
  191. ucc_fast_enable(uccf, mode);
  192. /* RISC microcode start */
  193. if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
  194. uec_restart_tx(uec);
  195. }
  196. if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
  197. uec_restart_rx(uec);
  198. }
  199. return 0;
  200. }
  201. static int uec_stop(uec_private_t *uec, comm_dir_e mode)
  202. {
  203. if (!uec || !uec->uccf) {
  204. printf("%s: No handle passed.\n", __FUNCTION__);
  205. return -EINVAL;
  206. }
  207. /* check if the UCC number is in range. */
  208. if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
  209. printf("%s: ucc_num out of range.\n", __FUNCTION__);
  210. return -EINVAL;
  211. }
  212. /* Stop any transmissions */
  213. if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
  214. uec_graceful_stop_tx(uec);
  215. }
  216. /* Stop any receptions */
  217. if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
  218. uec_graceful_stop_rx(uec);
  219. }
  220. /* Disable the UCC fast */
  221. ucc_fast_disable(uec->uccf, mode);
  222. /* Disable the MAC */
  223. uec_mac_disable(uec, mode);
  224. return 0;
  225. }
  226. static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
  227. {
  228. uec_t *uec_regs;
  229. u32 maccfg2;
  230. if (!uec) {
  231. printf("%s: uec not initial\n", __FUNCTION__);
  232. return -EINVAL;
  233. }
  234. uec_regs = uec->uec_regs;
  235. if (duplex == DUPLEX_HALF) {
  236. maccfg2 = in_be32(&uec_regs->maccfg2);
  237. maccfg2 &= ~MACCFG2_FDX;
  238. out_be32(&uec_regs->maccfg2, maccfg2);
  239. }
  240. if (duplex == DUPLEX_FULL) {
  241. maccfg2 = in_be32(&uec_regs->maccfg2);
  242. maccfg2 |= MACCFG2_FDX;
  243. out_be32(&uec_regs->maccfg2, maccfg2);
  244. }
  245. return 0;
  246. }
  247. static int uec_set_mac_if_mode(uec_private_t *uec,
  248. phy_interface_t if_mode, int speed)
  249. {
  250. phy_interface_t enet_if_mode;
  251. uec_t *uec_regs;
  252. u32 upsmr;
  253. u32 maccfg2;
  254. if (!uec) {
  255. printf("%s: uec not initial\n", __FUNCTION__);
  256. return -EINVAL;
  257. }
  258. uec_regs = uec->uec_regs;
  259. enet_if_mode = if_mode;
  260. maccfg2 = in_be32(&uec_regs->maccfg2);
  261. maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
  262. upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
  263. upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
  264. switch (speed) {
  265. case SPEED_10:
  266. maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
  267. switch (enet_if_mode) {
  268. case PHY_INTERFACE_MODE_MII:
  269. break;
  270. case PHY_INTERFACE_MODE_RGMII:
  271. upsmr |= (UPSMR_RPM | UPSMR_R10M);
  272. break;
  273. case PHY_INTERFACE_MODE_RMII:
  274. upsmr |= (UPSMR_R10M | UPSMR_RMM);
  275. break;
  276. default:
  277. return -EINVAL;
  278. break;
  279. }
  280. break;
  281. case SPEED_100:
  282. maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
  283. switch (enet_if_mode) {
  284. case PHY_INTERFACE_MODE_MII:
  285. break;
  286. case PHY_INTERFACE_MODE_RGMII:
  287. upsmr |= UPSMR_RPM;
  288. break;
  289. case PHY_INTERFACE_MODE_RMII:
  290. upsmr |= UPSMR_RMM;
  291. break;
  292. default:
  293. return -EINVAL;
  294. break;
  295. }
  296. break;
  297. case SPEED_1000:
  298. maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
  299. switch (enet_if_mode) {
  300. case PHY_INTERFACE_MODE_GMII:
  301. break;
  302. case PHY_INTERFACE_MODE_TBI:
  303. upsmr |= UPSMR_TBIM;
  304. break;
  305. case PHY_INTERFACE_MODE_RTBI:
  306. upsmr |= (UPSMR_RPM | UPSMR_TBIM);
  307. break;
  308. case PHY_INTERFACE_MODE_RGMII_RXID:
  309. case PHY_INTERFACE_MODE_RGMII_TXID:
  310. case PHY_INTERFACE_MODE_RGMII_ID:
  311. case PHY_INTERFACE_MODE_RGMII:
  312. upsmr |= UPSMR_RPM;
  313. break;
  314. case PHY_INTERFACE_MODE_SGMII:
  315. upsmr |= UPSMR_SGMM;
  316. break;
  317. default:
  318. return -EINVAL;
  319. break;
  320. }
  321. break;
  322. default:
  323. return -EINVAL;
  324. break;
  325. }
  326. out_be32(&uec_regs->maccfg2, maccfg2);
  327. out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
  328. return 0;
  329. }
  330. static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
  331. {
  332. uint timeout = 0x1000;
  333. u32 miimcfg = 0;
  334. miimcfg = in_be32(&uec_mii_regs->miimcfg);
  335. miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
  336. out_be32(&uec_mii_regs->miimcfg, miimcfg);
  337. /* Wait until the bus is free */
  338. while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
  339. if (timeout <= 0) {
  340. printf("%s: The MII Bus is stuck!", __FUNCTION__);
  341. return -ETIMEDOUT;
  342. }
  343. return 0;
  344. }
  345. static int init_phy(struct eth_device *dev)
  346. {
  347. uec_private_t *uec;
  348. uec_mii_t *umii_regs;
  349. struct uec_mii_info *mii_info;
  350. struct phy_info *curphy;
  351. int err;
  352. uec = (uec_private_t *)dev->priv;
  353. umii_regs = uec->uec_mii_regs;
  354. uec->oldlink = 0;
  355. uec->oldspeed = 0;
  356. uec->oldduplex = -1;
  357. mii_info = malloc(sizeof(*mii_info));
  358. if (!mii_info) {
  359. printf("%s: Could not allocate mii_info", dev->name);
  360. return -ENOMEM;
  361. }
  362. memset(mii_info, 0, sizeof(*mii_info));
  363. if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
  364. mii_info->speed = SPEED_1000;
  365. } else {
  366. mii_info->speed = SPEED_100;
  367. }
  368. mii_info->duplex = DUPLEX_FULL;
  369. mii_info->pause = 0;
  370. mii_info->link = 1;
  371. mii_info->advertising = (ADVERTISED_10baseT_Half |
  372. ADVERTISED_10baseT_Full |
  373. ADVERTISED_100baseT_Half |
  374. ADVERTISED_100baseT_Full |
  375. ADVERTISED_1000baseT_Full);
  376. mii_info->autoneg = 1;
  377. mii_info->mii_id = uec->uec_info->phy_address;
  378. mii_info->dev = dev;
  379. mii_info->mdio_read = &uec_read_phy_reg;
  380. mii_info->mdio_write = &uec_write_phy_reg;
  381. uec->mii_info = mii_info;
  382. qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
  383. if (init_mii_management_configuration(umii_regs)) {
  384. printf("%s: The MII Bus is stuck!", dev->name);
  385. err = -1;
  386. goto bus_fail;
  387. }
  388. /* get info for this PHY */
  389. curphy = uec_get_phy_info(uec->mii_info);
  390. if (!curphy) {
  391. printf("%s: No PHY found", dev->name);
  392. err = -1;
  393. goto no_phy;
  394. }
  395. mii_info->phyinfo = curphy;
  396. /* Run the commands which initialize the PHY */
  397. if (curphy->init) {
  398. err = curphy->init(uec->mii_info);
  399. if (err)
  400. goto phy_init_fail;
  401. }
  402. return 0;
  403. phy_init_fail:
  404. no_phy:
  405. bus_fail:
  406. free(mii_info);
  407. return err;
  408. }
  409. static void adjust_link(struct eth_device *dev)
  410. {
  411. uec_private_t *uec = (uec_private_t *)dev->priv;
  412. struct uec_mii_info *mii_info = uec->mii_info;
  413. extern void change_phy_interface_mode(struct eth_device *dev,
  414. phy_interface_t mode, int speed);
  415. if (mii_info->link) {
  416. /* Now we make sure that we can be in full duplex mode.
  417. * If not, we operate in half-duplex mode. */
  418. if (mii_info->duplex != uec->oldduplex) {
  419. if (!(mii_info->duplex)) {
  420. uec_set_mac_duplex(uec, DUPLEX_HALF);
  421. printf("%s: Half Duplex\n", dev->name);
  422. } else {
  423. uec_set_mac_duplex(uec, DUPLEX_FULL);
  424. printf("%s: Full Duplex\n", dev->name);
  425. }
  426. uec->oldduplex = mii_info->duplex;
  427. }
  428. if (mii_info->speed != uec->oldspeed) {
  429. phy_interface_t mode =
  430. uec->uec_info->enet_interface_type;
  431. if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
  432. switch (mii_info->speed) {
  433. case SPEED_1000:
  434. break;
  435. case SPEED_100:
  436. printf ("switching to rgmii 100\n");
  437. mode = PHY_INTERFACE_MODE_RGMII;
  438. break;
  439. case SPEED_10:
  440. printf ("switching to rgmii 10\n");
  441. mode = PHY_INTERFACE_MODE_RGMII;
  442. break;
  443. default:
  444. printf("%s: Ack,Speed(%d)is illegal\n",
  445. dev->name, mii_info->speed);
  446. break;
  447. }
  448. }
  449. /* change phy */
  450. change_phy_interface_mode(dev, mode, mii_info->speed);
  451. /* change the MAC interface mode */
  452. uec_set_mac_if_mode(uec, mode, mii_info->speed);
  453. printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
  454. uec->oldspeed = mii_info->speed;
  455. }
  456. if (!uec->oldlink) {
  457. printf("%s: Link is up\n", dev->name);
  458. uec->oldlink = 1;
  459. }
  460. } else { /* if (mii_info->link) */
  461. if (uec->oldlink) {
  462. printf("%s: Link is down\n", dev->name);
  463. uec->oldlink = 0;
  464. uec->oldspeed = 0;
  465. uec->oldduplex = -1;
  466. }
  467. }
  468. }
  469. static void phy_change(struct eth_device *dev)
  470. {
  471. uec_private_t *uec = (uec_private_t *)dev->priv;
  472. #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
  473. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  474. /* QE9 and QE12 need to be set for enabling QE MII managment signals */
  475. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
  476. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
  477. #endif
  478. /* Update the link, speed, duplex */
  479. uec->mii_info->phyinfo->read_status(uec->mii_info);
  480. #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
  481. /*
  482. * QE12 is muxed with LBCTL, it needs to be released for enabling
  483. * LBCTL signal for LBC usage.
  484. */
  485. clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
  486. #endif
  487. /* Adjust the interface according to speed */
  488. adjust_link(dev);
  489. }
  490. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  491. /*
  492. * Find a device index from the devlist by name
  493. *
  494. * Returns:
  495. * The index where the device is located, -1 on error
  496. */
  497. static int uec_miiphy_find_dev_by_name(const char *devname)
  498. {
  499. int i;
  500. for (i = 0; i < MAXCONTROLLERS; i++) {
  501. if (strncmp(devname, devlist[i]->name, strlen(devname)) == 0) {
  502. break;
  503. }
  504. }
  505. /* If device cannot be found, returns -1 */
  506. if (i == MAXCONTROLLERS) {
  507. debug ("%s: device %s not found in devlist\n", __FUNCTION__, devname);
  508. i = -1;
  509. }
  510. return i;
  511. }
  512. /*
  513. * Read a MII PHY register.
  514. *
  515. * Returns:
  516. * 0 on success
  517. */
  518. static int uec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
  519. {
  520. unsigned short value = 0;
  521. int devindex = 0;
  522. if (bus->name == NULL) {
  523. debug("%s: NULL pointer given\n", __FUNCTION__);
  524. } else {
  525. devindex = uec_miiphy_find_dev_by_name(bus->name);
  526. if (devindex >= 0) {
  527. value = uec_read_phy_reg(devlist[devindex], addr, reg);
  528. }
  529. }
  530. return value;
  531. }
  532. /*
  533. * Write a MII PHY register.
  534. *
  535. * Returns:
  536. * 0 on success
  537. */
  538. static int uec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
  539. u16 value)
  540. {
  541. int devindex = 0;
  542. if (bus->name == NULL) {
  543. debug("%s: NULL pointer given\n", __FUNCTION__);
  544. } else {
  545. devindex = uec_miiphy_find_dev_by_name(bus->name);
  546. if (devindex >= 0) {
  547. uec_write_phy_reg(devlist[devindex], addr, reg, value);
  548. }
  549. }
  550. return 0;
  551. }
  552. #endif
  553. static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
  554. {
  555. uec_t *uec_regs;
  556. u32 mac_addr1;
  557. u32 mac_addr2;
  558. if (!uec) {
  559. printf("%s: uec not initial\n", __FUNCTION__);
  560. return -EINVAL;
  561. }
  562. uec_regs = uec->uec_regs;
  563. /* if a station address of 0x12345678ABCD, perform a write to
  564. MACSTNADDR1 of 0xCDAB7856,
  565. MACSTNADDR2 of 0x34120000 */
  566. mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
  567. (mac_addr[3] << 8) | (mac_addr[2]);
  568. out_be32(&uec_regs->macstnaddr1, mac_addr1);
  569. mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
  570. out_be32(&uec_regs->macstnaddr2, mac_addr2);
  571. return 0;
  572. }
  573. static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
  574. int *threads_num_ret)
  575. {
  576. int num_threads_numerica;
  577. switch (threads_num) {
  578. case UEC_NUM_OF_THREADS_1:
  579. num_threads_numerica = 1;
  580. break;
  581. case UEC_NUM_OF_THREADS_2:
  582. num_threads_numerica = 2;
  583. break;
  584. case UEC_NUM_OF_THREADS_4:
  585. num_threads_numerica = 4;
  586. break;
  587. case UEC_NUM_OF_THREADS_6:
  588. num_threads_numerica = 6;
  589. break;
  590. case UEC_NUM_OF_THREADS_8:
  591. num_threads_numerica = 8;
  592. break;
  593. default:
  594. printf("%s: Bad number of threads value.",
  595. __FUNCTION__);
  596. return -EINVAL;
  597. }
  598. *threads_num_ret = num_threads_numerica;
  599. return 0;
  600. }
  601. static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
  602. {
  603. uec_info_t *uec_info;
  604. u32 end_bd;
  605. u8 bmrx = 0;
  606. int i;
  607. uec_info = uec->uec_info;
  608. /* Alloc global Tx parameter RAM page */
  609. uec->tx_glbl_pram_offset = qe_muram_alloc(
  610. sizeof(uec_tx_global_pram_t),
  611. UEC_TX_GLOBAL_PRAM_ALIGNMENT);
  612. uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
  613. qe_muram_addr(uec->tx_glbl_pram_offset);
  614. /* Zero the global Tx prameter RAM */
  615. memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
  616. /* Init global Tx parameter RAM */
  617. /* TEMODER, RMON statistics disable, one Tx queue */
  618. out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
  619. /* SQPTR */
  620. uec->send_q_mem_reg_offset = qe_muram_alloc(
  621. sizeof(uec_send_queue_qd_t),
  622. UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
  623. uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
  624. qe_muram_addr(uec->send_q_mem_reg_offset);
  625. out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
  626. /* Setup the table with TxBDs ring */
  627. end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
  628. * SIZEOFBD;
  629. out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
  630. (u32)(uec->p_tx_bd_ring));
  631. out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
  632. end_bd);
  633. /* Scheduler Base Pointer, we have only one Tx queue, no need it */
  634. out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
  635. /* TxRMON Base Pointer, TxRMON disable, we don't need it */
  636. out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
  637. /* TSTATE, global snooping, big endian, the CSB bus selected */
  638. bmrx = BMR_INIT_VALUE;
  639. out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
  640. /* IPH_Offset */
  641. for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
  642. out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
  643. }
  644. /* VTAG table */
  645. for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
  646. out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
  647. }
  648. /* TQPTR */
  649. uec->thread_dat_tx_offset = qe_muram_alloc(
  650. num_threads_tx * sizeof(uec_thread_data_tx_t) +
  651. 32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
  652. uec->p_thread_data_tx = (uec_thread_data_tx_t *)
  653. qe_muram_addr(uec->thread_dat_tx_offset);
  654. out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
  655. }
  656. static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
  657. {
  658. u8 bmrx = 0;
  659. int i;
  660. uec_82xx_address_filtering_pram_t *p_af_pram;
  661. /* Allocate global Rx parameter RAM page */
  662. uec->rx_glbl_pram_offset = qe_muram_alloc(
  663. sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
  664. uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
  665. qe_muram_addr(uec->rx_glbl_pram_offset);
  666. /* Zero Global Rx parameter RAM */
  667. memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
  668. /* Init global Rx parameter RAM */
  669. /* REMODER, Extended feature mode disable, VLAN disable,
  670. LossLess flow control disable, Receive firmware statisic disable,
  671. Extended address parsing mode disable, One Rx queues,
  672. Dynamic maximum/minimum frame length disable, IP checksum check
  673. disable, IP address alignment disable
  674. */
  675. out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
  676. /* RQPTR */
  677. uec->thread_dat_rx_offset = qe_muram_alloc(
  678. num_threads_rx * sizeof(uec_thread_data_rx_t),
  679. UEC_THREAD_DATA_ALIGNMENT);
  680. uec->p_thread_data_rx = (uec_thread_data_rx_t *)
  681. qe_muram_addr(uec->thread_dat_rx_offset);
  682. out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
  683. /* Type_or_Len */
  684. out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
  685. /* RxRMON base pointer, we don't need it */
  686. out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
  687. /* IntCoalescingPTR, we don't need it, no interrupt */
  688. out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
  689. /* RSTATE, global snooping, big endian, the CSB bus selected */
  690. bmrx = BMR_INIT_VALUE;
  691. out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
  692. /* MRBLR */
  693. out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
  694. /* RBDQPTR */
  695. uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
  696. sizeof(uec_rx_bd_queues_entry_t) + \
  697. sizeof(uec_rx_prefetched_bds_t),
  698. UEC_RX_BD_QUEUES_ALIGNMENT);
  699. uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
  700. qe_muram_addr(uec->rx_bd_qs_tbl_offset);
  701. /* Zero it */
  702. memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
  703. sizeof(uec_rx_prefetched_bds_t));
  704. out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
  705. out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
  706. (u32)uec->p_rx_bd_ring);
  707. /* MFLR */
  708. out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
  709. /* MINFLR */
  710. out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
  711. /* MAXD1 */
  712. out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
  713. /* MAXD2 */
  714. out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
  715. /* ECAM_PTR */
  716. out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
  717. /* L2QT */
  718. out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
  719. /* L3QT */
  720. for (i = 0; i < 8; i++) {
  721. out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
  722. }
  723. /* VLAN_TYPE */
  724. out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
  725. /* TCI */
  726. out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
  727. /* Clear PQ2 style address filtering hash table */
  728. p_af_pram = (uec_82xx_address_filtering_pram_t *) \
  729. uec->p_rx_glbl_pram->addressfiltering;
  730. p_af_pram->iaddr_h = 0;
  731. p_af_pram->iaddr_l = 0;
  732. p_af_pram->gaddr_h = 0;
  733. p_af_pram->gaddr_l = 0;
  734. }
  735. static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
  736. int thread_tx, int thread_rx)
  737. {
  738. uec_init_cmd_pram_t *p_init_enet_param;
  739. u32 init_enet_param_offset;
  740. uec_info_t *uec_info;
  741. int i;
  742. int snum;
  743. u32 init_enet_offset;
  744. u32 entry_val;
  745. u32 command;
  746. u32 cecr_subblock;
  747. uec_info = uec->uec_info;
  748. /* Allocate init enet command parameter */
  749. uec->init_enet_param_offset = qe_muram_alloc(
  750. sizeof(uec_init_cmd_pram_t), 4);
  751. init_enet_param_offset = uec->init_enet_param_offset;
  752. uec->p_init_enet_param = (uec_init_cmd_pram_t *)
  753. qe_muram_addr(uec->init_enet_param_offset);
  754. /* Zero init enet command struct */
  755. memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
  756. /* Init the command struct */
  757. p_init_enet_param = uec->p_init_enet_param;
  758. p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
  759. p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
  760. p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
  761. p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
  762. p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
  763. p_init_enet_param->largestexternallookupkeysize = 0;
  764. p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
  765. << ENET_INIT_PARAM_RGF_SHIFT;
  766. p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
  767. << ENET_INIT_PARAM_TGF_SHIFT;
  768. /* Init Rx global parameter pointer */
  769. p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
  770. (u32)uec_info->risc_rx;
  771. /* Init Rx threads */
  772. for (i = 0; i < (thread_rx + 1); i++) {
  773. if ((snum = qe_get_snum()) < 0) {
  774. printf("%s can not get snum\n", __FUNCTION__);
  775. return -ENOMEM;
  776. }
  777. if (i==0) {
  778. init_enet_offset = 0;
  779. } else {
  780. init_enet_offset = qe_muram_alloc(
  781. sizeof(uec_thread_rx_pram_t),
  782. UEC_THREAD_RX_PRAM_ALIGNMENT);
  783. }
  784. entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
  785. init_enet_offset | (u32)uec_info->risc_rx;
  786. p_init_enet_param->rxthread[i] = entry_val;
  787. }
  788. /* Init Tx global parameter pointer */
  789. p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
  790. (u32)uec_info->risc_tx;
  791. /* Init Tx threads */
  792. for (i = 0; i < thread_tx; i++) {
  793. if ((snum = qe_get_snum()) < 0) {
  794. printf("%s can not get snum\n", __FUNCTION__);
  795. return -ENOMEM;
  796. }
  797. init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
  798. UEC_THREAD_TX_PRAM_ALIGNMENT);
  799. entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
  800. init_enet_offset | (u32)uec_info->risc_tx;
  801. p_init_enet_param->txthread[i] = entry_val;
  802. }
  803. __asm__ __volatile__("sync");
  804. /* Issue QE command */
  805. command = QE_INIT_TX_RX;
  806. cecr_subblock = ucc_fast_get_qe_cr_subblock(
  807. uec->uec_info->uf_info.ucc_num);
  808. qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
  809. init_enet_param_offset);
  810. return 0;
  811. }
  812. static int uec_startup(uec_private_t *uec)
  813. {
  814. uec_info_t *uec_info;
  815. ucc_fast_info_t *uf_info;
  816. ucc_fast_private_t *uccf;
  817. ucc_fast_t *uf_regs;
  818. uec_t *uec_regs;
  819. int num_threads_tx;
  820. int num_threads_rx;
  821. u32 utbipar;
  822. u32 length;
  823. u32 align;
  824. qe_bd_t *bd;
  825. u8 *buf;
  826. int i;
  827. if (!uec || !uec->uec_info) {
  828. printf("%s: uec or uec_info not initial\n", __FUNCTION__);
  829. return -EINVAL;
  830. }
  831. uec_info = uec->uec_info;
  832. uf_info = &(uec_info->uf_info);
  833. /* Check if Rx BD ring len is illegal */
  834. if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
  835. (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
  836. printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
  837. __FUNCTION__);
  838. return -EINVAL;
  839. }
  840. /* Check if Tx BD ring len is illegal */
  841. if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
  842. printf("%s: Tx BD ring length must not be smaller than 2.\n",
  843. __FUNCTION__);
  844. return -EINVAL;
  845. }
  846. /* Check if MRBLR is illegal */
  847. if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT)) {
  848. printf("%s: max rx buffer length must be mutliple of 128.\n",
  849. __FUNCTION__);
  850. return -EINVAL;
  851. }
  852. /* Both Rx and Tx are stopped */
  853. uec->grace_stopped_rx = 1;
  854. uec->grace_stopped_tx = 1;
  855. /* Init UCC fast */
  856. if (ucc_fast_init(uf_info, &uccf)) {
  857. printf("%s: failed to init ucc fast\n", __FUNCTION__);
  858. return -ENOMEM;
  859. }
  860. /* Save uccf */
  861. uec->uccf = uccf;
  862. /* Convert the Tx threads number */
  863. if (uec_convert_threads_num(uec_info->num_threads_tx,
  864. &num_threads_tx)) {
  865. return -EINVAL;
  866. }
  867. /* Convert the Rx threads number */
  868. if (uec_convert_threads_num(uec_info->num_threads_rx,
  869. &num_threads_rx)) {
  870. return -EINVAL;
  871. }
  872. uf_regs = uccf->uf_regs;
  873. /* UEC register is following UCC fast registers */
  874. uec_regs = (uec_t *)(&uf_regs->ucc_eth);
  875. /* Save the UEC register pointer to UEC private struct */
  876. uec->uec_regs = uec_regs;
  877. /* Init UPSMR, enable hardware statistics (UCC) */
  878. out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
  879. /* Init MACCFG1, flow control disable, disable Tx and Rx */
  880. out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
  881. /* Init MACCFG2, length check, MAC PAD and CRC enable */
  882. out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
  883. /* Setup MAC interface mode */
  884. uec_set_mac_if_mode(uec, uec_info->enet_interface_type, uec_info->speed);
  885. /* Setup MII management base */
  886. #ifndef CONFIG_eTSEC_MDIO_BUS
  887. uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
  888. #else
  889. uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
  890. #endif
  891. /* Setup MII master clock source */
  892. qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
  893. /* Setup UTBIPAR */
  894. utbipar = in_be32(&uec_regs->utbipar);
  895. utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
  896. /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
  897. * This frees up the remaining SMI addresses for use.
  898. */
  899. utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT;
  900. out_be32(&uec_regs->utbipar, utbipar);
  901. /* Configure the TBI for SGMII operation */
  902. if ((uec->uec_info->enet_interface_type == PHY_INTERFACE_MODE_SGMII) &&
  903. (uec->uec_info->speed == SPEED_1000)) {
  904. uec_write_phy_reg(uec->dev, uec_regs->utbipar,
  905. ENET_TBI_MII_ANA, TBIANA_SETTINGS);
  906. uec_write_phy_reg(uec->dev, uec_regs->utbipar,
  907. ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
  908. uec_write_phy_reg(uec->dev, uec_regs->utbipar,
  909. ENET_TBI_MII_CR, TBICR_SETTINGS);
  910. }
  911. /* Allocate Tx BDs */
  912. length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
  913. UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
  914. UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
  915. if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
  916. UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
  917. length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
  918. }
  919. align = UEC_TX_BD_RING_ALIGNMENT;
  920. uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
  921. if (uec->tx_bd_ring_offset != 0) {
  922. uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
  923. & ~(align - 1));
  924. }
  925. /* Zero all of Tx BDs */
  926. memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
  927. /* Allocate Rx BDs */
  928. length = uec_info->rx_bd_ring_len * SIZEOFBD;
  929. align = UEC_RX_BD_RING_ALIGNMENT;
  930. uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
  931. if (uec->rx_bd_ring_offset != 0) {
  932. uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
  933. & ~(align - 1));
  934. }
  935. /* Zero all of Rx BDs */
  936. memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
  937. /* Allocate Rx buffer */
  938. length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
  939. align = UEC_RX_DATA_BUF_ALIGNMENT;
  940. uec->rx_buf_offset = (u32)malloc(length + align);
  941. if (uec->rx_buf_offset != 0) {
  942. uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
  943. & ~(align - 1));
  944. }
  945. /* Zero all of the Rx buffer */
  946. memset((void *)(uec->rx_buf_offset), 0, length + align);
  947. /* Init TxBD ring */
  948. bd = (qe_bd_t *)uec->p_tx_bd_ring;
  949. uec->txBd = bd;
  950. for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
  951. BD_DATA_CLEAR(bd);
  952. BD_STATUS_SET(bd, 0);
  953. BD_LENGTH_SET(bd, 0);
  954. bd ++;
  955. }
  956. BD_STATUS_SET((--bd), TxBD_WRAP);
  957. /* Init RxBD ring */
  958. bd = (qe_bd_t *)uec->p_rx_bd_ring;
  959. uec->rxBd = bd;
  960. buf = uec->p_rx_buf;
  961. for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
  962. BD_DATA_SET(bd, buf);
  963. BD_LENGTH_SET(bd, 0);
  964. BD_STATUS_SET(bd, RxBD_EMPTY);
  965. buf += MAX_RXBUF_LEN;
  966. bd ++;
  967. }
  968. BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
  969. /* Init global Tx parameter RAM */
  970. uec_init_tx_parameter(uec, num_threads_tx);
  971. /* Init global Rx parameter RAM */
  972. uec_init_rx_parameter(uec, num_threads_rx);
  973. /* Init ethernet Tx and Rx parameter command */
  974. if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
  975. num_threads_rx)) {
  976. printf("%s issue init enet cmd failed\n", __FUNCTION__);
  977. return -ENOMEM;
  978. }
  979. return 0;
  980. }
  981. static int uec_init(struct eth_device* dev, bd_t *bd)
  982. {
  983. uec_private_t *uec;
  984. int err, i;
  985. struct phy_info *curphy;
  986. #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
  987. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  988. #endif
  989. uec = (uec_private_t *)dev->priv;
  990. if (uec->the_first_run == 0) {
  991. #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
  992. /* QE9 and QE12 need to be set for enabling QE MII managment signals */
  993. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
  994. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
  995. #endif
  996. err = init_phy(dev);
  997. if (err) {
  998. printf("%s: Cannot initialize PHY, aborting.\n",
  999. dev->name);
  1000. return err;
  1001. }
  1002. curphy = uec->mii_info->phyinfo;
  1003. if (curphy->config_aneg) {
  1004. err = curphy->config_aneg(uec->mii_info);
  1005. if (err) {
  1006. printf("%s: Can't negotiate PHY\n", dev->name);
  1007. return err;
  1008. }
  1009. }
  1010. /* Give PHYs up to 5 sec to report a link */
  1011. i = 50;
  1012. do {
  1013. err = curphy->read_status(uec->mii_info);
  1014. if (!(((i-- > 0) && !uec->mii_info->link) || err))
  1015. break;
  1016. udelay(100000);
  1017. } while (1);
  1018. #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
  1019. /* QE12 needs to be released for enabling LBCTL signal*/
  1020. clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
  1021. #endif
  1022. if (err || i <= 0)
  1023. printf("warning: %s: timeout on PHY link\n", dev->name);
  1024. adjust_link(dev);
  1025. uec->the_first_run = 1;
  1026. }
  1027. /* Set up the MAC address */
  1028. if (dev->enetaddr[0] & 0x01) {
  1029. printf("%s: MacAddress is multcast address\n",
  1030. __FUNCTION__);
  1031. return -1;
  1032. }
  1033. uec_set_mac_address(uec, dev->enetaddr);
  1034. err = uec_open(uec, COMM_DIR_RX_AND_TX);
  1035. if (err) {
  1036. printf("%s: cannot enable UEC device\n", dev->name);
  1037. return -1;
  1038. }
  1039. phy_change(dev);
  1040. return (uec->mii_info->link ? 0 : -1);
  1041. }
  1042. static void uec_halt(struct eth_device* dev)
  1043. {
  1044. uec_private_t *uec = (uec_private_t *)dev->priv;
  1045. uec_stop(uec, COMM_DIR_RX_AND_TX);
  1046. }
  1047. static int uec_send(struct eth_device *dev, void *buf, int len)
  1048. {
  1049. uec_private_t *uec;
  1050. ucc_fast_private_t *uccf;
  1051. volatile qe_bd_t *bd;
  1052. u16 status;
  1053. int i;
  1054. int result = 0;
  1055. uec = (uec_private_t *)dev->priv;
  1056. uccf = uec->uccf;
  1057. bd = uec->txBd;
  1058. /* Find an empty TxBD */
  1059. for (i = 0; bd->status & TxBD_READY; i++) {
  1060. if (i > 0x100000) {
  1061. printf("%s: tx buffer not ready\n", dev->name);
  1062. return result;
  1063. }
  1064. }
  1065. /* Init TxBD */
  1066. BD_DATA_SET(bd, buf);
  1067. BD_LENGTH_SET(bd, len);
  1068. status = bd->status;
  1069. status &= BD_WRAP;
  1070. status |= (TxBD_READY | TxBD_LAST);
  1071. BD_STATUS_SET(bd, status);
  1072. /* Tell UCC to transmit the buffer */
  1073. ucc_fast_transmit_on_demand(uccf);
  1074. /* Wait for buffer to be transmitted */
  1075. for (i = 0; bd->status & TxBD_READY; i++) {
  1076. if (i > 0x100000) {
  1077. printf("%s: tx error\n", dev->name);
  1078. return result;
  1079. }
  1080. }
  1081. /* Ok, the buffer be transimitted */
  1082. BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
  1083. uec->txBd = bd;
  1084. result = 1;
  1085. return result;
  1086. }
  1087. static int uec_recv(struct eth_device* dev)
  1088. {
  1089. uec_private_t *uec = dev->priv;
  1090. volatile qe_bd_t *bd;
  1091. u16 status;
  1092. u16 len;
  1093. u8 *data;
  1094. bd = uec->rxBd;
  1095. status = bd->status;
  1096. while (!(status & RxBD_EMPTY)) {
  1097. if (!(status & RxBD_ERROR)) {
  1098. data = BD_DATA(bd);
  1099. len = BD_LENGTH(bd);
  1100. net_process_received_packet(data, len);
  1101. } else {
  1102. printf("%s: Rx error\n", dev->name);
  1103. }
  1104. status &= BD_CLEAN;
  1105. BD_LENGTH_SET(bd, 0);
  1106. BD_STATUS_SET(bd, status | RxBD_EMPTY);
  1107. BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
  1108. status = bd->status;
  1109. }
  1110. uec->rxBd = bd;
  1111. return 1;
  1112. }
  1113. int uec_initialize(bd_t *bis, uec_info_t *uec_info)
  1114. {
  1115. struct eth_device *dev;
  1116. int i;
  1117. uec_private_t *uec;
  1118. int err;
  1119. dev = (struct eth_device *)malloc(sizeof(struct eth_device));
  1120. if (!dev)
  1121. return 0;
  1122. memset(dev, 0, sizeof(struct eth_device));
  1123. /* Allocate the UEC private struct */
  1124. uec = (uec_private_t *)malloc(sizeof(uec_private_t));
  1125. if (!uec) {
  1126. return -ENOMEM;
  1127. }
  1128. memset(uec, 0, sizeof(uec_private_t));
  1129. /* Adjust uec_info */
  1130. #if (MAX_QE_RISC == 4)
  1131. uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS;
  1132. uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS;
  1133. #endif
  1134. devlist[uec_info->uf_info.ucc_num] = dev;
  1135. uec->uec_info = uec_info;
  1136. uec->dev = dev;
  1137. sprintf(dev->name, "UEC%d", uec_info->uf_info.ucc_num);
  1138. dev->iobase = 0;
  1139. dev->priv = (void *)uec;
  1140. dev->init = uec_init;
  1141. dev->halt = uec_halt;
  1142. dev->send = uec_send;
  1143. dev->recv = uec_recv;
  1144. /* Clear the ethnet address */
  1145. for (i = 0; i < 6; i++)
  1146. dev->enetaddr[i] = 0;
  1147. eth_register(dev);
  1148. err = uec_startup(uec);
  1149. if (err) {
  1150. printf("%s: Cannot configure net device, aborting.",dev->name);
  1151. return err;
  1152. }
  1153. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  1154. int retval;
  1155. struct mii_dev *mdiodev = mdio_alloc();
  1156. if (!mdiodev)
  1157. return -ENOMEM;
  1158. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  1159. mdiodev->read = uec_miiphy_read;
  1160. mdiodev->write = uec_miiphy_write;
  1161. retval = mdio_register(mdiodev);
  1162. if (retval < 0)
  1163. return retval;
  1164. #endif
  1165. return 1;
  1166. }
  1167. int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num)
  1168. {
  1169. int i;
  1170. for (i = 0; i < num; i++)
  1171. uec_initialize(bis, &uecs[i]);
  1172. return 0;
  1173. }
  1174. int uec_standard_init(bd_t *bis)
  1175. {
  1176. return uec_eth_init(bis, uec_info, ARRAY_SIZE(uec_info));
  1177. }