uccf.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2006 Freescale Semiconductor, Inc.
  4. *
  5. * Dave Liu <daveliu@freescale.com>
  6. * based on source code of Shlomi Gridish
  7. */
  8. #include <common.h>
  9. #include <malloc.h>
  10. #include <linux/errno.h>
  11. #include <asm/io.h>
  12. #include <linux/immap_qe.h>
  13. #include "uccf.h"
  14. #include <fsl_qe.h>
  15. void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf)
  16. {
  17. out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
  18. }
  19. u32 ucc_fast_get_qe_cr_subblock(int ucc_num)
  20. {
  21. switch (ucc_num) {
  22. case 0: return QE_CR_SUBBLOCK_UCCFAST1;
  23. case 1: return QE_CR_SUBBLOCK_UCCFAST2;
  24. case 2: return QE_CR_SUBBLOCK_UCCFAST3;
  25. case 3: return QE_CR_SUBBLOCK_UCCFAST4;
  26. case 4: return QE_CR_SUBBLOCK_UCCFAST5;
  27. case 5: return QE_CR_SUBBLOCK_UCCFAST6;
  28. case 6: return QE_CR_SUBBLOCK_UCCFAST7;
  29. case 7: return QE_CR_SUBBLOCK_UCCFAST8;
  30. default: return QE_CR_SUBBLOCK_INVALID;
  31. }
  32. }
  33. static void ucc_get_cmxucr_reg(int ucc_num, volatile u32 **p_cmxucr,
  34. u8 *reg_num, u8 *shift)
  35. {
  36. switch (ucc_num) {
  37. case 0: /* UCC1 */
  38. *p_cmxucr = &(qe_immr->qmx.cmxucr1);
  39. *reg_num = 1;
  40. *shift = 16;
  41. break;
  42. case 2: /* UCC3 */
  43. *p_cmxucr = &(qe_immr->qmx.cmxucr1);
  44. *reg_num = 1;
  45. *shift = 0;
  46. break;
  47. case 4: /* UCC5 */
  48. *p_cmxucr = &(qe_immr->qmx.cmxucr2);
  49. *reg_num = 2;
  50. *shift = 16;
  51. break;
  52. case 6: /* UCC7 */
  53. *p_cmxucr = &(qe_immr->qmx.cmxucr2);
  54. *reg_num = 2;
  55. *shift = 0;
  56. break;
  57. case 1: /* UCC2 */
  58. *p_cmxucr = &(qe_immr->qmx.cmxucr3);
  59. *reg_num = 3;
  60. *shift = 16;
  61. break;
  62. case 3: /* UCC4 */
  63. *p_cmxucr = &(qe_immr->qmx.cmxucr3);
  64. *reg_num = 3;
  65. *shift = 0;
  66. break;
  67. case 5: /* UCC6 */
  68. *p_cmxucr = &(qe_immr->qmx.cmxucr4);
  69. *reg_num = 4;
  70. *shift = 16;
  71. break;
  72. case 7: /* UCC8 */
  73. *p_cmxucr = &(qe_immr->qmx.cmxucr4);
  74. *reg_num = 4;
  75. *shift = 0;
  76. break;
  77. default:
  78. break;
  79. }
  80. }
  81. static int ucc_set_clk_src(int ucc_num, qe_clock_e clock, comm_dir_e mode)
  82. {
  83. volatile u32 *p_cmxucr = NULL;
  84. u8 reg_num = 0;
  85. u8 shift = 0;
  86. u32 clockBits;
  87. u32 clockMask;
  88. int source = -1;
  89. /* check if the UCC number is in range. */
  90. if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))
  91. return -EINVAL;
  92. if (! ((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX))) {
  93. printf("%s: bad comm mode type passed\n", __FUNCTION__);
  94. return -EINVAL;
  95. }
  96. ucc_get_cmxucr_reg(ucc_num, &p_cmxucr, &reg_num, &shift);
  97. switch (reg_num) {
  98. case 1:
  99. switch (clock) {
  100. case QE_BRG1: source = 1; break;
  101. case QE_BRG2: source = 2; break;
  102. case QE_BRG7: source = 3; break;
  103. case QE_BRG8: source = 4; break;
  104. case QE_CLK9: source = 5; break;
  105. case QE_CLK10: source = 6; break;
  106. case QE_CLK11: source = 7; break;
  107. case QE_CLK12: source = 8; break;
  108. case QE_CLK15: source = 9; break;
  109. case QE_CLK16: source = 10; break;
  110. default: source = -1; break;
  111. }
  112. break;
  113. case 2:
  114. switch (clock) {
  115. case QE_BRG5: source = 1; break;
  116. case QE_BRG6: source = 2; break;
  117. case QE_BRG7: source = 3; break;
  118. case QE_BRG8: source = 4; break;
  119. case QE_CLK13: source = 5; break;
  120. case QE_CLK14: source = 6; break;
  121. case QE_CLK19: source = 7; break;
  122. case QE_CLK20: source = 8; break;
  123. case QE_CLK15: source = 9; break;
  124. case QE_CLK16: source = 10; break;
  125. default: source = -1; break;
  126. }
  127. break;
  128. case 3:
  129. switch (clock) {
  130. case QE_BRG9: source = 1; break;
  131. case QE_BRG10: source = 2; break;
  132. case QE_BRG15: source = 3; break;
  133. case QE_BRG16: source = 4; break;
  134. case QE_CLK3: source = 5; break;
  135. case QE_CLK4: source = 6; break;
  136. case QE_CLK17: source = 7; break;
  137. case QE_CLK18: source = 8; break;
  138. case QE_CLK7: source = 9; break;
  139. case QE_CLK8: source = 10; break;
  140. case QE_CLK16: source = 11; break;
  141. default: source = -1; break;
  142. }
  143. break;
  144. case 4:
  145. switch (clock) {
  146. case QE_BRG13: source = 1; break;
  147. case QE_BRG14: source = 2; break;
  148. case QE_BRG15: source = 3; break;
  149. case QE_BRG16: source = 4; break;
  150. case QE_CLK5: source = 5; break;
  151. case QE_CLK6: source = 6; break;
  152. case QE_CLK21: source = 7; break;
  153. case QE_CLK22: source = 8; break;
  154. case QE_CLK7: source = 9; break;
  155. case QE_CLK8: source = 10; break;
  156. case QE_CLK16: source = 11; break;
  157. default: source = -1; break;
  158. }
  159. break;
  160. default:
  161. source = -1;
  162. break;
  163. }
  164. if (source == -1) {
  165. printf("%s: Bad combination of clock and UCC\n", __FUNCTION__);
  166. return -ENOENT;
  167. }
  168. clockBits = (u32) source;
  169. clockMask = QE_CMXUCR_TX_CLK_SRC_MASK;
  170. if (mode == COMM_DIR_RX) {
  171. clockBits <<= 4; /* Rx field is 4 bits to left of Tx field */
  172. clockMask <<= 4; /* Rx field is 4 bits to left of Tx field */
  173. }
  174. clockBits <<= shift;
  175. clockMask <<= shift;
  176. out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clockMask) | clockBits);
  177. return 0;
  178. }
  179. static uint ucc_get_reg_baseaddr(int ucc_num)
  180. {
  181. uint base = 0;
  182. /* check if the UCC number is in range */
  183. if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
  184. printf("%s: the UCC num not in ranges\n", __FUNCTION__);
  185. return 0;
  186. }
  187. switch (ucc_num) {
  188. case 0: base = 0x00002000; break;
  189. case 1: base = 0x00003000; break;
  190. case 2: base = 0x00002200; break;
  191. case 3: base = 0x00003200; break;
  192. case 4: base = 0x00002400; break;
  193. case 5: base = 0x00003400; break;
  194. case 6: base = 0x00002600; break;
  195. case 7: base = 0x00003600; break;
  196. default: break;
  197. }
  198. base = (uint)qe_immr + base;
  199. return base;
  200. }
  201. void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode)
  202. {
  203. ucc_fast_t *uf_regs;
  204. u32 gumr;
  205. uf_regs = uccf->uf_regs;
  206. /* Enable reception and/or transmission on this UCC. */
  207. gumr = in_be32(&uf_regs->gumr);
  208. if (mode & COMM_DIR_TX) {
  209. gumr |= UCC_FAST_GUMR_ENT;
  210. uccf->enabled_tx = 1;
  211. }
  212. if (mode & COMM_DIR_RX) {
  213. gumr |= UCC_FAST_GUMR_ENR;
  214. uccf->enabled_rx = 1;
  215. }
  216. out_be32(&uf_regs->gumr, gumr);
  217. }
  218. void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode)
  219. {
  220. ucc_fast_t *uf_regs;
  221. u32 gumr;
  222. uf_regs = uccf->uf_regs;
  223. /* Disable reception and/or transmission on this UCC. */
  224. gumr = in_be32(&uf_regs->gumr);
  225. if (mode & COMM_DIR_TX) {
  226. gumr &= ~UCC_FAST_GUMR_ENT;
  227. uccf->enabled_tx = 0;
  228. }
  229. if (mode & COMM_DIR_RX) {
  230. gumr &= ~UCC_FAST_GUMR_ENR;
  231. uccf->enabled_rx = 0;
  232. }
  233. out_be32(&uf_regs->gumr, gumr);
  234. }
  235. int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret)
  236. {
  237. ucc_fast_private_t *uccf;
  238. ucc_fast_t *uf_regs;
  239. if (!uf_info)
  240. return -EINVAL;
  241. if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
  242. printf("%s: Illagal UCC number!\n", __FUNCTION__);
  243. return -EINVAL;
  244. }
  245. uccf = (ucc_fast_private_t *)malloc(sizeof(ucc_fast_private_t));
  246. if (!uccf) {
  247. printf("%s: No memory for UCC fast data structure!\n",
  248. __FUNCTION__);
  249. return -ENOMEM;
  250. }
  251. memset(uccf, 0, sizeof(ucc_fast_private_t));
  252. /* Save fast UCC structure */
  253. uccf->uf_info = uf_info;
  254. uccf->uf_regs = (ucc_fast_t *)ucc_get_reg_baseaddr(uf_info->ucc_num);
  255. if (uccf->uf_regs == NULL) {
  256. printf("%s: No memory map for UCC fast controller!\n",
  257. __FUNCTION__);
  258. return -ENOMEM;
  259. }
  260. uccf->enabled_tx = 0;
  261. uccf->enabled_rx = 0;
  262. uf_regs = uccf->uf_regs;
  263. uccf->p_ucce = (u32 *) &(uf_regs->ucce);
  264. uccf->p_uccm = (u32 *) &(uf_regs->uccm);
  265. /* Init GUEMR register, UCC both Rx and Tx is Fast protocol */
  266. out_8(&uf_regs->guemr, UCC_GUEMR_SET_RESERVED3 | UCC_GUEMR_MODE_FAST_RX
  267. | UCC_GUEMR_MODE_FAST_TX);
  268. /* Set GUMR, disable UCC both Rx and Tx, Ethernet protocol */
  269. out_be32(&uf_regs->gumr, UCC_FAST_GUMR_ETH);
  270. /* Set the Giga ethernet VFIFO stuff */
  271. if (uf_info->eth_type == GIGA_ETH) {
  272. /* Allocate memory for Tx Virtual Fifo */
  273. uccf->ucc_fast_tx_virtual_fifo_base_offset =
  274. qe_muram_alloc(UCC_GETH_UTFS_GIGA_INIT,
  275. UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
  276. /* Allocate memory for Rx Virtual Fifo */
  277. uccf->ucc_fast_rx_virtual_fifo_base_offset =
  278. qe_muram_alloc(UCC_GETH_URFS_GIGA_INIT +
  279. UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
  280. UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
  281. /* utfb, urfb are offsets from MURAM base */
  282. out_be32(&uf_regs->utfb,
  283. uccf->ucc_fast_tx_virtual_fifo_base_offset);
  284. out_be32(&uf_regs->urfb,
  285. uccf->ucc_fast_rx_virtual_fifo_base_offset);
  286. /* Set Virtual Fifo registers */
  287. out_be16(&uf_regs->urfs, UCC_GETH_URFS_GIGA_INIT);
  288. out_be16(&uf_regs->urfet, UCC_GETH_URFET_GIGA_INIT);
  289. out_be16(&uf_regs->urfset, UCC_GETH_URFSET_GIGA_INIT);
  290. out_be16(&uf_regs->utfs, UCC_GETH_UTFS_GIGA_INIT);
  291. out_be16(&uf_regs->utfet, UCC_GETH_UTFET_GIGA_INIT);
  292. out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_GIGA_INIT);
  293. }
  294. /* Set the Fast ethernet VFIFO stuff */
  295. if (uf_info->eth_type == FAST_ETH) {
  296. /* Allocate memory for Tx Virtual Fifo */
  297. uccf->ucc_fast_tx_virtual_fifo_base_offset =
  298. qe_muram_alloc(UCC_GETH_UTFS_INIT,
  299. UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
  300. /* Allocate memory for Rx Virtual Fifo */
  301. uccf->ucc_fast_rx_virtual_fifo_base_offset =
  302. qe_muram_alloc(UCC_GETH_URFS_INIT +
  303. UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
  304. UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
  305. /* utfb, urfb are offsets from MURAM base */
  306. out_be32(&uf_regs->utfb,
  307. uccf->ucc_fast_tx_virtual_fifo_base_offset);
  308. out_be32(&uf_regs->urfb,
  309. uccf->ucc_fast_rx_virtual_fifo_base_offset);
  310. /* Set Virtual Fifo registers */
  311. out_be16(&uf_regs->urfs, UCC_GETH_URFS_INIT);
  312. out_be16(&uf_regs->urfet, UCC_GETH_URFET_INIT);
  313. out_be16(&uf_regs->urfset, UCC_GETH_URFSET_INIT);
  314. out_be16(&uf_regs->utfs, UCC_GETH_UTFS_INIT);
  315. out_be16(&uf_regs->utfet, UCC_GETH_UTFET_INIT);
  316. out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_INIT);
  317. }
  318. /* Rx clock routing */
  319. if (uf_info->rx_clock != QE_CLK_NONE) {
  320. if (ucc_set_clk_src(uf_info->ucc_num,
  321. uf_info->rx_clock, COMM_DIR_RX)) {
  322. printf("%s: Illegal value for parameter 'RxClock'.\n",
  323. __FUNCTION__);
  324. return -EINVAL;
  325. }
  326. }
  327. /* Tx clock routing */
  328. if (uf_info->tx_clock != QE_CLK_NONE) {
  329. if (ucc_set_clk_src(uf_info->ucc_num,
  330. uf_info->tx_clock, COMM_DIR_TX)) {
  331. printf("%s: Illegal value for parameter 'TxClock'.\n",
  332. __FUNCTION__);
  333. return -EINVAL;
  334. }
  335. }
  336. /* Clear interrupt mask register to disable all of interrupts */
  337. out_be32(&uf_regs->uccm, 0x0);
  338. /* Writing '1' to clear all of envents */
  339. out_be32(&uf_regs->ucce, 0xffffffff);
  340. *uccf_ret = uccf;
  341. return 0;
  342. }