zynqpl.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012-2013, Xilinx, Michal Simek
  4. *
  5. * (C) Copyright 2012
  6. * Joe Hershberger <joe.hershberger@ni.com>
  7. */
  8. #include <common.h>
  9. #include <console.h>
  10. #include <cpu_func.h>
  11. #include <asm/io.h>
  12. #include <fs.h>
  13. #include <zynqpl.h>
  14. #include <linux/sizes.h>
  15. #include <asm/arch/hardware.h>
  16. #include <asm/arch/sys_proto.h>
  17. #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
  18. #define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000
  19. #define DEVCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000
  20. #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
  21. #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
  22. #define DEVCFG_ISR_RX_FIFO_OV 0x00040000
  23. #define DEVCFG_ISR_DMA_DONE 0x00002000
  24. #define DEVCFG_ISR_PCFG_DONE 0x00000004
  25. #define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000
  26. #define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000
  27. #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
  28. #define DEVCFG_STATUS_PCFG_INIT 0x00000010
  29. #define DEVCFG_MCTRL_PCAP_LPBK 0x00000010
  30. #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002
  31. #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001
  32. #ifndef CONFIG_SYS_FPGA_WAIT
  33. #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
  34. #endif
  35. #ifndef CONFIG_SYS_FPGA_PROG_TIME
  36. #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
  37. #endif
  38. #define DUMMY_WORD 0xffffffff
  39. /* Xilinx binary format header */
  40. static const u32 bin_format[] = {
  41. DUMMY_WORD, /* Dummy words */
  42. DUMMY_WORD,
  43. DUMMY_WORD,
  44. DUMMY_WORD,
  45. DUMMY_WORD,
  46. DUMMY_WORD,
  47. DUMMY_WORD,
  48. DUMMY_WORD,
  49. 0x000000bb, /* Sync word */
  50. 0x11220044, /* Sync word */
  51. DUMMY_WORD,
  52. DUMMY_WORD,
  53. 0xaa995566, /* Sync word */
  54. };
  55. #define SWAP_NO 1
  56. #define SWAP_DONE 2
  57. /*
  58. * Load the whole word from unaligned buffer
  59. * Keep in your mind that it is byte loading on little-endian system
  60. */
  61. static u32 load_word(const void *buf, u32 swap)
  62. {
  63. u32 word = 0;
  64. u8 *bitc = (u8 *)buf;
  65. int p;
  66. if (swap == SWAP_NO) {
  67. for (p = 0; p < 4; p++) {
  68. word <<= 8;
  69. word |= bitc[p];
  70. }
  71. } else {
  72. for (p = 3; p >= 0; p--) {
  73. word <<= 8;
  74. word |= bitc[p];
  75. }
  76. }
  77. return word;
  78. }
  79. static u32 check_header(const void *buf)
  80. {
  81. u32 i, pattern;
  82. int swap = SWAP_NO;
  83. u32 *test = (u32 *)buf;
  84. debug("%s: Let's check bitstream header\n", __func__);
  85. /* Checking that passing bin is not a bitstream */
  86. for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
  87. pattern = load_word(&test[i], swap);
  88. /*
  89. * Bitstreams in binary format are swapped
  90. * compare to regular bistream.
  91. * Do not swap dummy word but if swap is done assume
  92. * that parsing buffer is binary format
  93. */
  94. if ((__swab32(pattern) != DUMMY_WORD) &&
  95. (__swab32(pattern) == bin_format[i])) {
  96. pattern = __swab32(pattern);
  97. swap = SWAP_DONE;
  98. debug("%s: data swapped - let's swap\n", __func__);
  99. }
  100. debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i,
  101. (u32)&test[i], pattern, bin_format[i]);
  102. if (pattern != bin_format[i]) {
  103. debug("%s: Bitstream is not recognized\n", __func__);
  104. return 0;
  105. }
  106. }
  107. debug("%s: Found bitstream header at %x %s swapinng\n", __func__,
  108. (u32)buf, swap == SWAP_NO ? "without" : "with");
  109. return swap;
  110. }
  111. static void *check_data(u8 *buf, size_t bsize, u32 *swap)
  112. {
  113. u32 word, p = 0; /* possition */
  114. /* Because buf doesn't need to be aligned let's read it by chars */
  115. for (p = 0; p < bsize; p++) {
  116. word = load_word(&buf[p], SWAP_NO);
  117. debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]);
  118. /* Find the first bitstream dummy word */
  119. if (word == DUMMY_WORD) {
  120. debug("%s: Found dummy word at position %x/%x\n",
  121. __func__, p, (u32)&buf[p]);
  122. *swap = check_header(&buf[p]);
  123. if (*swap) {
  124. /* FIXME add full bitstream checking here */
  125. return &buf[p];
  126. }
  127. }
  128. /* Loop can be huge - support CTRL + C */
  129. if (ctrlc())
  130. return NULL;
  131. }
  132. return NULL;
  133. }
  134. static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
  135. {
  136. unsigned long ts;
  137. u32 isr_status;
  138. /* Set up the transfer */
  139. writel((u32)srcbuf, &devcfg_base->dma_src_addr);
  140. writel(dstbuf, &devcfg_base->dma_dst_addr);
  141. writel(srclen, &devcfg_base->dma_src_len);
  142. writel(dstlen, &devcfg_base->dma_dst_len);
  143. isr_status = readl(&devcfg_base->int_sts);
  144. /* Polling the PCAP_INIT status for Set */
  145. ts = get_timer(0);
  146. while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
  147. if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
  148. debug("%s: Error: isr = 0x%08X\n", __func__,
  149. isr_status);
  150. debug("%s: Write count = 0x%08X\n", __func__,
  151. readl(&devcfg_base->write_count));
  152. debug("%s: Read count = 0x%08X\n", __func__,
  153. readl(&devcfg_base->read_count));
  154. return FPGA_FAIL;
  155. }
  156. if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
  157. printf("%s: Timeout wait for DMA to complete\n",
  158. __func__);
  159. return FPGA_FAIL;
  160. }
  161. isr_status = readl(&devcfg_base->int_sts);
  162. }
  163. debug("%s: DMA transfer is done\n", __func__);
  164. /* Clear out the DMA status */
  165. writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
  166. return FPGA_SUCCESS;
  167. }
  168. static int zynq_dma_xfer_init(bitstream_type bstype)
  169. {
  170. u32 status, control, isr_status;
  171. unsigned long ts;
  172. /* Clear loopback bit */
  173. clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
  174. if (bstype != BIT_PARTIAL) {
  175. zynq_slcr_devcfg_disable();
  176. /* Setting PCFG_PROG_B signal to high */
  177. control = readl(&devcfg_base->ctrl);
  178. writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
  179. /*
  180. * Delay is required if AES efuse is selected as
  181. * key source.
  182. */
  183. if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
  184. mdelay(5);
  185. /* Setting PCFG_PROG_B signal to low */
  186. writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
  187. /*
  188. * Delay is required if AES efuse is selected as
  189. * key source.
  190. */
  191. if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
  192. mdelay(5);
  193. /* Polling the PCAP_INIT status for Reset */
  194. ts = get_timer(0);
  195. while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
  196. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
  197. printf("%s: Timeout wait for INIT to clear\n",
  198. __func__);
  199. return FPGA_FAIL;
  200. }
  201. }
  202. /* Setting PCFG_PROG_B signal to high */
  203. writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
  204. /* Polling the PCAP_INIT status for Set */
  205. ts = get_timer(0);
  206. while (!(readl(&devcfg_base->status) &
  207. DEVCFG_STATUS_PCFG_INIT)) {
  208. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
  209. printf("%s: Timeout wait for INIT to set\n",
  210. __func__);
  211. return FPGA_FAIL;
  212. }
  213. }
  214. }
  215. isr_status = readl(&devcfg_base->int_sts);
  216. /* Clear it all, so if Boot ROM comes back, it can proceed */
  217. writel(0xFFFFFFFF, &devcfg_base->int_sts);
  218. if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
  219. debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);
  220. /* If RX FIFO overflow, need to flush RX FIFO first */
  221. if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
  222. writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
  223. writel(0xFFFFFFFF, &devcfg_base->int_sts);
  224. }
  225. return FPGA_FAIL;
  226. }
  227. status = readl(&devcfg_base->status);
  228. debug("%s: Status = 0x%08X\n", __func__, status);
  229. if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
  230. debug("%s: Error: device busy\n", __func__);
  231. return FPGA_FAIL;
  232. }
  233. debug("%s: Device ready\n", __func__);
  234. if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
  235. if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
  236. /* Error state, transfer cannot occur */
  237. debug("%s: ISR indicates error\n", __func__);
  238. return FPGA_FAIL;
  239. } else {
  240. /* Clear out the status */
  241. writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
  242. }
  243. }
  244. if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
  245. /* Clear the count of completed DMA transfers */
  246. writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
  247. }
  248. return FPGA_SUCCESS;
  249. }
  250. static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap)
  251. {
  252. u32 *new_buf;
  253. u32 i;
  254. if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
  255. new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
  256. /*
  257. * This might be dangerous but permits to flash if
  258. * ARCH_DMA_MINALIGN is greater than header size
  259. */
  260. if (new_buf > buf) {
  261. debug("%s: Aligned buffer is after buffer start\n",
  262. __func__);
  263. new_buf -= ARCH_DMA_MINALIGN;
  264. }
  265. printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
  266. (u32)buf, (u32)new_buf, swap);
  267. for (i = 0; i < (len/4); i++)
  268. new_buf[i] = load_word(&buf[i], swap);
  269. buf = new_buf;
  270. } else if (swap != SWAP_DONE) {
  271. /* For bitstream which are aligned */
  272. u32 *new_buf = (u32 *)buf;
  273. printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
  274. swap);
  275. for (i = 0; i < (len/4); i++)
  276. new_buf[i] = load_word(&buf[i], swap);
  277. }
  278. return buf;
  279. }
  280. static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
  281. size_t bsize, u32 blocksize, u32 *swap,
  282. bitstream_type *bstype)
  283. {
  284. u32 *buf_start;
  285. u32 diff;
  286. buf_start = check_data((u8 *)buf, blocksize, swap);
  287. if (!buf_start)
  288. return FPGA_FAIL;
  289. /* Check if data is postpone from start */
  290. diff = (u32)buf_start - (u32)buf;
  291. if (diff) {
  292. printf("%s: Bitstream is not validated yet (diff %x)\n",
  293. __func__, diff);
  294. return FPGA_FAIL;
  295. }
  296. if ((u32)buf < SZ_1M) {
  297. printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
  298. __func__, (u32)buf);
  299. return FPGA_FAIL;
  300. }
  301. if (zynq_dma_xfer_init(*bstype))
  302. return FPGA_FAIL;
  303. return 0;
  304. }
  305. static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
  306. bitstream_type bstype)
  307. {
  308. unsigned long ts; /* Timestamp */
  309. u32 isr_status, swap;
  310. /*
  311. * send bsize inplace of blocksize as it was not a bitstream
  312. * in chunks
  313. */
  314. if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
  315. &bstype))
  316. return FPGA_FAIL;
  317. buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
  318. debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
  319. debug("%s: Size = %zu\n", __func__, bsize);
  320. /* flush(clean & invalidate) d-cache range buf */
  321. flush_dcache_range((u32)buf, (u32)buf +
  322. roundup(bsize, ARCH_DMA_MINALIGN));
  323. if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
  324. return FPGA_FAIL;
  325. isr_status = readl(&devcfg_base->int_sts);
  326. /* Check FPGA configuration completion */
  327. ts = get_timer(0);
  328. while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
  329. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
  330. printf("%s: Timeout wait for FPGA to config\n",
  331. __func__);
  332. return FPGA_FAIL;
  333. }
  334. isr_status = readl(&devcfg_base->int_sts);
  335. }
  336. debug("%s: FPGA config done\n", __func__);
  337. if (bstype != BIT_PARTIAL)
  338. zynq_slcr_devcfg_enable();
  339. puts("INFO:post config was not run, please run manually if needed\n");
  340. return FPGA_SUCCESS;
  341. }
  342. #if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
  343. static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
  344. fpga_fs_info *fsinfo)
  345. {
  346. unsigned long ts; /* Timestamp */
  347. u32 isr_status, swap;
  348. u32 partialbit = 0;
  349. loff_t blocksize, actread;
  350. loff_t pos = 0;
  351. int fstype;
  352. char *interface, *dev_part;
  353. const char *filename;
  354. blocksize = fsinfo->blocksize;
  355. interface = fsinfo->interface;
  356. dev_part = fsinfo->dev_part;
  357. filename = fsinfo->filename;
  358. fstype = fsinfo->fstype;
  359. if (fs_set_blk_dev(interface, dev_part, fstype))
  360. return FPGA_FAIL;
  361. if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
  362. return FPGA_FAIL;
  363. if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap,
  364. &partialbit))
  365. return FPGA_FAIL;
  366. dcache_disable();
  367. do {
  368. buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
  369. if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2,
  370. 0xffffffff, 0))
  371. return FPGA_FAIL;
  372. bsize -= blocksize;
  373. pos += blocksize;
  374. if (fs_set_blk_dev(interface, dev_part, fstype))
  375. return FPGA_FAIL;
  376. if (bsize > blocksize) {
  377. if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
  378. return FPGA_FAIL;
  379. } else {
  380. if (fs_read(filename, (u32) buf, pos, bsize, &actread) < 0)
  381. return FPGA_FAIL;
  382. }
  383. } while (bsize > blocksize);
  384. buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
  385. if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
  386. return FPGA_FAIL;
  387. dcache_enable();
  388. isr_status = readl(&devcfg_base->int_sts);
  389. /* Check FPGA configuration completion */
  390. ts = get_timer(0);
  391. while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
  392. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
  393. printf("%s: Timeout wait for FPGA to config\n",
  394. __func__);
  395. return FPGA_FAIL;
  396. }
  397. isr_status = readl(&devcfg_base->int_sts);
  398. }
  399. debug("%s: FPGA config done\n", __func__);
  400. if (!partialbit)
  401. zynq_slcr_devcfg_enable();
  402. return FPGA_SUCCESS;
  403. }
  404. #endif
  405. struct xilinx_fpga_op zynq_op = {
  406. .load = zynq_load,
  407. #if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
  408. .loadfs = zynq_loadfs,
  409. #endif
  410. };
  411. #ifdef CONFIG_CMD_ZYNQ_AES
  412. /*
  413. * Load the encrypted image from src addr and decrypt the image and
  414. * place it back the decrypted image into dstaddr.
  415. */
  416. int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen)
  417. {
  418. if (srcaddr < SZ_1M || dstaddr < SZ_1M) {
  419. printf("%s: src and dst addr should be > 1M\n",
  420. __func__);
  421. return FPGA_FAIL;
  422. }
  423. if (zynq_dma_xfer_init(BIT_NONE)) {
  424. printf("%s: zynq_dma_xfer_init FAIL\n", __func__);
  425. return FPGA_FAIL;
  426. }
  427. writel((readl(&devcfg_base->ctrl) | DEVCFG_CTRL_PCAP_RATE_EN_MASK),
  428. &devcfg_base->ctrl);
  429. debug("%s: Source = 0x%08X\n", __func__, (u32)srcaddr);
  430. debug("%s: Size = %zu\n", __func__, srclen);
  431. /* flush(clean & invalidate) d-cache range buf */
  432. flush_dcache_range((u32)srcaddr, (u32)srcaddr +
  433. roundup(srclen << 2, ARCH_DMA_MINALIGN));
  434. /*
  435. * Flush destination address range only if image is not
  436. * bitstream.
  437. */
  438. flush_dcache_range((u32)dstaddr, (u32)dstaddr +
  439. roundup(dstlen << 2, ARCH_DMA_MINALIGN));
  440. if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
  441. return FPGA_FAIL;
  442. writel((readl(&devcfg_base->ctrl) & ~DEVCFG_CTRL_PCAP_RATE_EN_MASK),
  443. &devcfg_base->ctrl);
  444. return FPGA_SUCCESS;
  445. }
  446. #endif