zynqmppl.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2015 - 2016, Xilinx, Inc,
  4. * Michal Simek <michal.simek@xilinx.com>
  5. * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
  6. */
  7. #include <console.h>
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <zynqmppl.h>
  11. #include <zynqmp_firmware.h>
  12. #include <linux/sizes.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <memalign.h>
  15. #define DUMMY_WORD 0xffffffff
  16. /* Xilinx binary format header */
  17. static const u32 bin_format[] = {
  18. DUMMY_WORD, /* Dummy words */
  19. DUMMY_WORD,
  20. DUMMY_WORD,
  21. DUMMY_WORD,
  22. DUMMY_WORD,
  23. DUMMY_WORD,
  24. DUMMY_WORD,
  25. DUMMY_WORD,
  26. DUMMY_WORD,
  27. DUMMY_WORD,
  28. DUMMY_WORD,
  29. DUMMY_WORD,
  30. DUMMY_WORD,
  31. DUMMY_WORD,
  32. DUMMY_WORD,
  33. DUMMY_WORD,
  34. 0x000000bb, /* Sync word */
  35. 0x11220044, /* Sync word */
  36. DUMMY_WORD,
  37. DUMMY_WORD,
  38. 0xaa995566, /* Sync word */
  39. };
  40. #define SWAP_NO 1
  41. #define SWAP_DONE 2
  42. /*
  43. * Load the whole word from unaligned buffer
  44. * Keep in your mind that it is byte loading on little-endian system
  45. */
  46. static u32 load_word(const void *buf, u32 swap)
  47. {
  48. u32 word = 0;
  49. u8 *bitc = (u8 *)buf;
  50. int p;
  51. if (swap == SWAP_NO) {
  52. for (p = 0; p < 4; p++) {
  53. word <<= 8;
  54. word |= bitc[p];
  55. }
  56. } else {
  57. for (p = 3; p >= 0; p--) {
  58. word <<= 8;
  59. word |= bitc[p];
  60. }
  61. }
  62. return word;
  63. }
  64. static u32 check_header(const void *buf)
  65. {
  66. u32 i, pattern;
  67. int swap = SWAP_NO;
  68. u32 *test = (u32 *)buf;
  69. debug("%s: Let's check bitstream header\n", __func__);
  70. /* Checking that passing bin is not a bitstream */
  71. for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
  72. pattern = load_word(&test[i], swap);
  73. /*
  74. * Bitstreams in binary format are swapped
  75. * compare to regular bistream.
  76. * Do not swap dummy word but if swap is done assume
  77. * that parsing buffer is binary format
  78. */
  79. if ((__swab32(pattern) != DUMMY_WORD) &&
  80. (__swab32(pattern) == bin_format[i])) {
  81. swap = SWAP_DONE;
  82. debug("%s: data swapped - let's swap\n", __func__);
  83. }
  84. debug("%s: %d/%px: pattern %x/%x bin_format\n", __func__, i,
  85. &test[i], pattern, bin_format[i]);
  86. }
  87. debug("%s: Found bitstream header at %px %s swapinng\n", __func__,
  88. buf, swap == SWAP_NO ? "without" : "with");
  89. return swap;
  90. }
  91. static void *check_data(u8 *buf, size_t bsize, u32 *swap)
  92. {
  93. u32 word, p = 0; /* possition */
  94. /* Because buf doesn't need to be aligned let's read it by chars */
  95. for (p = 0; p < bsize; p++) {
  96. word = load_word(&buf[p], SWAP_NO);
  97. debug("%s: word %x %x/%px\n", __func__, word, p, &buf[p]);
  98. /* Find the first bitstream dummy word */
  99. if (word == DUMMY_WORD) {
  100. debug("%s: Found dummy word at position %x/%px\n",
  101. __func__, p, &buf[p]);
  102. *swap = check_header(&buf[p]);
  103. if (*swap) {
  104. /* FIXME add full bitstream checking here */
  105. return &buf[p];
  106. }
  107. }
  108. /* Loop can be huge - support CTRL + C */
  109. if (ctrlc())
  110. return NULL;
  111. }
  112. return NULL;
  113. }
  114. static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap)
  115. {
  116. u32 *new_buf;
  117. u32 i;
  118. if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
  119. new_buf = (u32 *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
  120. /*
  121. * This might be dangerous but permits to flash if
  122. * ARCH_DMA_MINALIGN is greater than header size
  123. */
  124. if (new_buf > (u32 *)buf) {
  125. debug("%s: Aligned buffer is after buffer start\n",
  126. __func__);
  127. new_buf -= ARCH_DMA_MINALIGN;
  128. }
  129. printf("%s: Align buffer at %px to %px(swap %d)\n", __func__,
  130. buf, new_buf, swap);
  131. for (i = 0; i < (len/4); i++)
  132. new_buf[i] = load_word(&buf[i], swap);
  133. buf = new_buf;
  134. } else if ((swap != SWAP_DONE) &&
  135. (zynqmp_firmware_version() <= PMUFW_V1_0)) {
  136. /* For bitstream which are aligned */
  137. new_buf = buf;
  138. printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
  139. swap);
  140. for (i = 0; i < (len/4); i++)
  141. new_buf[i] = load_word(&buf[i], swap);
  142. }
  143. return (ulong)buf;
  144. }
  145. static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
  146. size_t bsize, u32 blocksize, u32 *swap)
  147. {
  148. ulong *buf_start;
  149. ulong diff;
  150. buf_start = check_data((u8 *)buf, blocksize, swap);
  151. if (!buf_start)
  152. return FPGA_FAIL;
  153. /* Check if data is postpone from start */
  154. diff = (ulong)buf_start - (ulong)buf;
  155. if (diff) {
  156. printf("%s: Bitstream is not validated yet (diff %lx)\n",
  157. __func__, diff);
  158. return FPGA_FAIL;
  159. }
  160. if ((ulong)buf < SZ_1M) {
  161. printf("%s: Bitstream has to be placed up to 1MB (%px)\n",
  162. __func__, buf);
  163. return FPGA_FAIL;
  164. }
  165. return 0;
  166. }
  167. static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
  168. bitstream_type bstype)
  169. {
  170. ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
  171. u32 swap = 0;
  172. ulong bin_buf;
  173. int ret;
  174. u32 buf_lo, buf_hi;
  175. u32 ret_payload[PAYLOAD_ARG_CNT];
  176. bool xilfpga_old = false;
  177. if (zynqmp_firmware_version() <= PMUFW_V1_0) {
  178. puts("WARN: PMUFW v1.0 or less is detected\n");
  179. puts("WARN: Not all bitstream formats are supported\n");
  180. puts("WARN: Please upgrade PMUFW\n");
  181. xilfpga_old = true;
  182. if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
  183. return FPGA_FAIL;
  184. bsizeptr = (u32 *)&bsize;
  185. flush_dcache_range((ulong)bsizeptr,
  186. (ulong)bsizeptr + sizeof(size_t));
  187. bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
  188. }
  189. bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
  190. debug("%s called!\n", __func__);
  191. flush_dcache_range(bin_buf, bin_buf + bsize);
  192. buf_lo = (u32)bin_buf;
  193. buf_hi = upper_32_bits(bin_buf);
  194. if (xilfpga_old)
  195. ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
  196. buf_hi, (u32)(uintptr_t)bsizeptr,
  197. bstype, ret_payload);
  198. else
  199. ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
  200. buf_hi, (u32)bsize, 0, ret_payload);
  201. if (ret)
  202. puts("PL FPGA LOAD fail\n");
  203. return ret;
  204. }
  205. #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
  206. static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
  207. struct fpga_secure_info *fpga_sec_info)
  208. {
  209. int ret;
  210. u32 buf_lo, buf_hi;
  211. u32 ret_payload[PAYLOAD_ARG_CNT];
  212. u8 flag = 0;
  213. flush_dcache_range((ulong)buf, (ulong)buf +
  214. ALIGN(bsize, CONFIG_SYS_CACHELINE_SIZE));
  215. if (!fpga_sec_info->encflag)
  216. flag |= BIT(ZYNQMP_FPGA_BIT_ENC_DEV_KEY);
  217. if (fpga_sec_info->userkey_addr &&
  218. fpga_sec_info->encflag == FPGA_ENC_USR_KEY) {
  219. flush_dcache_range((ulong)fpga_sec_info->userkey_addr,
  220. (ulong)fpga_sec_info->userkey_addr +
  221. ALIGN(KEY_PTR_LEN,
  222. CONFIG_SYS_CACHELINE_SIZE));
  223. flag |= BIT(ZYNQMP_FPGA_BIT_ENC_USR_KEY);
  224. }
  225. if (!fpga_sec_info->authflag)
  226. flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_OCM);
  227. if (fpga_sec_info->authflag == ZYNQMP_FPGA_AUTH_DDR)
  228. flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_DDR);
  229. buf_lo = lower_32_bits((ulong)buf);
  230. buf_hi = upper_32_bits((ulong)buf);
  231. ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
  232. buf_hi,
  233. (u32)(uintptr_t)fpga_sec_info->userkey_addr,
  234. flag, ret_payload);
  235. if (ret)
  236. puts("PL FPGA LOAD fail\n");
  237. else
  238. puts("Bitstream successfully loaded\n");
  239. return ret;
  240. }
  241. #endif
  242. static int zynqmp_pcap_info(xilinx_desc *desc)
  243. {
  244. int ret;
  245. u32 ret_payload[PAYLOAD_ARG_CNT];
  246. ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0,
  247. 0, ret_payload);
  248. if (!ret)
  249. printf("PCAP status\t0x%x\n", ret_payload[1]);
  250. return ret;
  251. }
  252. struct xilinx_fpga_op zynqmp_op = {
  253. .load = zynqmp_load,
  254. #if defined CONFIG_CMD_FPGA_LOAD_SECURE
  255. .loads = zynqmp_loads,
  256. #endif
  257. .info = zynqmp_pcap_info,
  258. };