stratixv.c 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <altera.h>
  7. #include <spi.h>
  8. #include <asm/io.h>
  9. #include <linux/errno.h>
  10. /* Write the RBF data to FPGA via SPI */
  11. static int program_write(int spi_bus, int spi_dev, const void *rbf_data,
  12. unsigned long rbf_size)
  13. {
  14. struct spi_slave *slave;
  15. int ret;
  16. debug("%s (%d): data=%p size=%ld\n",
  17. __func__, __LINE__, rbf_data, rbf_size);
  18. /* FIXME: How to get the max. SPI clock and SPI mode? */
  19. slave = spi_setup_slave(spi_bus, spi_dev, 27777777, SPI_MODE_3);
  20. if (!slave)
  21. return -1;
  22. if (spi_claim_bus(slave))
  23. return -1;
  24. ret = spi_xfer(slave, rbf_size * 8, rbf_data, (void *)rbf_data,
  25. SPI_XFER_BEGIN | SPI_XFER_END);
  26. spi_release_bus(slave);
  27. return ret;
  28. }
  29. /*
  30. * This is the interface used by FPGA driver.
  31. * Return 0 for sucess, non-zero for error.
  32. */
  33. int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
  34. {
  35. altera_board_specific_func *pfns = desc->iface_fns;
  36. int cookie = desc->cookie;
  37. int spi_bus;
  38. int spi_dev;
  39. int ret = 0;
  40. if ((u32)rbf_data & 0x3) {
  41. puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
  42. return -EINVAL;
  43. }
  44. /* Run the pre configuration function if there is one */
  45. if (pfns->pre)
  46. (pfns->pre)(cookie);
  47. /* Establish the initial state */
  48. if (pfns->config) {
  49. /* De-assert nCONFIG */
  50. (pfns->config)(false, true, cookie);
  51. /* nConfig minimum low pulse width is 2us */
  52. udelay(200);
  53. /* Assert nCONFIG */
  54. (pfns->config)(true, true, cookie);
  55. /* nCONFIG high to first rising clock on DCLK min 1506 us */
  56. udelay(1600);
  57. }
  58. /* Write the RBF data to FPGA */
  59. if (pfns->write) {
  60. /*
  61. * Use board specific data function to write bitstream
  62. * into the FPGA
  63. */
  64. ret = (pfns->write)(rbf_data, rbf_size, true, cookie);
  65. } else {
  66. /*
  67. * Use common SPI functions to write bitstream into the
  68. * FPGA
  69. */
  70. spi_bus = COOKIE2SPI_BUS(cookie);
  71. spi_dev = COOKIE2SPI_DEV(cookie);
  72. ret = program_write(spi_bus, spi_dev, rbf_data, rbf_size);
  73. }
  74. if (ret)
  75. return ret;
  76. /* Check done pin */
  77. if (pfns->done) {
  78. ret = (pfns->done)(cookie);
  79. if (ret)
  80. printf("Error: DONE not set (ret=%d)!\n", ret);
  81. }
  82. return ret;
  83. }