stratixII.c 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Eran Liberty, Extricom , eran.liberty@gmail.com
  5. */
  6. #include <common.h> /* core U-Boot definitions */
  7. #include <altera.h>
  8. int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
  9. int isSerial, int isSecure);
  10. int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize);
  11. /****************************************************************/
  12. /* Stratix II Generic Implementation */
  13. int StratixII_load (Altera_desc * desc, void *buf, size_t bsize)
  14. {
  15. int ret_val = FPGA_FAIL;
  16. switch (desc->iface) {
  17. case passive_serial:
  18. ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 1, 0);
  19. break;
  20. case fast_passive_parallel:
  21. ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 0);
  22. break;
  23. case fast_passive_parallel_security:
  24. ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 1);
  25. break;
  26. /* Add new interface types here */
  27. default:
  28. printf ("%s: Unsupported interface type, %d\n", __FUNCTION__,
  29. desc->iface);
  30. }
  31. return ret_val;
  32. }
  33. int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize)
  34. {
  35. int ret_val = FPGA_FAIL;
  36. switch (desc->iface) {
  37. case passive_serial:
  38. case fast_passive_parallel:
  39. case fast_passive_parallel_security:
  40. ret_val = StratixII_ps_fpp_dump (desc, buf, bsize);
  41. break;
  42. /* Add new interface types here */
  43. default:
  44. printf ("%s: Unsupported interface type, %d\n", __FUNCTION__,
  45. desc->iface);
  46. }
  47. return ret_val;
  48. }
  49. int StratixII_info (Altera_desc * desc)
  50. {
  51. return FPGA_SUCCESS;
  52. }
  53. int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize)
  54. {
  55. printf ("Stratix II Fast Passive Parallel dump is not implemented\n");
  56. return FPGA_FAIL;
  57. }
  58. int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
  59. int isSerial, int isSecure)
  60. {
  61. altera_board_specific_func *fns;
  62. int cookie;
  63. int ret_val = FPGA_FAIL;
  64. int bytecount;
  65. char *buff = buf;
  66. int i;
  67. if (!desc) {
  68. printf ("%s(%d) Altera_desc missing\n", __FUNCTION__, __LINE__);
  69. return FPGA_FAIL;
  70. }
  71. if (!buff) {
  72. printf ("%s(%d) buffer is missing\n", __FUNCTION__, __LINE__);
  73. return FPGA_FAIL;
  74. }
  75. if (!bsize) {
  76. printf ("%s(%d) size is zero\n", __FUNCTION__, __LINE__);
  77. return FPGA_FAIL;
  78. }
  79. if (!desc->iface_fns) {
  80. printf
  81. ("%s(%d) Altera_desc function interface table is missing\n",
  82. __FUNCTION__, __LINE__);
  83. return FPGA_FAIL;
  84. }
  85. fns = (altera_board_specific_func *) (desc->iface_fns);
  86. cookie = desc->cookie;
  87. if (!
  88. (fns->config && fns->status && fns->done && fns->data
  89. && fns->abort)) {
  90. printf
  91. ("%s(%d) Missing some function in the function interface table\n",
  92. __FUNCTION__, __LINE__);
  93. return FPGA_FAIL;
  94. }
  95. /* 1. give board specific a chance to do anything before we start */
  96. if (fns->pre) {
  97. if ((ret_val = fns->pre (cookie)) < 0) {
  98. return ret_val;
  99. }
  100. }
  101. /* from this point on we must fail gracfully by calling lower layer abort */
  102. /* 2. Strat burn cycle by deasserting config for t_CFG and waiting t_CF2CK after reaserted */
  103. fns->config (0, 1, cookie);
  104. udelay (5); /* nCONFIG low pulse width 2usec */
  105. fns->config (1, 1, cookie);
  106. udelay (100); /* nCONFIG high to first rising edge on DCLK */
  107. /* 3. Start the Data cycle with clk deasserted */
  108. bytecount = 0;
  109. fns->clk (0, 1, cookie);
  110. printf ("loading to fpga ");
  111. while (bytecount < bsize) {
  112. /* 3.1 check stratix has not signaled us an error */
  113. if (fns->status (cookie) != 1) {
  114. printf
  115. ("\n%s(%d) Stratix failed (byte transferred till failure 0x%x)\n",
  116. __FUNCTION__, __LINE__, bytecount);
  117. fns->abort (cookie);
  118. return FPGA_FAIL;
  119. }
  120. if (isSerial) {
  121. int i;
  122. uint8_t data = buff[bytecount++];
  123. for (i = 0; i < 8; i++) {
  124. /* 3.2(ps) put data on the bus */
  125. fns->data ((data >> i) & 1, 1, cookie);
  126. /* 3.3(ps) clock once */
  127. fns->clk (1, 1, cookie);
  128. fns->clk (0, 1, cookie);
  129. }
  130. } else {
  131. /* 3.2(fpp) put data on the bus */
  132. fns->data (buff[bytecount++], 1, cookie);
  133. /* 3.3(fpp) clock once */
  134. fns->clk (1, 1, cookie);
  135. fns->clk (0, 1, cookie);
  136. /* 3.4(fpp) for secure cycle push 3 more clocks */
  137. for (i = 0; isSecure && i < 3; i++) {
  138. fns->clk (1, 1, cookie);
  139. fns->clk (0, 1, cookie);
  140. }
  141. }
  142. /* 3.5 while clk is deasserted it is safe to print some progress indication */
  143. if ((bytecount % (bsize / 100)) == 0) {
  144. printf ("\b\b\b%02d\%", bytecount * 100 / bsize);
  145. }
  146. }
  147. /* 4. Set one last clock and check conf done signal */
  148. fns->clk (1, 1, cookie);
  149. udelay (100);
  150. if (!fns->done (cookie)) {
  151. printf (" error!.\n");
  152. fns->abort (cookie);
  153. return FPGA_FAIL;
  154. } else {
  155. printf ("\b\b\b done.\n");
  156. }
  157. /* 5. call lower layer post configuration */
  158. if (fns->post) {
  159. if ((ret_val = fns->post (cookie)) < 0) {
  160. fns->abort (cookie);
  161. return ret_val;
  162. }
  163. }
  164. return FPGA_SUCCESS;
  165. }