stratix10.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Intel Corporation <www.intel.com>
  4. */
  5. #include <common.h>
  6. #include <altera.h>
  7. #include <asm/arch/mailbox_s10.h>
  8. #define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000
  9. #define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000
  10. static const struct mbox_cfgstat_state {
  11. int err_no;
  12. const char *error_name;
  13. } mbox_cfgstat_state[] = {
  14. {MBOX_CFGSTAT_STATE_IDLE, "FPGA in idle mode."},
  15. {MBOX_CFGSTAT_STATE_CONFIG, "FPGA in config mode."},
  16. {MBOX_CFGSTAT_STATE_FAILACK, "Acknowledgment failed!"},
  17. {MBOX_CFGSTAT_STATE_ERROR_INVALID, "Invalid bitstream!"},
  18. {MBOX_CFGSTAT_STATE_ERROR_CORRUPT, "Corrupted bitstream!"},
  19. {MBOX_CFGSTAT_STATE_ERROR_AUTH, "Authentication failed!"},
  20. {MBOX_CFGSTAT_STATE_ERROR_CORE_IO, "I/O error!"},
  21. {MBOX_CFGSTAT_STATE_ERROR_HARDWARE, "Hardware error!"},
  22. {MBOX_CFGSTAT_STATE_ERROR_FAKE, "Fake error!"},
  23. {MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO, "Error in boot info!"},
  24. {MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR, "Error in QSPI!"},
  25. {MBOX_RESP_ERROR, "Mailbox general error!"},
  26. {-ETIMEDOUT, "I/O timeout error"},
  27. {-1, "Unknown error!"}
  28. };
  29. #define MBOX_CFGSTAT_MAX ARRAY_SIZE(mbox_cfgstat_state)
  30. static const char *mbox_cfgstat_to_str(int err)
  31. {
  32. int i;
  33. for (i = 0; i < MBOX_CFGSTAT_MAX - 1; i++) {
  34. if (mbox_cfgstat_state[i].err_no == err)
  35. return mbox_cfgstat_state[i].error_name;
  36. }
  37. return mbox_cfgstat_state[MBOX_CFGSTAT_MAX - 1].error_name;
  38. }
  39. /*
  40. * Add the ongoing transaction's command ID into pending list and return
  41. * the command ID for next transfer.
  42. */
  43. static u8 add_transfer(u32 *xfer_pending_list, size_t list_size, u8 id)
  44. {
  45. int i;
  46. for (i = 0; i < list_size; i++) {
  47. if (xfer_pending_list[i])
  48. continue;
  49. xfer_pending_list[i] = id;
  50. debug("ID(%d) added to transaction pending list\n", id);
  51. /*
  52. * Increment command ID for next transaction.
  53. * Valid command ID (4 bits) is from 1 to 15.
  54. */
  55. id = (id % 15) + 1;
  56. break;
  57. }
  58. return id;
  59. }
  60. /*
  61. * Check whether response ID match the command ID in the transfer
  62. * pending list. If a match is found in the transfer pending list,
  63. * it clears the transfer pending list and return the matched
  64. * command ID.
  65. */
  66. static int get_and_clr_transfer(u32 *xfer_pending_list, size_t list_size,
  67. u8 id)
  68. {
  69. int i;
  70. for (i = 0; i < list_size; i++) {
  71. if (id != xfer_pending_list[i])
  72. continue;
  73. xfer_pending_list[i] = 0;
  74. return id;
  75. }
  76. return 0;
  77. }
  78. /*
  79. * Polling the FPGA configuration status.
  80. * Return 0 for success, non-zero for error.
  81. */
  82. static int reconfig_status_polling_resp(void)
  83. {
  84. int ret;
  85. unsigned long start = get_timer(0);
  86. while (1) {
  87. ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
  88. if (!ret)
  89. return 0; /* configuration success */
  90. if (ret != MBOX_CFGSTAT_STATE_CONFIG)
  91. return ret;
  92. if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
  93. break; /* time out */
  94. puts(".");
  95. udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
  96. }
  97. return -ETIMEDOUT;
  98. }
  99. static u32 get_resp_hdr(u32 *r_index, u32 *w_index, u32 *resp_count,
  100. u32 *resp_buf, u32 buf_size, u32 client_id)
  101. {
  102. u32 buf[MBOX_RESP_BUFFER_SIZE];
  103. u32 mbox_hdr;
  104. u32 resp_len;
  105. u32 hdr_len;
  106. u32 i;
  107. if (*resp_count < buf_size) {
  108. u32 rcv_len_max = buf_size - *resp_count;
  109. if (rcv_len_max > MBOX_RESP_BUFFER_SIZE)
  110. rcv_len_max = MBOX_RESP_BUFFER_SIZE;
  111. resp_len = mbox_rcv_resp(buf, rcv_len_max);
  112. for (i = 0; i < resp_len; i++) {
  113. resp_buf[(*w_index)++] = buf[i];
  114. *w_index %= buf_size;
  115. (*resp_count)++;
  116. }
  117. }
  118. /* No response in buffer */
  119. if (*resp_count == 0)
  120. return 0;
  121. mbox_hdr = resp_buf[*r_index];
  122. hdr_len = MBOX_RESP_LEN_GET(mbox_hdr);
  123. /* Insufficient header length to return a mailbox header */
  124. if ((*resp_count - 1) < hdr_len)
  125. return 0;
  126. *r_index += (hdr_len + 1);
  127. *r_index %= buf_size;
  128. *resp_count -= (hdr_len + 1);
  129. /* Make sure response belongs to us */
  130. if (MBOX_RESP_CLIENT_GET(mbox_hdr) != client_id)
  131. return 0;
  132. return mbox_hdr;
  133. }
  134. /* Send bit stream data to SDM via RECONFIG_DATA mailbox command */
  135. static int send_reconfig_data(const void *rbf_data, size_t rbf_size,
  136. u32 xfer_max, u32 buf_size_max)
  137. {
  138. u32 response_buffer[MBOX_RESP_BUFFER_SIZE];
  139. u32 xfer_pending[MBOX_RESP_BUFFER_SIZE];
  140. u32 resp_rindex = 0;
  141. u32 resp_windex = 0;
  142. u32 resp_count = 0;
  143. u32 xfer_count = 0;
  144. int resp_err = 0;
  145. u8 cmd_id = 1;
  146. u32 args[3];
  147. int ret;
  148. debug("SDM xfer_max = %d\n", xfer_max);
  149. debug("SDM buf_size_max = %x\n\n", buf_size_max);
  150. memset(xfer_pending, 0, sizeof(xfer_pending));
  151. while (rbf_size || xfer_count) {
  152. if (!resp_err && rbf_size && xfer_count < xfer_max) {
  153. args[0] = MBOX_ARG_DESC_COUNT(1);
  154. args[1] = (u64)rbf_data;
  155. if (rbf_size >= buf_size_max) {
  156. args[2] = buf_size_max;
  157. rbf_size -= buf_size_max;
  158. rbf_data += buf_size_max;
  159. } else {
  160. args[2] = (u64)rbf_size;
  161. rbf_size = 0;
  162. }
  163. resp_err = mbox_send_cmd_only(cmd_id, MBOX_RECONFIG_DATA,
  164. MBOX_CMD_INDIRECT, 3, args);
  165. if (!resp_err) {
  166. xfer_count++;
  167. cmd_id = add_transfer(xfer_pending,
  168. MBOX_RESP_BUFFER_SIZE,
  169. cmd_id);
  170. }
  171. puts(".");
  172. } else {
  173. u32 resp_hdr = get_resp_hdr(&resp_rindex, &resp_windex,
  174. &resp_count,
  175. response_buffer,
  176. MBOX_RESP_BUFFER_SIZE,
  177. MBOX_CLIENT_ID_UBOOT);
  178. /*
  179. * If no valid response header found or
  180. * non-zero length from RECONFIG_DATA
  181. */
  182. if (!resp_hdr || MBOX_RESP_LEN_GET(resp_hdr))
  183. continue;
  184. /* Check for response's status */
  185. if (!resp_err) {
  186. resp_err = MBOX_RESP_ERR_GET(resp_hdr);
  187. debug("Response error code: %08x\n", resp_err);
  188. }
  189. ret = get_and_clr_transfer(xfer_pending,
  190. MBOX_RESP_BUFFER_SIZE,
  191. MBOX_RESP_ID_GET(resp_hdr));
  192. if (ret) {
  193. /* Claim and reuse the ID */
  194. cmd_id = (u8)ret;
  195. xfer_count--;
  196. }
  197. if (resp_err && !xfer_count)
  198. return resp_err;
  199. }
  200. }
  201. return 0;
  202. }
  203. /*
  204. * This is the interface used by FPGA driver.
  205. * Return 0 for success, non-zero for error.
  206. */
  207. int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
  208. {
  209. int ret;
  210. u32 resp_len = 2;
  211. u32 resp_buf[2];
  212. debug("Sending MBOX_RECONFIG...\n");
  213. ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, 0,
  214. NULL, 0, &resp_len, resp_buf);
  215. if (ret) {
  216. puts("Failure in RECONFIG mailbox command!\n");
  217. return ret;
  218. }
  219. ret = send_reconfig_data(rbf_data, rbf_size, resp_buf[0], resp_buf[1]);
  220. if (ret) {
  221. printf("RECONFIG_DATA error: %08x, %s\n", ret,
  222. mbox_cfgstat_to_str(ret));
  223. return ret;
  224. }
  225. /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
  226. udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
  227. debug("Polling with MBOX_RECONFIG_STATUS...\n");
  228. ret = reconfig_status_polling_resp();
  229. if (ret) {
  230. printf("RECONFIG_STATUS Error: %08x, %s\n", ret,
  231. mbox_cfgstat_to_str(ret));
  232. return ret;
  233. }
  234. puts("FPGA reconfiguration OK!\n");
  235. return ret;
  236. }