altera.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2003
  4. * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
  5. *
  6. * (C) Copyright 2002
  7. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  8. */
  9. /*
  10. * Altera FPGA support
  11. */
  12. #include <common.h>
  13. #include <errno.h>
  14. #include <ACEX1K.h>
  15. #include <stratixII.h>
  16. /* Define FPGA_DEBUG to 1 to get debug printf's */
  17. #define FPGA_DEBUG 0
  18. static const struct altera_fpga {
  19. enum altera_family family;
  20. const char *name;
  21. int (*load)(Altera_desc *, const void *, size_t);
  22. int (*dump)(Altera_desc *, const void *, size_t);
  23. int (*info)(Altera_desc *);
  24. } altera_fpga[] = {
  25. #if defined(CONFIG_FPGA_ACEX1K)
  26. { Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
  27. { Altera_CYC2, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
  28. #elif defined(CONFIG_FPGA_CYCLON2)
  29. { Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
  30. { Altera_CYC2, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
  31. #endif
  32. #if defined(CONFIG_FPGA_STRATIX_II)
  33. { Altera_StratixII, "StratixII", StratixII_load,
  34. StratixII_dump, StratixII_info },
  35. #endif
  36. #if defined(CONFIG_FPGA_STRATIX_V)
  37. { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
  38. #endif
  39. #if defined(CONFIG_FPGA_STRATIX10)
  40. { Intel_FPGA_Stratix10, "Stratix10", stratix10_load, NULL, NULL },
  41. #endif
  42. #if defined(CONFIG_FPGA_SOCFPGA)
  43. { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
  44. #endif
  45. };
  46. static int altera_validate(Altera_desc *desc, const char *fn)
  47. {
  48. if (!desc) {
  49. printf("%s: NULL descriptor!\n", fn);
  50. return -EINVAL;
  51. }
  52. if ((desc->family < min_altera_type) ||
  53. (desc->family > max_altera_type)) {
  54. printf("%s: Invalid family type, %d\n", fn, desc->family);
  55. return -EINVAL;
  56. }
  57. if ((desc->iface < min_altera_iface_type) ||
  58. (desc->iface > max_altera_iface_type)) {
  59. printf("%s: Invalid Interface type, %d\n", fn, desc->iface);
  60. return -EINVAL;
  61. }
  62. if (!desc->size) {
  63. printf("%s: NULL part size\n", fn);
  64. return -EINVAL;
  65. }
  66. return 0;
  67. }
  68. static const struct altera_fpga *
  69. altera_desc_to_fpga(Altera_desc *desc, const char *fn)
  70. {
  71. int i;
  72. if (altera_validate(desc, fn)) {
  73. printf("%s: Invalid device descriptor\n", fn);
  74. return NULL;
  75. }
  76. for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) {
  77. if (desc->family == altera_fpga[i].family)
  78. break;
  79. }
  80. if (i == ARRAY_SIZE(altera_fpga)) {
  81. printf("%s: Unsupported family type, %d\n", fn, desc->family);
  82. return NULL;
  83. }
  84. return &altera_fpga[i];
  85. }
  86. int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
  87. {
  88. const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
  89. if (!fpga)
  90. return FPGA_FAIL;
  91. debug_cond(FPGA_DEBUG, "%s: Launching the %s Loader...\n",
  92. __func__, fpga->name);
  93. if (fpga->load)
  94. return fpga->load(desc, buf, bsize);
  95. return 0;
  96. }
  97. int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
  98. {
  99. const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
  100. if (!fpga)
  101. return FPGA_FAIL;
  102. debug_cond(FPGA_DEBUG, "%s: Launching the %s Reader...\n",
  103. __func__, fpga->name);
  104. if (fpga->dump)
  105. return fpga->dump(desc, buf, bsize);
  106. return 0;
  107. }
  108. int altera_info(Altera_desc *desc)
  109. {
  110. const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
  111. if (!fpga)
  112. return FPGA_FAIL;
  113. printf("Family: \t%s\n", fpga->name);
  114. printf("Interface type:\t");
  115. switch (desc->iface) {
  116. case passive_serial:
  117. printf("Passive Serial (PS)\n");
  118. break;
  119. case passive_parallel_synchronous:
  120. printf("Passive Parallel Synchronous (PPS)\n");
  121. break;
  122. case passive_parallel_asynchronous:
  123. printf("Passive Parallel Asynchronous (PPA)\n");
  124. break;
  125. case passive_serial_asynchronous:
  126. printf("Passive Serial Asynchronous (PSA)\n");
  127. break;
  128. case altera_jtag_mode: /* Not used */
  129. printf("JTAG Mode\n");
  130. break;
  131. case fast_passive_parallel:
  132. printf("Fast Passive Parallel (FPP)\n");
  133. break;
  134. case fast_passive_parallel_security:
  135. printf("Fast Passive Parallel with Security (FPPS)\n");
  136. break;
  137. case secure_device_manager_mailbox:
  138. puts("Secure Device Manager (SDM) Mailbox\n");
  139. break;
  140. /* Add new interface types here */
  141. default:
  142. printf("Unsupported interface type, %d\n", desc->iface);
  143. }
  144. printf("Device Size: \t%zd bytes\n"
  145. "Cookie: \t0x%x (%d)\n",
  146. desc->size, desc->cookie, desc->cookie);
  147. if (desc->iface_fns) {
  148. printf("Device Function Table @ 0x%p\n", desc->iface_fns);
  149. if (fpga->info)
  150. fpga->info(desc);
  151. } else {
  152. printf("No Device Function Table.\n");
  153. }
  154. return FPGA_SUCCESS;
  155. }