ACEX1K.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2003
  4. * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
  5. *
  6. * (C) Copyright 2002
  7. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  8. */
  9. #include <common.h> /* core U-Boot definitions */
  10. #include <console.h>
  11. #include <ACEX1K.h> /* ACEX device family */
  12. /* Define FPGA_DEBUG to get debug printf's */
  13. #ifdef FPGA_DEBUG
  14. #define PRINTF(fmt,args...) printf (fmt ,##args)
  15. #else
  16. #define PRINTF(fmt,args...)
  17. #endif
  18. /* Note: The assumption is that we cannot possibly run fast enough to
  19. * overrun the device (the Slave Parallel mode can free run at 50MHz).
  20. * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
  21. * the board config file to slow things down.
  22. */
  23. #ifndef CONFIG_FPGA_DELAY
  24. #define CONFIG_FPGA_DELAY()
  25. #endif
  26. #ifndef CONFIG_SYS_FPGA_WAIT
  27. #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */
  28. #endif
  29. static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize);
  30. static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize);
  31. /* static int ACEX1K_ps_info(Altera_desc *desc); */
  32. /* ------------------------------------------------------------------------- */
  33. /* ACEX1K Generic Implementation */
  34. int ACEX1K_load(Altera_desc *desc, const void *buf, size_t bsize)
  35. {
  36. int ret_val = FPGA_FAIL;
  37. switch (desc->iface) {
  38. case passive_serial:
  39. PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__);
  40. ret_val = ACEX1K_ps_load (desc, buf, bsize);
  41. break;
  42. /* Add new interface types here */
  43. default:
  44. printf ("%s: Unsupported interface type, %d\n",
  45. __FUNCTION__, desc->iface);
  46. }
  47. return ret_val;
  48. }
  49. int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize)
  50. {
  51. int ret_val = FPGA_FAIL;
  52. switch (desc->iface) {
  53. case passive_serial:
  54. PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__);
  55. ret_val = ACEX1K_ps_dump (desc, buf, bsize);
  56. break;
  57. /* Add new interface types here */
  58. default:
  59. printf ("%s: Unsupported interface type, %d\n",
  60. __FUNCTION__, desc->iface);
  61. }
  62. return ret_val;
  63. }
  64. int ACEX1K_info( Altera_desc *desc )
  65. {
  66. return FPGA_SUCCESS;
  67. }
  68. /* ------------------------------------------------------------------------- */
  69. /* ACEX1K Passive Serial Generic Implementation */
  70. static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
  71. {
  72. int ret_val = FPGA_FAIL; /* assume the worst */
  73. Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns;
  74. int i;
  75. PRINTF ("%s: start with interface functions @ 0x%p\n",
  76. __FUNCTION__, fn);
  77. if (fn) {
  78. size_t bytecount = 0;
  79. unsigned char *data = (unsigned char *) buf;
  80. int cookie = desc->cookie; /* make a local copy */
  81. unsigned long ts; /* timestamp */
  82. PRINTF ("%s: Function Table:\n"
  83. "ptr:\t0x%p\n"
  84. "struct: 0x%p\n"
  85. "config:\t0x%p\n"
  86. "status:\t0x%p\n"
  87. "clk:\t0x%p\n"
  88. "data:\t0x%p\n"
  89. "done:\t0x%p\n\n",
  90. __FUNCTION__, &fn, fn, fn->config, fn->status,
  91. fn->clk, fn->data, fn->done);
  92. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  93. printf ("Loading FPGA Device %d...", cookie);
  94. #endif
  95. /*
  96. * Run the pre configuration function if there is one.
  97. */
  98. if (*fn->pre) {
  99. (*fn->pre) (cookie);
  100. }
  101. /* Establish the initial state */
  102. (*fn->config) (true, true, cookie); /* Assert nCONFIG */
  103. udelay(2); /* T_cfg > 2us */
  104. /* nSTATUS should be asserted now */
  105. (*fn->done) (cookie);
  106. if ( !(*fn->status) (cookie) ) {
  107. puts ("** nSTATUS is not asserted.\n");
  108. (*fn->abort) (cookie);
  109. return FPGA_FAIL;
  110. }
  111. (*fn->config) (false, true, cookie); /* Deassert nCONFIG */
  112. udelay(2); /* T_cf2st1 < 4us */
  113. /* Wait for nSTATUS to be released (i.e. deasserted) */
  114. ts = get_timer (0); /* get current time */
  115. do {
  116. CONFIG_FPGA_DELAY ();
  117. if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
  118. puts ("** Timeout waiting for STATUS to go high.\n");
  119. (*fn->abort) (cookie);
  120. return FPGA_FAIL;
  121. }
  122. (*fn->done) (cookie);
  123. } while ((*fn->status) (cookie));
  124. /* Get ready for the burn */
  125. CONFIG_FPGA_DELAY ();
  126. /* Load the data */
  127. while (bytecount < bsize) {
  128. unsigned char val=0;
  129. #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
  130. if (ctrlc ()) {
  131. (*fn->abort) (cookie);
  132. return FPGA_FAIL;
  133. }
  134. #endif
  135. /* Altera detects an error if INIT goes low (active)
  136. while DONE is low (inactive) */
  137. #if 0 /* not yet implemented */
  138. if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
  139. puts ("** CRC error during FPGA load.\n");
  140. (*fn->abort) (cookie);
  141. return (FPGA_FAIL);
  142. }
  143. #endif
  144. val = data [bytecount ++ ];
  145. i = 8;
  146. do {
  147. /* Deassert the clock */
  148. (*fn->clk) (false, true, cookie);
  149. CONFIG_FPGA_DELAY ();
  150. /* Write data */
  151. (*fn->data) ((val & 0x01), true, cookie);
  152. CONFIG_FPGA_DELAY ();
  153. /* Assert the clock */
  154. (*fn->clk) (true, true, cookie);
  155. CONFIG_FPGA_DELAY ();
  156. val >>= 1;
  157. i --;
  158. } while (i > 0);
  159. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  160. if (bytecount % (bsize / 40) == 0)
  161. putc ('.'); /* let them know we are alive */
  162. #endif
  163. }
  164. CONFIG_FPGA_DELAY ();
  165. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  166. putc (' '); /* terminate the dotted line */
  167. #endif
  168. /*
  169. * Checking FPGA's CONF_DONE signal - correctly booted ?
  170. */
  171. if ( ! (*fn->done) (cookie) ) {
  172. puts ("** Booting failed! CONF_DONE is still deasserted.\n");
  173. (*fn->abort) (cookie);
  174. return (FPGA_FAIL);
  175. }
  176. /*
  177. * "DCLK must be clocked an additional 10 times fpr ACEX 1K..."
  178. */
  179. for (i = 0; i < 12; i++) {
  180. CONFIG_FPGA_DELAY ();
  181. (*fn->clk) (true, true, cookie); /* Assert the clock pin */
  182. CONFIG_FPGA_DELAY ();
  183. (*fn->clk) (false, true, cookie); /* Deassert the clock pin */
  184. }
  185. ret_val = FPGA_SUCCESS;
  186. #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
  187. if (ret_val == FPGA_SUCCESS) {
  188. puts ("Done.\n");
  189. }
  190. else {
  191. puts ("Fail.\n");
  192. }
  193. #endif
  194. (*fn->post) (cookie);
  195. } else {
  196. printf ("%s: NULL Interface function table!\n", __FUNCTION__);
  197. }
  198. return ret_val;
  199. }
  200. static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize)
  201. {
  202. /* Readback is only available through the Slave Parallel and */
  203. /* boundary-scan interfaces. */
  204. printf ("%s: Passive Serial Dumping is unavailable\n",
  205. __FUNCTION__);
  206. return FPGA_FAIL;
  207. }