ace_sha.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Advanced Crypto Engine - SHA Firmware
  4. * Copyright (c) 2012 Samsung Electronics
  5. */
  6. #include <common.h>
  7. #include "ace_sha.h"
  8. #ifdef CONFIG_SHA_HW_ACCEL
  9. #include <u-boot/sha256.h>
  10. #include <u-boot/sha1.h>
  11. #include <linux/errno.h>
  12. /* SHA1 value for the message of zero length */
  13. static const unsigned char sha1_digest_emptymsg[SHA1_SUM_LEN] = {
  14. 0xDA, 0x39, 0xA3, 0xEE, 0x5E, 0x6B, 0x4B, 0x0D,
  15. 0x32, 0x55, 0xBF, 0xFF, 0x95, 0x60, 0x18, 0x90,
  16. 0xAF, 0xD8, 0x07, 0x09};
  17. /* SHA256 value for the message of zero length */
  18. static const unsigned char sha256_digest_emptymsg[SHA256_SUM_LEN] = {
  19. 0xE3, 0xB0, 0xC4, 0x42, 0x98, 0xFC, 0x1C, 0x14,
  20. 0x9A, 0xFB, 0xF4, 0xC8, 0x99, 0x6F, 0xB9, 0x24,
  21. 0x27, 0xAE, 0x41, 0xE4, 0x64, 0x9B, 0x93, 0x4C,
  22. 0xA4, 0x95, 0x99, 0x1B, 0x78, 0x52, 0xB8, 0x55};
  23. int ace_sha_hash_digest(const unsigned char *pbuf, unsigned int buf_len,
  24. unsigned char *pout, unsigned int hash_type)
  25. {
  26. unsigned int i, reg, len;
  27. unsigned int *pdigest;
  28. struct exynos_ace_sfr *ace_sha_reg =
  29. (struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
  30. if (buf_len == 0) {
  31. /* ACE H/W cannot compute hash value for empty string */
  32. if (hash_type == ACE_SHA_TYPE_SHA1)
  33. memcpy(pout, sha1_digest_emptymsg, SHA1_SUM_LEN);
  34. else
  35. memcpy(pout, sha256_digest_emptymsg, SHA256_SUM_LEN);
  36. return 0;
  37. }
  38. /* Flush HRDMA */
  39. writel(ACE_FC_HRDMACFLUSH_ON, &ace_sha_reg->fc_hrdmac);
  40. writel(ACE_FC_HRDMACFLUSH_OFF, &ace_sha_reg->fc_hrdmac);
  41. /* Set byte swap of data in */
  42. writel(ACE_HASH_SWAPDI_ON | ACE_HASH_SWAPDO_ON | ACE_HASH_SWAPIV_ON,
  43. &ace_sha_reg->hash_byteswap);
  44. /* Select Hash input mux as external source */
  45. reg = readl(&ace_sha_reg->fc_fifoctrl);
  46. reg = (reg & ~ACE_FC_SELHASH_MASK) | ACE_FC_SELHASH_EXOUT;
  47. writel(reg, &ace_sha_reg->fc_fifoctrl);
  48. /* Set Hash as SHA1 or SHA256 and start Hash engine */
  49. reg = (hash_type == ACE_SHA_TYPE_SHA1) ?
  50. ACE_HASH_ENGSEL_SHA1HASH : ACE_HASH_ENGSEL_SHA256HASH;
  51. reg |= ACE_HASH_STARTBIT_ON;
  52. writel(reg, &ace_sha_reg->hash_control);
  53. /* Enable FIFO mode */
  54. writel(ACE_HASH_FIFO_ON, &ace_sha_reg->hash_fifo_mode);
  55. /* Set message length */
  56. writel(buf_len, &ace_sha_reg->hash_msgsize_low);
  57. writel(0, &ace_sha_reg->hash_msgsize_high);
  58. /* Set HRDMA */
  59. writel((unsigned int)pbuf, &ace_sha_reg->fc_hrdmas);
  60. writel(buf_len, &ace_sha_reg->fc_hrdmal);
  61. while ((readl(&ace_sha_reg->hash_status) & ACE_HASH_MSGDONE_MASK) ==
  62. ACE_HASH_MSGDONE_OFF) {
  63. /*
  64. * PRNG error bit goes HIGH if a PRNG request occurs without
  65. * a complete seed setup. We are using this bit to check h/w
  66. * fault because proper setup is not expected in that case.
  67. */
  68. if ((readl(&ace_sha_reg->hash_status)
  69. & ACE_HASH_PRNGERROR_MASK) == ACE_HASH_PRNGERROR_ON)
  70. return -EBUSY;
  71. }
  72. /* Clear MSG_DONE bit */
  73. writel(ACE_HASH_MSGDONE_ON, &ace_sha_reg->hash_status);
  74. /* Read hash result */
  75. pdigest = (unsigned int *)pout;
  76. len = (hash_type == ACE_SHA_TYPE_SHA1) ? SHA1_SUM_LEN : SHA256_SUM_LEN;
  77. for (i = 0; i < len / 4; i++)
  78. pdigest[i] = readl(&ace_sha_reg->hash_result[i]);
  79. /* Clear HRDMA pending bit */
  80. writel(ACE_FC_HRDMA, &ace_sha_reg->fc_intpend);
  81. return 0;
  82. }
  83. void hw_sha256(const unsigned char *pbuf, unsigned int buf_len,
  84. unsigned char *pout, unsigned int chunk_size)
  85. {
  86. if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA256))
  87. debug("ACE was not setup properly or it is faulty\n");
  88. }
  89. void hw_sha1(const unsigned char *pbuf, unsigned int buf_len,
  90. unsigned char *pout, unsigned int chunk_size)
  91. {
  92. if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA1))
  93. debug("ACE was not setup properly or it is faulty\n");
  94. }
  95. #endif /* CONFIG_SHA_HW_ACCEL */
  96. #ifdef CONFIG_LIB_HW_RAND
  97. static unsigned int seed_done;
  98. void srand(unsigned int seed)
  99. {
  100. struct exynos_ace_sfr *reg =
  101. (struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
  102. int i, status;
  103. /* Seed data */
  104. for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++)
  105. writel(seed << i, &reg->hash_seed[i]);
  106. /* Wait for seed setup done */
  107. while (1) {
  108. status = readl(&reg->hash_status);
  109. if ((status & ACE_HASH_SEEDSETTING_MASK) ||
  110. (status & ACE_HASH_PRNGERROR_MASK))
  111. break;
  112. }
  113. seed_done = 1;
  114. }
  115. unsigned int rand(void)
  116. {
  117. struct exynos_ace_sfr *reg =
  118. (struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
  119. int i, status;
  120. unsigned int seed = (unsigned int)&status;
  121. unsigned int ret = 0;
  122. if (!seed_done)
  123. srand(seed);
  124. /* Start PRNG */
  125. writel(ACE_HASH_ENGSEL_PRNG | ACE_HASH_STARTBIT_ON, &reg->hash_control);
  126. /* Wait for PRNG done */
  127. while (1) {
  128. status = readl(&reg->hash_status);
  129. if (status & ACE_HASH_PRNGDONE_MASK)
  130. break;
  131. if (status & ACE_HASH_PRNGERROR_MASK) {
  132. seed_done = 0;
  133. return 0;
  134. }
  135. }
  136. /* Clear Done IRQ */
  137. writel(ACE_HASH_PRNGDONE_MASK, &reg->hash_status);
  138. /* Read a PRNG result */
  139. for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++)
  140. ret += readl(&reg->hash_prng[i]);
  141. seed_done = 0;
  142. return ret;
  143. }
  144. unsigned int rand_r(unsigned int *seedp)
  145. {
  146. srand(*seedp);
  147. return rand();
  148. }
  149. #endif /* CONFIG_LIB_HW_RAND */