clk_stm32mp1.c 53 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <clk-uclass.h>
  7. #include <div64.h>
  8. #include <dm.h>
  9. #include <regmap.h>
  10. #include <spl.h>
  11. #include <syscon.h>
  12. #include <time.h>
  13. #include <vsprintf.h>
  14. #include <linux/io.h>
  15. #include <linux/iopoll.h>
  16. #include <dt-bindings/clock/stm32mp1-clks.h>
  17. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #ifndef CONFIG_TFABOOT
  20. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  21. /* activate clock tree initialization in the driver */
  22. #define STM32MP1_CLOCK_TREE_INIT
  23. #endif
  24. #endif
  25. #define MAX_HSI_HZ 64000000
  26. /* TIMEOUT */
  27. #define TIMEOUT_200MS 200000
  28. #define TIMEOUT_1S 1000000
  29. /* STGEN registers */
  30. #define STGENC_CNTCR 0x00
  31. #define STGENC_CNTSR 0x04
  32. #define STGENC_CNTCVL 0x08
  33. #define STGENC_CNTCVU 0x0C
  34. #define STGENC_CNTFID0 0x20
  35. #define STGENC_CNTCR_EN BIT(0)
  36. /* RCC registers */
  37. #define RCC_OCENSETR 0x0C
  38. #define RCC_OCENCLRR 0x10
  39. #define RCC_HSICFGR 0x18
  40. #define RCC_MPCKSELR 0x20
  41. #define RCC_ASSCKSELR 0x24
  42. #define RCC_RCK12SELR 0x28
  43. #define RCC_MPCKDIVR 0x2C
  44. #define RCC_AXIDIVR 0x30
  45. #define RCC_APB4DIVR 0x3C
  46. #define RCC_APB5DIVR 0x40
  47. #define RCC_RTCDIVR 0x44
  48. #define RCC_MSSCKSELR 0x48
  49. #define RCC_PLL1CR 0x80
  50. #define RCC_PLL1CFGR1 0x84
  51. #define RCC_PLL1CFGR2 0x88
  52. #define RCC_PLL1FRACR 0x8C
  53. #define RCC_PLL1CSGR 0x90
  54. #define RCC_PLL2CR 0x94
  55. #define RCC_PLL2CFGR1 0x98
  56. #define RCC_PLL2CFGR2 0x9C
  57. #define RCC_PLL2FRACR 0xA0
  58. #define RCC_PLL2CSGR 0xA4
  59. #define RCC_I2C46CKSELR 0xC0
  60. #define RCC_CPERCKSELR 0xD0
  61. #define RCC_STGENCKSELR 0xD4
  62. #define RCC_DDRITFCR 0xD8
  63. #define RCC_BDCR 0x140
  64. #define RCC_RDLSICR 0x144
  65. #define RCC_MP_APB4ENSETR 0x200
  66. #define RCC_MP_APB5ENSETR 0x208
  67. #define RCC_MP_AHB5ENSETR 0x210
  68. #define RCC_MP_AHB6ENSETR 0x218
  69. #define RCC_OCRDYR 0x808
  70. #define RCC_DBGCFGR 0x80C
  71. #define RCC_RCK3SELR 0x820
  72. #define RCC_RCK4SELR 0x824
  73. #define RCC_MCUDIVR 0x830
  74. #define RCC_APB1DIVR 0x834
  75. #define RCC_APB2DIVR 0x838
  76. #define RCC_APB3DIVR 0x83C
  77. #define RCC_PLL3CR 0x880
  78. #define RCC_PLL3CFGR1 0x884
  79. #define RCC_PLL3CFGR2 0x888
  80. #define RCC_PLL3FRACR 0x88C
  81. #define RCC_PLL3CSGR 0x890
  82. #define RCC_PLL4CR 0x894
  83. #define RCC_PLL4CFGR1 0x898
  84. #define RCC_PLL4CFGR2 0x89C
  85. #define RCC_PLL4FRACR 0x8A0
  86. #define RCC_PLL4CSGR 0x8A4
  87. #define RCC_I2C12CKSELR 0x8C0
  88. #define RCC_I2C35CKSELR 0x8C4
  89. #define RCC_SPI2S1CKSELR 0x8D8
  90. #define RCC_SPI45CKSELR 0x8E0
  91. #define RCC_UART6CKSELR 0x8E4
  92. #define RCC_UART24CKSELR 0x8E8
  93. #define RCC_UART35CKSELR 0x8EC
  94. #define RCC_UART78CKSELR 0x8F0
  95. #define RCC_SDMMC12CKSELR 0x8F4
  96. #define RCC_SDMMC3CKSELR 0x8F8
  97. #define RCC_ETHCKSELR 0x8FC
  98. #define RCC_QSPICKSELR 0x900
  99. #define RCC_FMCCKSELR 0x904
  100. #define RCC_USBCKSELR 0x91C
  101. #define RCC_DSICKSELR 0x924
  102. #define RCC_ADCCKSELR 0x928
  103. #define RCC_MP_APB1ENSETR 0xA00
  104. #define RCC_MP_APB2ENSETR 0XA08
  105. #define RCC_MP_APB3ENSETR 0xA10
  106. #define RCC_MP_AHB2ENSETR 0xA18
  107. #define RCC_MP_AHB3ENSETR 0xA20
  108. #define RCC_MP_AHB4ENSETR 0xA28
  109. /* used for most of SELR register */
  110. #define RCC_SELR_SRC_MASK GENMASK(2, 0)
  111. #define RCC_SELR_SRCRDY BIT(31)
  112. /* Values of RCC_MPCKSELR register */
  113. #define RCC_MPCKSELR_HSI 0
  114. #define RCC_MPCKSELR_HSE 1
  115. #define RCC_MPCKSELR_PLL 2
  116. #define RCC_MPCKSELR_PLL_MPUDIV 3
  117. /* Values of RCC_ASSCKSELR register */
  118. #define RCC_ASSCKSELR_HSI 0
  119. #define RCC_ASSCKSELR_HSE 1
  120. #define RCC_ASSCKSELR_PLL 2
  121. /* Values of RCC_MSSCKSELR register */
  122. #define RCC_MSSCKSELR_HSI 0
  123. #define RCC_MSSCKSELR_HSE 1
  124. #define RCC_MSSCKSELR_CSI 2
  125. #define RCC_MSSCKSELR_PLL 3
  126. /* Values of RCC_CPERCKSELR register */
  127. #define RCC_CPERCKSELR_HSI 0
  128. #define RCC_CPERCKSELR_CSI 1
  129. #define RCC_CPERCKSELR_HSE 2
  130. /* used for most of DIVR register : max div for RTC */
  131. #define RCC_DIVR_DIV_MASK GENMASK(5, 0)
  132. #define RCC_DIVR_DIVRDY BIT(31)
  133. /* Masks for specific DIVR registers */
  134. #define RCC_APBXDIV_MASK GENMASK(2, 0)
  135. #define RCC_MPUDIV_MASK GENMASK(2, 0)
  136. #define RCC_AXIDIV_MASK GENMASK(2, 0)
  137. #define RCC_MCUDIV_MASK GENMASK(3, 0)
  138. /* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
  139. #define RCC_MP_ENCLRR_OFFSET 4
  140. /* Fields of RCC_BDCR register */
  141. #define RCC_BDCR_LSEON BIT(0)
  142. #define RCC_BDCR_LSEBYP BIT(1)
  143. #define RCC_BDCR_LSERDY BIT(2)
  144. #define RCC_BDCR_DIGBYP BIT(3)
  145. #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
  146. #define RCC_BDCR_LSEDRV_SHIFT 4
  147. #define RCC_BDCR_LSECSSON BIT(8)
  148. #define RCC_BDCR_RTCCKEN BIT(20)
  149. #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
  150. #define RCC_BDCR_RTCSRC_SHIFT 16
  151. /* Fields of RCC_RDLSICR register */
  152. #define RCC_RDLSICR_LSION BIT(0)
  153. #define RCC_RDLSICR_LSIRDY BIT(1)
  154. /* used for ALL PLLNCR registers */
  155. #define RCC_PLLNCR_PLLON BIT(0)
  156. #define RCC_PLLNCR_PLLRDY BIT(1)
  157. #define RCC_PLLNCR_SSCG_CTRL BIT(2)
  158. #define RCC_PLLNCR_DIVPEN BIT(4)
  159. #define RCC_PLLNCR_DIVQEN BIT(5)
  160. #define RCC_PLLNCR_DIVREN BIT(6)
  161. #define RCC_PLLNCR_DIVEN_SHIFT 4
  162. /* used for ALL PLLNCFGR1 registers */
  163. #define RCC_PLLNCFGR1_DIVM_SHIFT 16
  164. #define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
  165. #define RCC_PLLNCFGR1_DIVN_SHIFT 0
  166. #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
  167. /* only for PLL3 and PLL4 */
  168. #define RCC_PLLNCFGR1_IFRGE_SHIFT 24
  169. #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
  170. /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
  171. #define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8)
  172. #define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
  173. #define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P)
  174. #define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
  175. #define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q)
  176. #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
  177. #define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R)
  178. #define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
  179. /* used for ALL PLLNFRACR registers */
  180. #define RCC_PLLNFRACR_FRACV_SHIFT 3
  181. #define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
  182. #define RCC_PLLNFRACR_FRACLE BIT(16)
  183. /* used for ALL PLLNCSGR registers */
  184. #define RCC_PLLNCSGR_INC_STEP_SHIFT 16
  185. #define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
  186. #define RCC_PLLNCSGR_MOD_PER_SHIFT 0
  187. #define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
  188. #define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
  189. #define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
  190. /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
  191. #define RCC_OCENR_HSION BIT(0)
  192. #define RCC_OCENR_CSION BIT(4)
  193. #define RCC_OCENR_DIGBYP BIT(7)
  194. #define RCC_OCENR_HSEON BIT(8)
  195. #define RCC_OCENR_HSEBYP BIT(10)
  196. #define RCC_OCENR_HSECSSON BIT(11)
  197. /* Fields of RCC_OCRDYR register */
  198. #define RCC_OCRDYR_HSIRDY BIT(0)
  199. #define RCC_OCRDYR_HSIDIVRDY BIT(2)
  200. #define RCC_OCRDYR_CSIRDY BIT(4)
  201. #define RCC_OCRDYR_HSERDY BIT(8)
  202. /* Fields of DDRITFCR register */
  203. #define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
  204. #define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
  205. #define RCC_DDRITFCR_DDRCKMOD_SSR 0
  206. /* Fields of RCC_HSICFGR register */
  207. #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
  208. /* used for MCO related operations */
  209. #define RCC_MCOCFG_MCOON BIT(12)
  210. #define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
  211. #define RCC_MCOCFG_MCODIV_SHIFT 4
  212. #define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
  213. enum stm32mp1_parent_id {
  214. /*
  215. * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
  216. * they are used as index in osc[] as entry point
  217. */
  218. _HSI,
  219. _HSE,
  220. _CSI,
  221. _LSI,
  222. _LSE,
  223. _I2S_CKIN,
  224. NB_OSC,
  225. /* other parent source */
  226. _HSI_KER = NB_OSC,
  227. _HSE_KER,
  228. _HSE_KER_DIV2,
  229. _CSI_KER,
  230. _PLL1_P,
  231. _PLL1_Q,
  232. _PLL1_R,
  233. _PLL2_P,
  234. _PLL2_Q,
  235. _PLL2_R,
  236. _PLL3_P,
  237. _PLL3_Q,
  238. _PLL3_R,
  239. _PLL4_P,
  240. _PLL4_Q,
  241. _PLL4_R,
  242. _ACLK,
  243. _PCLK1,
  244. _PCLK2,
  245. _PCLK3,
  246. _PCLK4,
  247. _PCLK5,
  248. _HCLK6,
  249. _HCLK2,
  250. _CK_PER,
  251. _CK_MPU,
  252. _CK_MCU,
  253. _DSI_PHY,
  254. _USB_PHY_48,
  255. _PARENT_NB,
  256. _UNKNOWN_ID = 0xff,
  257. };
  258. enum stm32mp1_parent_sel {
  259. _I2C12_SEL,
  260. _I2C35_SEL,
  261. _I2C46_SEL,
  262. _UART6_SEL,
  263. _UART24_SEL,
  264. _UART35_SEL,
  265. _UART78_SEL,
  266. _SDMMC12_SEL,
  267. _SDMMC3_SEL,
  268. _ETH_SEL,
  269. _QSPI_SEL,
  270. _FMC_SEL,
  271. _USBPHY_SEL,
  272. _USBO_SEL,
  273. _STGEN_SEL,
  274. _DSI_SEL,
  275. _ADC12_SEL,
  276. _SPI1_SEL,
  277. _SPI45_SEL,
  278. _RTC_SEL,
  279. _PARENT_SEL_NB,
  280. _UNKNOWN_SEL = 0xff,
  281. };
  282. enum stm32mp1_pll_id {
  283. _PLL1,
  284. _PLL2,
  285. _PLL3,
  286. _PLL4,
  287. _PLL_NB
  288. };
  289. enum stm32mp1_div_id {
  290. _DIV_P,
  291. _DIV_Q,
  292. _DIV_R,
  293. _DIV_NB,
  294. };
  295. enum stm32mp1_clksrc_id {
  296. CLKSRC_MPU,
  297. CLKSRC_AXI,
  298. CLKSRC_MCU,
  299. CLKSRC_PLL12,
  300. CLKSRC_PLL3,
  301. CLKSRC_PLL4,
  302. CLKSRC_RTC,
  303. CLKSRC_MCO1,
  304. CLKSRC_MCO2,
  305. CLKSRC_NB
  306. };
  307. enum stm32mp1_clkdiv_id {
  308. CLKDIV_MPU,
  309. CLKDIV_AXI,
  310. CLKDIV_MCU,
  311. CLKDIV_APB1,
  312. CLKDIV_APB2,
  313. CLKDIV_APB3,
  314. CLKDIV_APB4,
  315. CLKDIV_APB5,
  316. CLKDIV_RTC,
  317. CLKDIV_MCO1,
  318. CLKDIV_MCO2,
  319. CLKDIV_NB
  320. };
  321. enum stm32mp1_pllcfg {
  322. PLLCFG_M,
  323. PLLCFG_N,
  324. PLLCFG_P,
  325. PLLCFG_Q,
  326. PLLCFG_R,
  327. PLLCFG_O,
  328. PLLCFG_NB
  329. };
  330. enum stm32mp1_pllcsg {
  331. PLLCSG_MOD_PER,
  332. PLLCSG_INC_STEP,
  333. PLLCSG_SSCG_MODE,
  334. PLLCSG_NB
  335. };
  336. enum stm32mp1_plltype {
  337. PLL_800,
  338. PLL_1600,
  339. PLL_TYPE_NB
  340. };
  341. struct stm32mp1_pll {
  342. u8 refclk_min;
  343. u8 refclk_max;
  344. u8 divn_max;
  345. };
  346. struct stm32mp1_clk_gate {
  347. u16 offset;
  348. u8 bit;
  349. u8 index;
  350. u8 set_clr;
  351. u8 sel;
  352. u8 fixed;
  353. };
  354. struct stm32mp1_clk_sel {
  355. u16 offset;
  356. u8 src;
  357. u8 msk;
  358. u8 nb_parent;
  359. const u8 *parent;
  360. };
  361. #define REFCLK_SIZE 4
  362. struct stm32mp1_clk_pll {
  363. enum stm32mp1_plltype plltype;
  364. u16 rckxselr;
  365. u16 pllxcfgr1;
  366. u16 pllxcfgr2;
  367. u16 pllxfracr;
  368. u16 pllxcr;
  369. u16 pllxcsgr;
  370. u8 refclk[REFCLK_SIZE];
  371. };
  372. struct stm32mp1_clk_data {
  373. const struct stm32mp1_clk_gate *gate;
  374. const struct stm32mp1_clk_sel *sel;
  375. const struct stm32mp1_clk_pll *pll;
  376. const int nb_gate;
  377. };
  378. struct stm32mp1_clk_priv {
  379. fdt_addr_t base;
  380. const struct stm32mp1_clk_data *data;
  381. ulong osc[NB_OSC];
  382. struct udevice *osc_dev[NB_OSC];
  383. };
  384. #define STM32MP1_CLK(off, b, idx, s) \
  385. { \
  386. .offset = (off), \
  387. .bit = (b), \
  388. .index = (idx), \
  389. .set_clr = 0, \
  390. .sel = (s), \
  391. .fixed = _UNKNOWN_ID, \
  392. }
  393. #define STM32MP1_CLK_F(off, b, idx, f) \
  394. { \
  395. .offset = (off), \
  396. .bit = (b), \
  397. .index = (idx), \
  398. .set_clr = 0, \
  399. .sel = _UNKNOWN_SEL, \
  400. .fixed = (f), \
  401. }
  402. #define STM32MP1_CLK_SET_CLR(off, b, idx, s) \
  403. { \
  404. .offset = (off), \
  405. .bit = (b), \
  406. .index = (idx), \
  407. .set_clr = 1, \
  408. .sel = (s), \
  409. .fixed = _UNKNOWN_ID, \
  410. }
  411. #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \
  412. { \
  413. .offset = (off), \
  414. .bit = (b), \
  415. .index = (idx), \
  416. .set_clr = 1, \
  417. .sel = _UNKNOWN_SEL, \
  418. .fixed = (f), \
  419. }
  420. #define STM32MP1_CLK_PARENT(idx, off, s, m, p) \
  421. [(idx)] = { \
  422. .offset = (off), \
  423. .src = (s), \
  424. .msk = (m), \
  425. .parent = (p), \
  426. .nb_parent = ARRAY_SIZE((p)) \
  427. }
  428. #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
  429. p1, p2, p3, p4) \
  430. [(idx)] = { \
  431. .plltype = (type), \
  432. .rckxselr = (off1), \
  433. .pllxcfgr1 = (off2), \
  434. .pllxcfgr2 = (off3), \
  435. .pllxfracr = (off4), \
  436. .pllxcr = (off5), \
  437. .pllxcsgr = (off6), \
  438. .refclk[0] = (p1), \
  439. .refclk[1] = (p2), \
  440. .refclk[2] = (p3), \
  441. .refclk[3] = (p4), \
  442. }
  443. static const u8 stm32mp1_clks[][2] = {
  444. {CK_PER, _CK_PER},
  445. {CK_MPU, _CK_MPU},
  446. {CK_AXI, _ACLK},
  447. {CK_MCU, _CK_MCU},
  448. {CK_HSE, _HSE},
  449. {CK_CSI, _CSI},
  450. {CK_LSI, _LSI},
  451. {CK_LSE, _LSE},
  452. {CK_HSI, _HSI},
  453. {CK_HSE_DIV2, _HSE_KER_DIV2},
  454. };
  455. static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
  456. STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
  457. STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
  458. STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
  459. STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
  460. STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
  461. STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
  462. STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
  463. STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
  464. STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
  465. STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
  466. STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
  467. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
  468. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
  469. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
  470. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
  471. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
  472. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
  473. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
  474. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
  475. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
  476. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
  477. STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
  478. STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 10, SPI5_K, _SPI45_SEL),
  479. STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
  480. STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
  481. STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
  482. STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
  483. STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
  484. STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
  485. STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
  486. STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
  487. STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
  488. STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
  489. STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
  490. STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
  491. STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
  492. STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
  493. STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
  494. STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
  495. STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
  496. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
  497. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
  498. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
  499. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
  500. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
  501. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
  502. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
  503. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
  504. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
  505. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
  506. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
  507. STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
  508. STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _UNKNOWN_SEL),
  509. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
  510. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
  511. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
  512. STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
  513. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
  514. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
  515. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
  516. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
  517. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
  518. STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
  519. STM32MP1_CLK(RCC_BDCR, 20, RTC, _RTC_SEL),
  520. };
  521. static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
  522. static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
  523. static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
  524. static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
  525. _HSE_KER};
  526. static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
  527. _HSE_KER};
  528. static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
  529. _HSE_KER};
  530. static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
  531. _HSE_KER};
  532. static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
  533. static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
  534. static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
  535. static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
  536. static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
  537. static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
  538. static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
  539. static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
  540. static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
  541. static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
  542. static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
  543. _PLL3_R};
  544. static const u8 spi45_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
  545. _HSE_KER};
  546. static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
  547. static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
  548. STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
  549. STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
  550. STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
  551. STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
  552. STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
  553. uart24_parents),
  554. STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
  555. uart35_parents),
  556. STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
  557. uart78_parents),
  558. STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
  559. sdmmc12_parents),
  560. STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
  561. sdmmc3_parents),
  562. STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
  563. STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0x3, qspi_parents),
  564. STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0x3, fmc_parents),
  565. STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
  566. STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
  567. STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
  568. STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
  569. STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents),
  570. STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
  571. STM32MP1_CLK_PARENT(_SPI45_SEL, RCC_SPI45CKSELR, 0, 0x7, spi45_parents),
  572. STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
  573. (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
  574. rtc_parents),
  575. };
  576. #ifdef STM32MP1_CLOCK_TREE_INIT
  577. /* define characteristic of PLL according type */
  578. #define DIVN_MIN 24
  579. static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
  580. [PLL_800] = {
  581. .refclk_min = 4,
  582. .refclk_max = 16,
  583. .divn_max = 99,
  584. },
  585. [PLL_1600] = {
  586. .refclk_min = 8,
  587. .refclk_max = 16,
  588. .divn_max = 199,
  589. },
  590. };
  591. #endif /* STM32MP1_CLOCK_TREE_INIT */
  592. static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
  593. STM32MP1_CLK_PLL(_PLL1, PLL_1600,
  594. RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
  595. RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
  596. _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
  597. STM32MP1_CLK_PLL(_PLL2, PLL_1600,
  598. RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
  599. RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
  600. _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
  601. STM32MP1_CLK_PLL(_PLL3, PLL_800,
  602. RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
  603. RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
  604. _HSI, _HSE, _CSI, _UNKNOWN_ID),
  605. STM32MP1_CLK_PLL(_PLL4, PLL_800,
  606. RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
  607. RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
  608. _HSI, _HSE, _CSI, _I2S_CKIN),
  609. };
  610. /* Prescaler table lookups for clock computation */
  611. /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
  612. static const u8 stm32mp1_mcu_div[16] = {
  613. 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
  614. };
  615. /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
  616. #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
  617. #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
  618. static const u8 stm32mp1_mpu_apbx_div[8] = {
  619. 0, 1, 2, 3, 4, 4, 4, 4
  620. };
  621. /* div = /1 /2 /3 /4 */
  622. static const u8 stm32mp1_axi_div[8] = {
  623. 1, 2, 3, 4, 4, 4, 4, 4
  624. };
  625. static const __maybe_unused
  626. char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
  627. [_HSI] = "HSI",
  628. [_HSE] = "HSE",
  629. [_CSI] = "CSI",
  630. [_LSI] = "LSI",
  631. [_LSE] = "LSE",
  632. [_I2S_CKIN] = "I2S_CKIN",
  633. [_HSI_KER] = "HSI_KER",
  634. [_HSE_KER] = "HSE_KER",
  635. [_HSE_KER_DIV2] = "HSE_KER_DIV2",
  636. [_CSI_KER] = "CSI_KER",
  637. [_PLL1_P] = "PLL1_P",
  638. [_PLL1_Q] = "PLL1_Q",
  639. [_PLL1_R] = "PLL1_R",
  640. [_PLL2_P] = "PLL2_P",
  641. [_PLL2_Q] = "PLL2_Q",
  642. [_PLL2_R] = "PLL2_R",
  643. [_PLL3_P] = "PLL3_P",
  644. [_PLL3_Q] = "PLL3_Q",
  645. [_PLL3_R] = "PLL3_R",
  646. [_PLL4_P] = "PLL4_P",
  647. [_PLL4_Q] = "PLL4_Q",
  648. [_PLL4_R] = "PLL4_R",
  649. [_ACLK] = "ACLK",
  650. [_PCLK1] = "PCLK1",
  651. [_PCLK2] = "PCLK2",
  652. [_PCLK3] = "PCLK3",
  653. [_PCLK4] = "PCLK4",
  654. [_PCLK5] = "PCLK5",
  655. [_HCLK6] = "KCLK6",
  656. [_HCLK2] = "HCLK2",
  657. [_CK_PER] = "CK_PER",
  658. [_CK_MPU] = "CK_MPU",
  659. [_CK_MCU] = "CK_MCU",
  660. [_USB_PHY_48] = "USB_PHY_48",
  661. [_DSI_PHY] = "DSI_PHY_PLL",
  662. };
  663. static const __maybe_unused
  664. char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
  665. [_I2C12_SEL] = "I2C12",
  666. [_I2C35_SEL] = "I2C35",
  667. [_I2C46_SEL] = "I2C46",
  668. [_UART6_SEL] = "UART6",
  669. [_UART24_SEL] = "UART24",
  670. [_UART35_SEL] = "UART35",
  671. [_UART78_SEL] = "UART78",
  672. [_SDMMC12_SEL] = "SDMMC12",
  673. [_SDMMC3_SEL] = "SDMMC3",
  674. [_ETH_SEL] = "ETH",
  675. [_QSPI_SEL] = "QSPI",
  676. [_FMC_SEL] = "FMC",
  677. [_USBPHY_SEL] = "USBPHY",
  678. [_USBO_SEL] = "USBO",
  679. [_STGEN_SEL] = "STGEN",
  680. [_DSI_SEL] = "DSI",
  681. [_ADC12_SEL] = "ADC12",
  682. [_SPI1_SEL] = "SPI1",
  683. [_SPI45_SEL] = "SPI45",
  684. [_RTC_SEL] = "RTC",
  685. };
  686. static const struct stm32mp1_clk_data stm32mp1_data = {
  687. .gate = stm32mp1_clk_gate,
  688. .sel = stm32mp1_clk_sel,
  689. .pll = stm32mp1_clk_pll,
  690. .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
  691. };
  692. static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
  693. {
  694. if (idx >= NB_OSC) {
  695. debug("%s: clk id %d not found\n", __func__, idx);
  696. return 0;
  697. }
  698. return priv->osc[idx];
  699. }
  700. static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
  701. {
  702. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  703. int i, nb_clks = priv->data->nb_gate;
  704. for (i = 0; i < nb_clks; i++) {
  705. if (gate[i].index == id)
  706. break;
  707. }
  708. if (i == nb_clks) {
  709. printf("%s: clk id %d not found\n", __func__, (u32)id);
  710. return -EINVAL;
  711. }
  712. return i;
  713. }
  714. static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
  715. int i)
  716. {
  717. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  718. if (gate[i].sel > _PARENT_SEL_NB) {
  719. printf("%s: parents for clk id %d not found\n",
  720. __func__, i);
  721. return -EINVAL;
  722. }
  723. return gate[i].sel;
  724. }
  725. static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
  726. int i)
  727. {
  728. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  729. if (gate[i].fixed == _UNKNOWN_ID)
  730. return -ENOENT;
  731. return gate[i].fixed;
  732. }
  733. static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
  734. unsigned long id)
  735. {
  736. const struct stm32mp1_clk_sel *sel = priv->data->sel;
  737. int i;
  738. int s, p;
  739. unsigned int idx;
  740. for (idx = 0; idx < ARRAY_SIZE(stm32mp1_clks); idx++)
  741. if (stm32mp1_clks[idx][0] == id)
  742. return stm32mp1_clks[idx][1];
  743. i = stm32mp1_clk_get_id(priv, id);
  744. if (i < 0)
  745. return i;
  746. p = stm32mp1_clk_get_fixed_parent(priv, i);
  747. if (p >= 0 && p < _PARENT_NB)
  748. return p;
  749. s = stm32mp1_clk_get_sel(priv, i);
  750. if (s < 0)
  751. return s;
  752. p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
  753. if (p < sel[s].nb_parent) {
  754. #ifdef DEBUG
  755. debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
  756. stm32mp1_clk_parent_name[sel[s].parent[p]],
  757. stm32mp1_clk_parent_sel_name[s],
  758. (u32)id);
  759. #endif
  760. return sel[s].parent[p];
  761. }
  762. pr_err("%s: no parents defined for clk id %d\n",
  763. __func__, (u32)id);
  764. return -EINVAL;
  765. }
  766. static ulong pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
  767. int pll_id)
  768. {
  769. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  770. u32 selr;
  771. int src;
  772. ulong refclk;
  773. /* Get current refclk */
  774. selr = readl(priv->base + pll[pll_id].rckxselr);
  775. src = selr & RCC_SELR_SRC_MASK;
  776. refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
  777. return refclk;
  778. }
  779. /*
  780. * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
  781. * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
  782. * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
  783. * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
  784. */
  785. static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
  786. int pll_id)
  787. {
  788. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  789. int divm, divn;
  790. ulong refclk, fvco;
  791. u32 cfgr1, fracr;
  792. cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
  793. fracr = readl(priv->base + pll[pll_id].pllxfracr);
  794. divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
  795. divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
  796. refclk = pll_get_fref_ck(priv, pll_id);
  797. /* with FRACV :
  798. * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
  799. * without FRACV
  800. * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
  801. */
  802. if (fracr & RCC_PLLNFRACR_FRACLE) {
  803. u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
  804. >> RCC_PLLNFRACR_FRACV_SHIFT;
  805. fvco = (ulong)lldiv((unsigned long long)refclk *
  806. (((divn + 1) << 13) + fracv),
  807. ((unsigned long long)(divm + 1)) << 13);
  808. } else {
  809. fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
  810. }
  811. return fvco;
  812. }
  813. static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
  814. int pll_id, int div_id)
  815. {
  816. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  817. int divy;
  818. ulong dfout;
  819. u32 cfgr2;
  820. if (div_id >= _DIV_NB)
  821. return 0;
  822. cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
  823. divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
  824. dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
  825. return dfout;
  826. }
  827. static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
  828. {
  829. u32 reg;
  830. ulong clock = 0;
  831. switch (p) {
  832. case _CK_MPU:
  833. /* MPU sub system */
  834. reg = readl(priv->base + RCC_MPCKSELR);
  835. switch (reg & RCC_SELR_SRC_MASK) {
  836. case RCC_MPCKSELR_HSI:
  837. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  838. break;
  839. case RCC_MPCKSELR_HSE:
  840. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  841. break;
  842. case RCC_MPCKSELR_PLL:
  843. case RCC_MPCKSELR_PLL_MPUDIV:
  844. clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
  845. if (p == RCC_MPCKSELR_PLL_MPUDIV) {
  846. reg = readl(priv->base + RCC_MPCKDIVR);
  847. clock /= stm32mp1_mpu_div[reg &
  848. RCC_MPUDIV_MASK];
  849. }
  850. break;
  851. }
  852. break;
  853. /* AXI sub system */
  854. case _ACLK:
  855. case _HCLK2:
  856. case _HCLK6:
  857. case _PCLK4:
  858. case _PCLK5:
  859. reg = readl(priv->base + RCC_ASSCKSELR);
  860. switch (reg & RCC_SELR_SRC_MASK) {
  861. case RCC_ASSCKSELR_HSI:
  862. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  863. break;
  864. case RCC_ASSCKSELR_HSE:
  865. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  866. break;
  867. case RCC_ASSCKSELR_PLL:
  868. clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
  869. break;
  870. }
  871. /* System clock divider */
  872. reg = readl(priv->base + RCC_AXIDIVR);
  873. clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
  874. switch (p) {
  875. case _PCLK4:
  876. reg = readl(priv->base + RCC_APB4DIVR);
  877. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  878. break;
  879. case _PCLK5:
  880. reg = readl(priv->base + RCC_APB5DIVR);
  881. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  882. break;
  883. default:
  884. break;
  885. }
  886. break;
  887. /* MCU sub system */
  888. case _CK_MCU:
  889. case _PCLK1:
  890. case _PCLK2:
  891. case _PCLK3:
  892. reg = readl(priv->base + RCC_MSSCKSELR);
  893. switch (reg & RCC_SELR_SRC_MASK) {
  894. case RCC_MSSCKSELR_HSI:
  895. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  896. break;
  897. case RCC_MSSCKSELR_HSE:
  898. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  899. break;
  900. case RCC_MSSCKSELR_CSI:
  901. clock = stm32mp1_clk_get_fixed(priv, _CSI);
  902. break;
  903. case RCC_MSSCKSELR_PLL:
  904. clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
  905. break;
  906. }
  907. /* MCU clock divider */
  908. reg = readl(priv->base + RCC_MCUDIVR);
  909. clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
  910. switch (p) {
  911. case _PCLK1:
  912. reg = readl(priv->base + RCC_APB1DIVR);
  913. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  914. break;
  915. case _PCLK2:
  916. reg = readl(priv->base + RCC_APB2DIVR);
  917. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  918. break;
  919. case _PCLK3:
  920. reg = readl(priv->base + RCC_APB3DIVR);
  921. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  922. break;
  923. case _CK_MCU:
  924. default:
  925. break;
  926. }
  927. break;
  928. case _CK_PER:
  929. reg = readl(priv->base + RCC_CPERCKSELR);
  930. switch (reg & RCC_SELR_SRC_MASK) {
  931. case RCC_CPERCKSELR_HSI:
  932. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  933. break;
  934. case RCC_CPERCKSELR_HSE:
  935. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  936. break;
  937. case RCC_CPERCKSELR_CSI:
  938. clock = stm32mp1_clk_get_fixed(priv, _CSI);
  939. break;
  940. }
  941. break;
  942. case _HSI:
  943. case _HSI_KER:
  944. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  945. break;
  946. case _CSI:
  947. case _CSI_KER:
  948. clock = stm32mp1_clk_get_fixed(priv, _CSI);
  949. break;
  950. case _HSE:
  951. case _HSE_KER:
  952. case _HSE_KER_DIV2:
  953. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  954. if (p == _HSE_KER_DIV2)
  955. clock >>= 1;
  956. break;
  957. case _LSI:
  958. clock = stm32mp1_clk_get_fixed(priv, _LSI);
  959. break;
  960. case _LSE:
  961. clock = stm32mp1_clk_get_fixed(priv, _LSE);
  962. break;
  963. /* PLL */
  964. case _PLL1_P:
  965. case _PLL1_Q:
  966. case _PLL1_R:
  967. clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
  968. break;
  969. case _PLL2_P:
  970. case _PLL2_Q:
  971. case _PLL2_R:
  972. clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
  973. break;
  974. case _PLL3_P:
  975. case _PLL3_Q:
  976. case _PLL3_R:
  977. clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
  978. break;
  979. case _PLL4_P:
  980. case _PLL4_Q:
  981. case _PLL4_R:
  982. clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
  983. break;
  984. /* other */
  985. case _USB_PHY_48:
  986. clock = 48000000;
  987. break;
  988. case _DSI_PHY:
  989. {
  990. struct clk clk;
  991. struct udevice *dev = NULL;
  992. if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
  993. &dev)) {
  994. if (clk_request(dev, &clk)) {
  995. pr_err("ck_dsi_phy request");
  996. } else {
  997. clk.id = 0;
  998. clock = clk_get_rate(&clk);
  999. }
  1000. }
  1001. break;
  1002. }
  1003. default:
  1004. break;
  1005. }
  1006. debug("%s(%d) clock = %lx : %ld kHz\n",
  1007. __func__, p, clock, clock / 1000);
  1008. return clock;
  1009. }
  1010. static int stm32mp1_clk_enable(struct clk *clk)
  1011. {
  1012. struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
  1013. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  1014. int i = stm32mp1_clk_get_id(priv, clk->id);
  1015. if (i < 0)
  1016. return i;
  1017. if (gate[i].set_clr)
  1018. writel(BIT(gate[i].bit), priv->base + gate[i].offset);
  1019. else
  1020. setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
  1021. debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
  1022. return 0;
  1023. }
  1024. static int stm32mp1_clk_disable(struct clk *clk)
  1025. {
  1026. struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
  1027. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  1028. int i = stm32mp1_clk_get_id(priv, clk->id);
  1029. if (i < 0)
  1030. return i;
  1031. if (gate[i].set_clr)
  1032. writel(BIT(gate[i].bit),
  1033. priv->base + gate[i].offset
  1034. + RCC_MP_ENCLRR_OFFSET);
  1035. else
  1036. clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
  1037. debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
  1038. return 0;
  1039. }
  1040. static ulong stm32mp1_clk_get_rate(struct clk *clk)
  1041. {
  1042. struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
  1043. int p = stm32mp1_clk_get_parent(priv, clk->id);
  1044. ulong rate;
  1045. if (p < 0)
  1046. return 0;
  1047. rate = stm32mp1_clk_get(priv, p);
  1048. #ifdef DEBUG
  1049. debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
  1050. __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
  1051. #endif
  1052. return rate;
  1053. }
  1054. #ifdef STM32MP1_CLOCK_TREE_INIT
  1055. static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
  1056. u32 mask_on)
  1057. {
  1058. u32 address = rcc + offset;
  1059. if (enable)
  1060. setbits_le32(address, mask_on);
  1061. else
  1062. clrbits_le32(address, mask_on);
  1063. }
  1064. static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
  1065. {
  1066. writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));
  1067. }
  1068. static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
  1069. u32 mask_rdy)
  1070. {
  1071. u32 mask_test = 0;
  1072. u32 address = rcc + offset;
  1073. u32 val;
  1074. int ret;
  1075. if (enable)
  1076. mask_test = mask_rdy;
  1077. ret = readl_poll_timeout(address, val,
  1078. (val & mask_rdy) == mask_test,
  1079. TIMEOUT_1S);
  1080. if (ret)
  1081. pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
  1082. mask_rdy, address, enable, readl(address));
  1083. return ret;
  1084. }
  1085. static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
  1086. u32 lsedrv)
  1087. {
  1088. u32 value;
  1089. if (digbyp)
  1090. setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
  1091. if (bypass || digbyp)
  1092. setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
  1093. /*
  1094. * warning: not recommended to switch directly from "high drive"
  1095. * to "medium low drive", and vice-versa.
  1096. */
  1097. value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
  1098. >> RCC_BDCR_LSEDRV_SHIFT;
  1099. while (value != lsedrv) {
  1100. if (value > lsedrv)
  1101. value--;
  1102. else
  1103. value++;
  1104. clrsetbits_le32(rcc + RCC_BDCR,
  1105. RCC_BDCR_LSEDRV_MASK,
  1106. value << RCC_BDCR_LSEDRV_SHIFT);
  1107. }
  1108. stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
  1109. }
  1110. static void stm32mp1_lse_wait(fdt_addr_t rcc)
  1111. {
  1112. stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
  1113. }
  1114. static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
  1115. {
  1116. stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
  1117. stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
  1118. }
  1119. static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
  1120. {
  1121. if (digbyp)
  1122. writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);
  1123. if (bypass || digbyp)
  1124. writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);
  1125. stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
  1126. stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
  1127. if (css)
  1128. writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);
  1129. }
  1130. static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
  1131. {
  1132. stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);
  1133. stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
  1134. }
  1135. static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
  1136. {
  1137. stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
  1138. stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
  1139. }
  1140. static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
  1141. {
  1142. u32 address = rcc + RCC_OCRDYR;
  1143. u32 val;
  1144. int ret;
  1145. clrsetbits_le32(rcc + RCC_HSICFGR,
  1146. RCC_HSICFGR_HSIDIV_MASK,
  1147. RCC_HSICFGR_HSIDIV_MASK & hsidiv);
  1148. ret = readl_poll_timeout(address, val,
  1149. val & RCC_OCRDYR_HSIDIVRDY,
  1150. TIMEOUT_200MS);
  1151. if (ret)
  1152. pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
  1153. address, readl(address));
  1154. return ret;
  1155. }
  1156. static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
  1157. {
  1158. u8 hsidiv;
  1159. u32 hsidivfreq = MAX_HSI_HZ;
  1160. for (hsidiv = 0; hsidiv < 4; hsidiv++,
  1161. hsidivfreq = hsidivfreq / 2)
  1162. if (hsidivfreq == hsifreq)
  1163. break;
  1164. if (hsidiv == 4) {
  1165. pr_err("clk-hsi frequency invalid");
  1166. return -1;
  1167. }
  1168. if (hsidiv > 0)
  1169. return stm32mp1_set_hsidiv(rcc, hsidiv);
  1170. return 0;
  1171. }
  1172. static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
  1173. {
  1174. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1175. clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
  1176. RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
  1177. RCC_PLLNCR_DIVREN,
  1178. RCC_PLLNCR_PLLON);
  1179. }
  1180. static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
  1181. {
  1182. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1183. u32 pllxcr = priv->base + pll[pll_id].pllxcr;
  1184. u32 val;
  1185. int ret;
  1186. ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
  1187. TIMEOUT_200MS);
  1188. if (ret) {
  1189. pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
  1190. pll_id, pllxcr, readl(pllxcr));
  1191. return ret;
  1192. }
  1193. /* start the requested output */
  1194. setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
  1195. return 0;
  1196. }
  1197. static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
  1198. {
  1199. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1200. u32 pllxcr = priv->base + pll[pll_id].pllxcr;
  1201. u32 val;
  1202. /* stop all output */
  1203. clrbits_le32(pllxcr,
  1204. RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
  1205. /* stop PLL */
  1206. clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
  1207. /* wait PLL stopped */
  1208. return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
  1209. TIMEOUT_200MS);
  1210. }
  1211. static void pll_config_output(struct stm32mp1_clk_priv *priv,
  1212. int pll_id, u32 *pllcfg)
  1213. {
  1214. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1215. fdt_addr_t rcc = priv->base;
  1216. u32 value;
  1217. value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
  1218. & RCC_PLLNCFGR2_DIVP_MASK;
  1219. value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
  1220. & RCC_PLLNCFGR2_DIVQ_MASK;
  1221. value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
  1222. & RCC_PLLNCFGR2_DIVR_MASK;
  1223. writel(value, rcc + pll[pll_id].pllxcfgr2);
  1224. }
  1225. static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
  1226. u32 *pllcfg, u32 fracv)
  1227. {
  1228. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1229. fdt_addr_t rcc = priv->base;
  1230. enum stm32mp1_plltype type = pll[pll_id].plltype;
  1231. int src;
  1232. ulong refclk;
  1233. u8 ifrge = 0;
  1234. u32 value;
  1235. src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
  1236. refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
  1237. (pllcfg[PLLCFG_M] + 1);
  1238. if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
  1239. refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
  1240. debug("invalid refclk = %x\n", (u32)refclk);
  1241. return -EINVAL;
  1242. }
  1243. if (type == PLL_800 && refclk >= 8000000)
  1244. ifrge = 1;
  1245. value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
  1246. & RCC_PLLNCFGR1_DIVN_MASK;
  1247. value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
  1248. & RCC_PLLNCFGR1_DIVM_MASK;
  1249. value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
  1250. & RCC_PLLNCFGR1_IFRGE_MASK;
  1251. writel(value, rcc + pll[pll_id].pllxcfgr1);
  1252. /* fractional configuration: load sigma-delta modulator (SDM) */
  1253. /* Write into FRACV the new fractional value , and FRACLE to 0 */
  1254. writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
  1255. rcc + pll[pll_id].pllxfracr);
  1256. /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
  1257. setbits_le32(rcc + pll[pll_id].pllxfracr,
  1258. RCC_PLLNFRACR_FRACLE);
  1259. pll_config_output(priv, pll_id, pllcfg);
  1260. return 0;
  1261. }
  1262. static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
  1263. {
  1264. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1265. u32 pllxcsg;
  1266. pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
  1267. RCC_PLLNCSGR_MOD_PER_MASK) |
  1268. ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
  1269. RCC_PLLNCSGR_INC_STEP_MASK) |
  1270. ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
  1271. RCC_PLLNCSGR_SSCG_MODE_MASK);
  1272. writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
  1273. setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
  1274. }
  1275. static __maybe_unused int pll_set_rate(struct udevice *dev,
  1276. int pll_id,
  1277. int div_id,
  1278. unsigned long clk_rate)
  1279. {
  1280. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1281. unsigned int pllcfg[PLLCFG_NB];
  1282. ofnode plloff;
  1283. char name[12];
  1284. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1285. enum stm32mp1_plltype type = pll[pll_id].plltype;
  1286. int divm, divn, divy;
  1287. int ret;
  1288. ulong fck_ref;
  1289. u32 fracv;
  1290. u64 value;
  1291. if (div_id > _DIV_NB)
  1292. return -EINVAL;
  1293. sprintf(name, "st,pll@%d", pll_id);
  1294. plloff = dev_read_subnode(dev, name);
  1295. if (!ofnode_valid(plloff))
  1296. return -FDT_ERR_NOTFOUND;
  1297. ret = ofnode_read_u32_array(plloff, "cfg",
  1298. pllcfg, PLLCFG_NB);
  1299. if (ret < 0)
  1300. return -FDT_ERR_NOTFOUND;
  1301. fck_ref = pll_get_fref_ck(priv, pll_id);
  1302. divm = pllcfg[PLLCFG_M];
  1303. /* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */
  1304. divy = pllcfg[PLLCFG_P + div_id];
  1305. /* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
  1306. * So same final result than PLL2 et 4
  1307. * with FRACV
  1308. * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
  1309. * / (DIVy + 1) * (DIVM + 1)
  1310. * value = (DIVN + 1) * 2^13 + FRACV / 2^13
  1311. * = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref
  1312. */
  1313. value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13;
  1314. value = lldiv(value, fck_ref);
  1315. divn = (value >> 13) - 1;
  1316. if (divn < DIVN_MIN ||
  1317. divn > stm32mp1_pll[type].divn_max) {
  1318. pr_err("divn invalid = %d", divn);
  1319. return -EINVAL;
  1320. }
  1321. fracv = value - ((divn + 1) << 13);
  1322. pllcfg[PLLCFG_N] = divn;
  1323. /* reconfigure PLL */
  1324. pll_stop(priv, pll_id);
  1325. pll_config(priv, pll_id, pllcfg, fracv);
  1326. pll_start(priv, pll_id);
  1327. pll_output(priv, pll_id, pllcfg[PLLCFG_O]);
  1328. return 0;
  1329. }
  1330. static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
  1331. {
  1332. u32 address = priv->base + (clksrc >> 4);
  1333. u32 val;
  1334. int ret;
  1335. clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
  1336. ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
  1337. TIMEOUT_200MS);
  1338. if (ret)
  1339. pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
  1340. clksrc, address, readl(address));
  1341. return ret;
  1342. }
  1343. static void stgen_config(struct stm32mp1_clk_priv *priv)
  1344. {
  1345. int p;
  1346. u32 stgenc, cntfid0;
  1347. ulong rate;
  1348. stgenc = STM32_STGEN_BASE;
  1349. cntfid0 = readl(stgenc + STGENC_CNTFID0);
  1350. p = stm32mp1_clk_get_parent(priv, STGEN_K);
  1351. rate = stm32mp1_clk_get(priv, p);
  1352. if (cntfid0 != rate) {
  1353. u64 counter;
  1354. pr_debug("System Generic Counter (STGEN) update\n");
  1355. clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
  1356. counter = (u64)readl(stgenc + STGENC_CNTCVL);
  1357. counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
  1358. counter = lldiv(counter * (u64)rate, cntfid0);
  1359. writel((u32)counter, stgenc + STGENC_CNTCVL);
  1360. writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU);
  1361. writel(rate, stgenc + STGENC_CNTFID0);
  1362. setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
  1363. __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
  1364. /* need to update gd->arch.timer_rate_hz with new frequency */
  1365. timer_init();
  1366. }
  1367. }
  1368. static int set_clkdiv(unsigned int clkdiv, u32 address)
  1369. {
  1370. u32 val;
  1371. int ret;
  1372. clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
  1373. ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
  1374. TIMEOUT_200MS);
  1375. if (ret)
  1376. pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
  1377. clkdiv, address, readl(address));
  1378. return ret;
  1379. }
  1380. static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
  1381. u32 clksrc, u32 clkdiv)
  1382. {
  1383. u32 address = priv->base + (clksrc >> 4);
  1384. /*
  1385. * binding clksrc : bit15-4 offset
  1386. * bit3: disable
  1387. * bit2-0: MCOSEL[2:0]
  1388. */
  1389. if (clksrc & 0x8) {
  1390. clrbits_le32(address, RCC_MCOCFG_MCOON);
  1391. } else {
  1392. clrsetbits_le32(address,
  1393. RCC_MCOCFG_MCOSRC_MASK,
  1394. clksrc & RCC_MCOCFG_MCOSRC_MASK);
  1395. clrsetbits_le32(address,
  1396. RCC_MCOCFG_MCODIV_MASK,
  1397. clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
  1398. setbits_le32(address, RCC_MCOCFG_MCOON);
  1399. }
  1400. }
  1401. static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
  1402. unsigned int clksrc,
  1403. int lse_css)
  1404. {
  1405. u32 address = priv->base + RCC_BDCR;
  1406. if (readl(address) & RCC_BDCR_RTCCKEN)
  1407. goto skip_rtc;
  1408. if (clksrc == CLK_RTC_DISABLED)
  1409. goto skip_rtc;
  1410. clrsetbits_le32(address,
  1411. RCC_BDCR_RTCSRC_MASK,
  1412. clksrc << RCC_BDCR_RTCSRC_SHIFT);
  1413. setbits_le32(address, RCC_BDCR_RTCCKEN);
  1414. skip_rtc:
  1415. if (lse_css)
  1416. setbits_le32(address, RCC_BDCR_LSECSSON);
  1417. }
  1418. static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
  1419. {
  1420. u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
  1421. u32 value = pkcs & 0xF;
  1422. u32 mask = 0xF;
  1423. if (pkcs & BIT(31)) {
  1424. mask <<= 4;
  1425. value <<= 4;
  1426. }
  1427. clrsetbits_le32(address, mask, value);
  1428. }
  1429. static int stm32mp1_clktree(struct udevice *dev)
  1430. {
  1431. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1432. fdt_addr_t rcc = priv->base;
  1433. unsigned int clksrc[CLKSRC_NB];
  1434. unsigned int clkdiv[CLKDIV_NB];
  1435. unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
  1436. ofnode plloff[_PLL_NB];
  1437. int ret, len;
  1438. uint i;
  1439. int lse_css = 0;
  1440. const u32 *pkcs_cell;
  1441. /* check mandatory field */
  1442. ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
  1443. if (ret < 0) {
  1444. debug("field st,clksrc invalid: error %d\n", ret);
  1445. return -FDT_ERR_NOTFOUND;
  1446. }
  1447. ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
  1448. if (ret < 0) {
  1449. debug("field st,clkdiv invalid: error %d\n", ret);
  1450. return -FDT_ERR_NOTFOUND;
  1451. }
  1452. /* check mandatory field in each pll */
  1453. for (i = 0; i < _PLL_NB; i++) {
  1454. char name[12];
  1455. sprintf(name, "st,pll@%d", i);
  1456. plloff[i] = dev_read_subnode(dev, name);
  1457. if (!ofnode_valid(plloff[i]))
  1458. continue;
  1459. ret = ofnode_read_u32_array(plloff[i], "cfg",
  1460. pllcfg[i], PLLCFG_NB);
  1461. if (ret < 0) {
  1462. debug("field cfg invalid: error %d\n", ret);
  1463. return -FDT_ERR_NOTFOUND;
  1464. }
  1465. }
  1466. debug("configuration MCO\n");
  1467. stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
  1468. stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
  1469. debug("switch ON osillator\n");
  1470. /*
  1471. * switch ON oscillator found in device-tree,
  1472. * HSI already ON after bootrom
  1473. */
  1474. if (priv->osc[_LSI])
  1475. stm32mp1_lsi_set(rcc, 1);
  1476. if (priv->osc[_LSE]) {
  1477. int bypass, digbyp;
  1478. u32 lsedrv;
  1479. struct udevice *dev = priv->osc_dev[_LSE];
  1480. bypass = dev_read_bool(dev, "st,bypass");
  1481. digbyp = dev_read_bool(dev, "st,digbypass");
  1482. lse_css = dev_read_bool(dev, "st,css");
  1483. lsedrv = dev_read_u32_default(dev, "st,drive",
  1484. LSEDRV_MEDIUM_HIGH);
  1485. stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
  1486. }
  1487. if (priv->osc[_HSE]) {
  1488. int bypass, digbyp, css;
  1489. struct udevice *dev = priv->osc_dev[_HSE];
  1490. bypass = dev_read_bool(dev, "st,bypass");
  1491. digbyp = dev_read_bool(dev, "st,digbypass");
  1492. css = dev_read_bool(dev, "st,css");
  1493. stm32mp1_hse_enable(rcc, bypass, digbyp, css);
  1494. }
  1495. /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
  1496. * => switch on CSI even if node is not present in device tree
  1497. */
  1498. stm32mp1_csi_set(rcc, 1);
  1499. /* come back to HSI */
  1500. debug("come back to HSI\n");
  1501. set_clksrc(priv, CLK_MPU_HSI);
  1502. set_clksrc(priv, CLK_AXI_HSI);
  1503. set_clksrc(priv, CLK_MCU_HSI);
  1504. debug("pll stop\n");
  1505. for (i = 0; i < _PLL_NB; i++)
  1506. pll_stop(priv, i);
  1507. /* configure HSIDIV */
  1508. debug("configure HSIDIV\n");
  1509. if (priv->osc[_HSI]) {
  1510. stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
  1511. stgen_config(priv);
  1512. }
  1513. /* select DIV */
  1514. debug("select DIV\n");
  1515. /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
  1516. writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
  1517. set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
  1518. set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
  1519. set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
  1520. set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
  1521. set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
  1522. set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
  1523. set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
  1524. /* no ready bit for RTC */
  1525. writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
  1526. /* configure PLLs source */
  1527. debug("configure PLLs source\n");
  1528. set_clksrc(priv, clksrc[CLKSRC_PLL12]);
  1529. set_clksrc(priv, clksrc[CLKSRC_PLL3]);
  1530. set_clksrc(priv, clksrc[CLKSRC_PLL4]);
  1531. /* configure and start PLLs */
  1532. debug("configure PLLs\n");
  1533. for (i = 0; i < _PLL_NB; i++) {
  1534. u32 fracv;
  1535. u32 csg[PLLCSG_NB];
  1536. debug("configure PLL %d @ %d\n", i,
  1537. ofnode_to_offset(plloff[i]));
  1538. if (!ofnode_valid(plloff[i]))
  1539. continue;
  1540. fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
  1541. pll_config(priv, i, pllcfg[i], fracv);
  1542. ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
  1543. if (!ret) {
  1544. pll_csg(priv, i, csg);
  1545. } else if (ret != -FDT_ERR_NOTFOUND) {
  1546. debug("invalid csg node for pll@%d res=%d\n", i, ret);
  1547. return ret;
  1548. }
  1549. pll_start(priv, i);
  1550. }
  1551. /* wait and start PLLs ouptut when ready */
  1552. for (i = 0; i < _PLL_NB; i++) {
  1553. if (!ofnode_valid(plloff[i]))
  1554. continue;
  1555. debug("output PLL %d\n", i);
  1556. pll_output(priv, i, pllcfg[i][PLLCFG_O]);
  1557. }
  1558. /* wait LSE ready before to use it */
  1559. if (priv->osc[_LSE])
  1560. stm32mp1_lse_wait(rcc);
  1561. /* configure with expected clock source */
  1562. debug("CLKSRC\n");
  1563. set_clksrc(priv, clksrc[CLKSRC_MPU]);
  1564. set_clksrc(priv, clksrc[CLKSRC_AXI]);
  1565. set_clksrc(priv, clksrc[CLKSRC_MCU]);
  1566. set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
  1567. /* configure PKCK */
  1568. debug("PKCK\n");
  1569. pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
  1570. if (pkcs_cell) {
  1571. bool ckper_disabled = false;
  1572. for (i = 0; i < len / sizeof(u32); i++) {
  1573. u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
  1574. if (pkcs == CLK_CKPER_DISABLED) {
  1575. ckper_disabled = true;
  1576. continue;
  1577. }
  1578. pkcs_config(priv, pkcs);
  1579. }
  1580. /* CKPER is source for some peripheral clock
  1581. * (FMC-NAND / QPSI-NOR) and switching source is allowed
  1582. * only if previous clock is still ON
  1583. * => deactivated CKPER only after switching clock
  1584. */
  1585. if (ckper_disabled)
  1586. pkcs_config(priv, CLK_CKPER_DISABLED);
  1587. }
  1588. /* STGEN clock source can change with CLK_STGEN_XXX */
  1589. stgen_config(priv);
  1590. debug("oscillator off\n");
  1591. /* switch OFF HSI if not found in device-tree */
  1592. if (!priv->osc[_HSI])
  1593. stm32mp1_hsi_set(rcc, 0);
  1594. /* Software Self-Refresh mode (SSR) during DDR initilialization */
  1595. clrsetbits_le32(priv->base + RCC_DDRITFCR,
  1596. RCC_DDRITFCR_DDRCKMOD_MASK,
  1597. RCC_DDRITFCR_DDRCKMOD_SSR <<
  1598. RCC_DDRITFCR_DDRCKMOD_SHIFT);
  1599. return 0;
  1600. }
  1601. #endif /* STM32MP1_CLOCK_TREE_INIT */
  1602. static int pll_set_output_rate(struct udevice *dev,
  1603. int pll_id,
  1604. int div_id,
  1605. unsigned long clk_rate)
  1606. {
  1607. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1608. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1609. u32 pllxcr = priv->base + pll[pll_id].pllxcr;
  1610. int div;
  1611. ulong fvco;
  1612. if (div_id > _DIV_NB)
  1613. return -EINVAL;
  1614. fvco = pll_get_fvco(priv, pll_id);
  1615. if (fvco <= clk_rate)
  1616. div = 1;
  1617. else
  1618. div = DIV_ROUND_UP(fvco, clk_rate);
  1619. if (div > 128)
  1620. div = 128;
  1621. /* stop the requested output */
  1622. clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
  1623. /* change divider */
  1624. clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
  1625. RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
  1626. (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
  1627. /* start the requested output */
  1628. setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
  1629. return 0;
  1630. }
  1631. static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
  1632. {
  1633. struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
  1634. int p;
  1635. switch (clk->id) {
  1636. #if defined(STM32MP1_CLOCK_TREE_INIT) && \
  1637. defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
  1638. case DDRPHYC:
  1639. break;
  1640. #endif
  1641. case LTDC_PX:
  1642. case DSI_PX:
  1643. break;
  1644. default:
  1645. pr_err("not supported");
  1646. return -EINVAL;
  1647. }
  1648. p = stm32mp1_clk_get_parent(priv, clk->id);
  1649. #ifdef DEBUG
  1650. debug("%s: parent = %d:%s\n", __func__, p, stm32mp1_clk_parent_name[p]);
  1651. #endif
  1652. if (p < 0)
  1653. return -EINVAL;
  1654. switch (p) {
  1655. #if defined(STM32MP1_CLOCK_TREE_INIT) && \
  1656. defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
  1657. case _PLL2_R: /* DDRPHYC */
  1658. {
  1659. /* only for change DDR clock in interactive mode */
  1660. ulong result;
  1661. set_clksrc(priv, CLK_AXI_HSI);
  1662. result = pll_set_rate(clk->dev, _PLL2, _DIV_R, clk_rate);
  1663. set_clksrc(priv, CLK_AXI_PLL2P);
  1664. return result;
  1665. }
  1666. #endif
  1667. case _PLL4_Q:
  1668. /* for LTDC_PX and DSI_PX case */
  1669. return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
  1670. }
  1671. return -EINVAL;
  1672. }
  1673. static void stm32mp1_osc_clk_init(const char *name,
  1674. struct stm32mp1_clk_priv *priv,
  1675. int index)
  1676. {
  1677. struct clk clk;
  1678. struct udevice *dev = NULL;
  1679. priv->osc[index] = 0;
  1680. clk.id = 0;
  1681. if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
  1682. if (clk_request(dev, &clk))
  1683. pr_err("%s request", name);
  1684. else
  1685. priv->osc[index] = clk_get_rate(&clk);
  1686. }
  1687. priv->osc_dev[index] = dev;
  1688. }
  1689. static void stm32mp1_osc_init(struct udevice *dev)
  1690. {
  1691. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1692. int i;
  1693. const char *name[NB_OSC] = {
  1694. [_LSI] = "clk-lsi",
  1695. [_LSE] = "clk-lse",
  1696. [_HSI] = "clk-hsi",
  1697. [_HSE] = "clk-hse",
  1698. [_CSI] = "clk-csi",
  1699. [_I2S_CKIN] = "i2s_ckin",
  1700. };
  1701. for (i = 0; i < NB_OSC; i++) {
  1702. stm32mp1_osc_clk_init(name[i], priv, i);
  1703. debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
  1704. }
  1705. }
  1706. static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
  1707. {
  1708. char buf[32];
  1709. int i, s, p;
  1710. printf("Clocks:\n");
  1711. for (i = 0; i < _PARENT_NB; i++) {
  1712. printf("- %s : %s MHz\n",
  1713. stm32mp1_clk_parent_name[i],
  1714. strmhz(buf, stm32mp1_clk_get(priv, i)));
  1715. }
  1716. printf("Source Clocks:\n");
  1717. for (i = 0; i < _PARENT_SEL_NB; i++) {
  1718. p = (readl(priv->base + priv->data->sel[i].offset) >>
  1719. priv->data->sel[i].src) & priv->data->sel[i].msk;
  1720. if (p < priv->data->sel[i].nb_parent) {
  1721. s = priv->data->sel[i].parent[p];
  1722. printf("- %s(%d) => parent %s(%d)\n",
  1723. stm32mp1_clk_parent_sel_name[i], i,
  1724. stm32mp1_clk_parent_name[s], s);
  1725. } else {
  1726. printf("- %s(%d) => parent index %d is invalid\n",
  1727. stm32mp1_clk_parent_sel_name[i], i, p);
  1728. }
  1729. }
  1730. }
  1731. #ifdef CONFIG_CMD_CLK
  1732. int soc_clk_dump(void)
  1733. {
  1734. struct udevice *dev;
  1735. struct stm32mp1_clk_priv *priv;
  1736. int ret;
  1737. ret = uclass_get_device_by_driver(UCLASS_CLK,
  1738. DM_GET_DRIVER(stm32mp1_clock),
  1739. &dev);
  1740. if (ret)
  1741. return ret;
  1742. priv = dev_get_priv(dev);
  1743. stm32mp1_clk_dump(priv);
  1744. return 0;
  1745. }
  1746. #endif
  1747. static int stm32mp1_clk_probe(struct udevice *dev)
  1748. {
  1749. int result = 0;
  1750. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1751. priv->base = dev_read_addr(dev->parent);
  1752. if (priv->base == FDT_ADDR_T_NONE)
  1753. return -EINVAL;
  1754. priv->data = (void *)&stm32mp1_data;
  1755. if (!priv->data->gate || !priv->data->sel ||
  1756. !priv->data->pll)
  1757. return -EINVAL;
  1758. stm32mp1_osc_init(dev);
  1759. #ifdef STM32MP1_CLOCK_TREE_INIT
  1760. /* clock tree init is done only one time, before relocation */
  1761. if (!(gd->flags & GD_FLG_RELOC))
  1762. result = stm32mp1_clktree(dev);
  1763. #endif
  1764. #ifndef CONFIG_SPL_BUILD
  1765. #if defined(DEBUG)
  1766. /* display debug information for probe after relocation */
  1767. if (gd->flags & GD_FLG_RELOC)
  1768. stm32mp1_clk_dump(priv);
  1769. #endif
  1770. gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU);
  1771. gd->bus_clk = stm32mp1_clk_get(priv, _ACLK);
  1772. /* DDRPHYC father */
  1773. gd->mem_clk = stm32mp1_clk_get(priv, _PLL2_R);
  1774. #if defined(CONFIG_DISPLAY_CPUINFO)
  1775. if (gd->flags & GD_FLG_RELOC) {
  1776. char buf[32];
  1777. printf("Clocks:\n");
  1778. printf("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
  1779. printf("- MCU : %s MHz\n",
  1780. strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
  1781. printf("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
  1782. printf("- PER : %s MHz\n",
  1783. strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
  1784. printf("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
  1785. }
  1786. #endif /* CONFIG_DISPLAY_CPUINFO */
  1787. #endif
  1788. return result;
  1789. }
  1790. static const struct clk_ops stm32mp1_clk_ops = {
  1791. .enable = stm32mp1_clk_enable,
  1792. .disable = stm32mp1_clk_disable,
  1793. .get_rate = stm32mp1_clk_get_rate,
  1794. .set_rate = stm32mp1_clk_set_rate,
  1795. };
  1796. U_BOOT_DRIVER(stm32mp1_clock) = {
  1797. .name = "stm32mp1_clk",
  1798. .id = UCLASS_CLK,
  1799. .ops = &stm32mp1_clk_ops,
  1800. .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
  1801. .probe = stm32mp1_clk_probe,
  1802. };