clk_stm32h7.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  4. * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
  5. */
  6. #include <common.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <regmap.h>
  10. #include <syscon.h>
  11. #include <asm/io.h>
  12. #include <dm/root.h>
  13. #include <dt-bindings/clock/stm32h7-clks.h>
  14. /* RCC CR specific definitions */
  15. #define RCC_CR_HSION BIT(0)
  16. #define RCC_CR_HSIRDY BIT(2)
  17. #define RCC_CR_HSEON BIT(16)
  18. #define RCC_CR_HSERDY BIT(17)
  19. #define RCC_CR_HSEBYP BIT(18)
  20. #define RCC_CR_PLL1ON BIT(24)
  21. #define RCC_CR_PLL1RDY BIT(25)
  22. #define RCC_CR_HSIDIV_MASK GENMASK(4, 3)
  23. #define RCC_CR_HSIDIV_SHIFT 3
  24. #define RCC_CFGR_SW_MASK GENMASK(2, 0)
  25. #define RCC_CFGR_SW_HSI 0
  26. #define RCC_CFGR_SW_CSI 1
  27. #define RCC_CFGR_SW_HSE 2
  28. #define RCC_CFGR_SW_PLL1 3
  29. #define RCC_CFGR_TIMPRE BIT(15)
  30. #define RCC_PLLCKSELR_PLLSRC_HSI 0
  31. #define RCC_PLLCKSELR_PLLSRC_CSI 1
  32. #define RCC_PLLCKSELR_PLLSRC_HSE 2
  33. #define RCC_PLLCKSELR_PLLSRC_NO_CLK 3
  34. #define RCC_PLLCKSELR_PLLSRC_MASK GENMASK(1, 0)
  35. #define RCC_PLLCKSELR_DIVM1_SHIFT 4
  36. #define RCC_PLLCKSELR_DIVM1_MASK GENMASK(9, 4)
  37. #define RCC_PLL1DIVR_DIVN1_MASK GENMASK(8, 0)
  38. #define RCC_PLL1DIVR_DIVP1_SHIFT 9
  39. #define RCC_PLL1DIVR_DIVP1_MASK GENMASK(15, 9)
  40. #define RCC_PLL1DIVR_DIVQ1_SHIFT 16
  41. #define RCC_PLL1DIVR_DIVQ1_MASK GENMASK(22, 16)
  42. #define RCC_PLL1DIVR_DIVR1_SHIFT 24
  43. #define RCC_PLL1DIVR_DIVR1_MASK GENMASK(30, 24)
  44. #define RCC_PLL1FRACR_FRACN1_SHIFT 3
  45. #define RCC_PLL1FRACR_FRACN1_MASK GENMASK(15, 3)
  46. #define RCC_PLLCFGR_PLL1RGE_SHIFT 2
  47. #define PLL1RGE_1_2_MHZ 0
  48. #define PLL1RGE_2_4_MHZ 1
  49. #define PLL1RGE_4_8_MHZ 2
  50. #define PLL1RGE_8_16_MHZ 3
  51. #define RCC_PLLCFGR_DIVP1EN BIT(16)
  52. #define RCC_PLLCFGR_DIVQ1EN BIT(17)
  53. #define RCC_PLLCFGR_DIVR1EN BIT(18)
  54. #define RCC_D1CFGR_HPRE_MASK GENMASK(3, 0)
  55. #define RCC_D1CFGR_HPRE_DIVIDED BIT(3)
  56. #define RCC_D1CFGR_HPRE_DIVIDER GENMASK(2, 0)
  57. #define RCC_D1CFGR_HPRE_DIV2 8
  58. #define RCC_D1CFGR_D1PPRE_SHIFT 4
  59. #define RCC_D1CFGR_D1PPRE_DIVIDED BIT(6)
  60. #define RCC_D1CFGR_D1PPRE_DIVIDER GENMASK(5, 4)
  61. #define RCC_D1CFGR_D1CPRE_SHIFT 8
  62. #define RCC_D1CFGR_D1CPRE_DIVIDER GENMASK(10, 8)
  63. #define RCC_D1CFGR_D1CPRE_DIVIDED BIT(11)
  64. #define RCC_D2CFGR_D2PPRE1_SHIFT 4
  65. #define RCC_D2CFGR_D2PPRE1_DIVIDED BIT(6)
  66. #define RCC_D2CFGR_D2PPRE1_DIVIDER GENMASK(5, 4)
  67. #define RCC_D2CFGR_D2PPRE2_SHIFT 8
  68. #define RCC_D2CFGR_D2PPRE2_DIVIDED BIT(10)
  69. #define RCC_D2CFGR_D2PPRE2_DIVIDER GENMASK(9, 8)
  70. #define RCC_D3CFGR_D3PPRE_SHIFT 4
  71. #define RCC_D3CFGR_D3PPRE_DIVIDED BIT(6)
  72. #define RCC_D3CFGR_D3PPRE_DIVIDER GENMASK(5, 4)
  73. #define RCC_D1CCIPR_FMCSRC_MASK GENMASK(1, 0)
  74. #define FMCSRC_HCLKD1 0
  75. #define FMCSRC_PLL1_Q_CK 1
  76. #define FMCSRC_PLL2_R_CK 2
  77. #define FMCSRC_PER_CK 3
  78. #define RCC_D1CCIPR_QSPISRC_MASK GENMASK(5, 4)
  79. #define RCC_D1CCIPR_QSPISRC_SHIFT 4
  80. #define QSPISRC_HCLKD1 0
  81. #define QSPISRC_PLL1_Q_CK 1
  82. #define QSPISRC_PLL2_R_CK 2
  83. #define QSPISRC_PER_CK 3
  84. #define PWR_CR3 0x0c
  85. #define PWR_CR3_SCUEN BIT(2)
  86. #define PWR_D3CR 0x18
  87. #define PWR_D3CR_VOS_MASK GENMASK(15, 14)
  88. #define PWR_D3CR_VOS_SHIFT 14
  89. #define VOS_SCALE_3 1
  90. #define VOS_SCALE_2 2
  91. #define VOS_SCALE_1 3
  92. #define PWR_D3CR_VOSREADY BIT(13)
  93. struct stm32_rcc_regs {
  94. u32 cr; /* 0x00 Source Control Register */
  95. u32 icscr; /* 0x04 Internal Clock Source Calibration Register */
  96. u32 crrcr; /* 0x08 Clock Recovery RC Register */
  97. u32 reserved1; /* 0x0c reserved */
  98. u32 cfgr; /* 0x10 Clock Configuration Register */
  99. u32 reserved2; /* 0x14 reserved */
  100. u32 d1cfgr; /* 0x18 Domain 1 Clock Configuration Register */
  101. u32 d2cfgr; /* 0x1c Domain 2 Clock Configuration Register */
  102. u32 d3cfgr; /* 0x20 Domain 3 Clock Configuration Register */
  103. u32 reserved3; /* 0x24 reserved */
  104. u32 pllckselr; /* 0x28 PLLs Clock Source Selection Register */
  105. u32 pllcfgr; /* 0x2c PLLs Configuration Register */
  106. u32 pll1divr; /* 0x30 PLL1 Dividers Configuration Register */
  107. u32 pll1fracr; /* 0x34 PLL1 Fractional Divider Register */
  108. u32 pll2divr; /* 0x38 PLL2 Dividers Configuration Register */
  109. u32 pll2fracr; /* 0x3c PLL2 Fractional Divider Register */
  110. u32 pll3divr; /* 0x40 PLL3 Dividers Configuration Register */
  111. u32 pll3fracr; /* 0x44 PLL3 Fractional Divider Register */
  112. u32 reserved4; /* 0x48 reserved */
  113. u32 d1ccipr; /* 0x4c Domain 1 Kernel Clock Configuration Register */
  114. u32 d2ccip1r; /* 0x50 Domain 2 Kernel Clock Configuration Register */
  115. u32 d2ccip2r; /* 0x54 Domain 2 Kernel Clock Configuration Register */
  116. u32 d3ccipr; /* 0x58 Domain 3 Kernel Clock Configuration Register */
  117. u32 reserved5; /* 0x5c reserved */
  118. u32 cier; /* 0x60 Clock Source Interrupt Enable Register */
  119. u32 cifr; /* 0x64 Clock Source Interrupt Flag Register */
  120. u32 cicr; /* 0x68 Clock Source Interrupt Clear Register */
  121. u32 reserved6; /* 0x6c reserved */
  122. u32 bdcr; /* 0x70 Backup Domain Control Register */
  123. u32 csr; /* 0x74 Clock Control and Status Register */
  124. u32 reserved7; /* 0x78 reserved */
  125. u32 ahb3rstr; /* 0x7c AHB3 Peripheral Reset Register */
  126. u32 ahb1rstr; /* 0x80 AHB1 Peripheral Reset Register */
  127. u32 ahb2rstr; /* 0x84 AHB2 Peripheral Reset Register */
  128. u32 ahb4rstr; /* 0x88 AHB4 Peripheral Reset Register */
  129. u32 apb3rstr; /* 0x8c APB3 Peripheral Reset Register */
  130. u32 apb1lrstr; /* 0x90 APB1 low Peripheral Reset Register */
  131. u32 apb1hrstr; /* 0x94 APB1 high Peripheral Reset Register */
  132. u32 apb2rstr; /* 0x98 APB2 Clock Register */
  133. u32 apb4rstr; /* 0x9c APB4 Clock Register */
  134. u32 gcr; /* 0xa0 Global Control Register */
  135. u32 reserved8; /* 0xa4 reserved */
  136. u32 d3amr; /* 0xa8 D3 Autonomous mode Register */
  137. u32 reserved9[9];/* 0xac to 0xcc reserved */
  138. u32 rsr; /* 0xd0 Reset Status Register */
  139. u32 ahb3enr; /* 0xd4 AHB3 Clock Register */
  140. u32 ahb1enr; /* 0xd8 AHB1 Clock Register */
  141. u32 ahb2enr; /* 0xdc AHB2 Clock Register */
  142. u32 ahb4enr; /* 0xe0 AHB4 Clock Register */
  143. u32 apb3enr; /* 0xe4 APB3 Clock Register */
  144. u32 apb1lenr; /* 0xe8 APB1 low Clock Register */
  145. u32 apb1henr; /* 0xec APB1 high Clock Register */
  146. u32 apb2enr; /* 0xf0 APB2 Clock Register */
  147. u32 apb4enr; /* 0xf4 APB4 Clock Register */
  148. };
  149. #define RCC_AHB3ENR offsetof(struct stm32_rcc_regs, ahb3enr)
  150. #define RCC_AHB1ENR offsetof(struct stm32_rcc_regs, ahb1enr)
  151. #define RCC_AHB2ENR offsetof(struct stm32_rcc_regs, ahb2enr)
  152. #define RCC_AHB4ENR offsetof(struct stm32_rcc_regs, ahb4enr)
  153. #define RCC_APB3ENR offsetof(struct stm32_rcc_regs, apb3enr)
  154. #define RCC_APB1LENR offsetof(struct stm32_rcc_regs, apb1lenr)
  155. #define RCC_APB1HENR offsetof(struct stm32_rcc_regs, apb1henr)
  156. #define RCC_APB2ENR offsetof(struct stm32_rcc_regs, apb2enr)
  157. #define RCC_APB4ENR offsetof(struct stm32_rcc_regs, apb4enr)
  158. struct clk_cfg {
  159. u32 gate_offset;
  160. u8 gate_bit_idx;
  161. const char *name;
  162. };
  163. /*
  164. * the way all these entries are sorted in this array could seem
  165. * unlogical, but we are dependant of kernel DT_bindings,
  166. * where clocks are separate in 2 banks, peripheral clocks and
  167. * kernel clocks.
  168. */
  169. static const struct clk_cfg clk_map[] = {
  170. {RCC_AHB3ENR, 31, "d1sram1"}, /* peripheral clocks */
  171. {RCC_AHB3ENR, 30, "itcm"},
  172. {RCC_AHB3ENR, 29, "dtcm2"},
  173. {RCC_AHB3ENR, 28, "dtcm1"},
  174. {RCC_AHB3ENR, 8, "flitf"},
  175. {RCC_AHB3ENR, 5, "jpgdec"},
  176. {RCC_AHB3ENR, 4, "dma2d"},
  177. {RCC_AHB3ENR, 0, "mdma"},
  178. {RCC_AHB1ENR, 28, "usb2ulpi"},
  179. {RCC_AHB1ENR, 17, "eth1rx"},
  180. {RCC_AHB1ENR, 16, "eth1tx"},
  181. {RCC_AHB1ENR, 15, "eth1mac"},
  182. {RCC_AHB1ENR, 14, "art"},
  183. {RCC_AHB1ENR, 26, "usb1ulpi"},
  184. {RCC_AHB1ENR, 1, "dma2"},
  185. {RCC_AHB1ENR, 0, "dma1"},
  186. {RCC_AHB2ENR, 31, "d2sram3"},
  187. {RCC_AHB2ENR, 30, "d2sram2"},
  188. {RCC_AHB2ENR, 29, "d2sram1"},
  189. {RCC_AHB2ENR, 5, "hash"},
  190. {RCC_AHB2ENR, 4, "crypt"},
  191. {RCC_AHB2ENR, 0, "camitf"},
  192. {RCC_AHB4ENR, 28, "bkpram"},
  193. {RCC_AHB4ENR, 25, "hsem"},
  194. {RCC_AHB4ENR, 21, "bdma"},
  195. {RCC_AHB4ENR, 19, "crc"},
  196. {RCC_AHB4ENR, 10, "gpiok"},
  197. {RCC_AHB4ENR, 9, "gpioj"},
  198. {RCC_AHB4ENR, 8, "gpioi"},
  199. {RCC_AHB4ENR, 7, "gpioh"},
  200. {RCC_AHB4ENR, 6, "gpiog"},
  201. {RCC_AHB4ENR, 5, "gpiof"},
  202. {RCC_AHB4ENR, 4, "gpioe"},
  203. {RCC_AHB4ENR, 3, "gpiod"},
  204. {RCC_AHB4ENR, 2, "gpioc"},
  205. {RCC_AHB4ENR, 1, "gpiob"},
  206. {RCC_AHB4ENR, 0, "gpioa"},
  207. {RCC_APB3ENR, 6, "wwdg1"},
  208. {RCC_APB1LENR, 29, "dac12"},
  209. {RCC_APB1LENR, 11, "wwdg2"},
  210. {RCC_APB1LENR, 8, "tim14"},
  211. {RCC_APB1LENR, 7, "tim13"},
  212. {RCC_APB1LENR, 6, "tim12"},
  213. {RCC_APB1LENR, 5, "tim7"},
  214. {RCC_APB1LENR, 4, "tim6"},
  215. {RCC_APB1LENR, 3, "tim5"},
  216. {RCC_APB1LENR, 2, "tim4"},
  217. {RCC_APB1LENR, 1, "tim3"},
  218. {RCC_APB1LENR, 0, "tim2"},
  219. {RCC_APB1HENR, 5, "mdios"},
  220. {RCC_APB1HENR, 4, "opamp"},
  221. {RCC_APB1HENR, 1, "crs"},
  222. {RCC_APB2ENR, 18, "tim17"},
  223. {RCC_APB2ENR, 17, "tim16"},
  224. {RCC_APB2ENR, 16, "tim15"},
  225. {RCC_APB2ENR, 1, "tim8"},
  226. {RCC_APB2ENR, 0, "tim1"},
  227. {RCC_APB4ENR, 26, "tmpsens"},
  228. {RCC_APB4ENR, 16, "rtcapb"},
  229. {RCC_APB4ENR, 15, "vref"},
  230. {RCC_APB4ENR, 14, "comp12"},
  231. {RCC_APB4ENR, 1, "syscfg"},
  232. {RCC_AHB3ENR, 16, "sdmmc1"}, /* kernel clocks */
  233. {RCC_AHB3ENR, 14, "quadspi"},
  234. {RCC_AHB3ENR, 12, "fmc"},
  235. {RCC_AHB1ENR, 27, "usb2otg"},
  236. {RCC_AHB1ENR, 25, "usb1otg"},
  237. {RCC_AHB1ENR, 5, "adc12"},
  238. {RCC_AHB2ENR, 9, "sdmmc2"},
  239. {RCC_AHB2ENR, 6, "rng"},
  240. {RCC_AHB4ENR, 24, "adc3"},
  241. {RCC_APB3ENR, 4, "dsi"},
  242. {RCC_APB3ENR, 3, "ltdc"},
  243. {RCC_APB1LENR, 31, "usart8"},
  244. {RCC_APB1LENR, 30, "usart7"},
  245. {RCC_APB1LENR, 27, "hdmicec"},
  246. {RCC_APB1LENR, 23, "i2c3"},
  247. {RCC_APB1LENR, 22, "i2c2"},
  248. {RCC_APB1LENR, 21, "i2c1"},
  249. {RCC_APB1LENR, 20, "uart5"},
  250. {RCC_APB1LENR, 19, "uart4"},
  251. {RCC_APB1LENR, 18, "usart3"},
  252. {RCC_APB1LENR, 17, "usart2"},
  253. {RCC_APB1LENR, 16, "spdifrx"},
  254. {RCC_APB1LENR, 15, "spi3"},
  255. {RCC_APB1LENR, 14, "spi2"},
  256. {RCC_APB1LENR, 9, "lptim1"},
  257. {RCC_APB1HENR, 8, "fdcan"},
  258. {RCC_APB1HENR, 2, "swp"},
  259. {RCC_APB2ENR, 29, "hrtim"},
  260. {RCC_APB2ENR, 28, "dfsdm1"},
  261. {RCC_APB2ENR, 24, "sai3"},
  262. {RCC_APB2ENR, 23, "sai2"},
  263. {RCC_APB2ENR, 22, "sai1"},
  264. {RCC_APB2ENR, 20, "spi5"},
  265. {RCC_APB2ENR, 13, "spi4"},
  266. {RCC_APB2ENR, 12, "spi1"},
  267. {RCC_APB2ENR, 5, "usart6"},
  268. {RCC_APB2ENR, 4, "usart1"},
  269. {RCC_APB4ENR, 21, "sai4a"},
  270. {RCC_APB4ENR, 21, "sai4b"},
  271. {RCC_APB4ENR, 12, "lptim5"},
  272. {RCC_APB4ENR, 11, "lptim4"},
  273. {RCC_APB4ENR, 10, "lptim3"},
  274. {RCC_APB4ENR, 9, "lptim2"},
  275. {RCC_APB4ENR, 7, "i2c4"},
  276. {RCC_APB4ENR, 5, "spi6"},
  277. {RCC_APB4ENR, 3, "lpuart1"},
  278. };
  279. struct stm32_clk {
  280. struct stm32_rcc_regs *rcc_base;
  281. struct regmap *pwr_regmap;
  282. };
  283. struct pll_psc {
  284. u8 divm;
  285. u16 divn;
  286. u8 divp;
  287. u8 divq;
  288. u8 divr;
  289. };
  290. /*
  291. * OSC_HSE = 25 MHz
  292. * VCO = 500MHz
  293. * pll1_p = 250MHz / pll1_q = 250MHz pll1_r = 250Mhz
  294. */
  295. struct pll_psc sys_pll_psc = {
  296. .divm = 4,
  297. .divn = 80,
  298. .divp = 2,
  299. .divq = 2,
  300. .divr = 2,
  301. };
  302. enum apb {
  303. APB1,
  304. APB2,
  305. };
  306. int configure_clocks(struct udevice *dev)
  307. {
  308. struct stm32_clk *priv = dev_get_priv(dev);
  309. struct stm32_rcc_regs *regs = priv->rcc_base;
  310. uint8_t *pwr_base = (uint8_t *)regmap_get_range(priv->pwr_regmap, 0);
  311. uint32_t pllckselr = 0;
  312. uint32_t pll1divr = 0;
  313. uint32_t pllcfgr = 0;
  314. /* Switch on HSI */
  315. setbits_le32(&regs->cr, RCC_CR_HSION);
  316. while (!(readl(&regs->cr) & RCC_CR_HSIRDY))
  317. ;
  318. /* Reset CFGR, now HSI is the default system clock */
  319. writel(0, &regs->cfgr);
  320. /* Set all kernel domain clock registers to reset value*/
  321. writel(0x0, &regs->d1ccipr);
  322. writel(0x0, &regs->d2ccip1r);
  323. writel(0x0, &regs->d2ccip2r);
  324. /* Set voltage scaling at scale 1 (1,15 - 1,26 Volts) */
  325. clrsetbits_le32(pwr_base + PWR_D3CR, PWR_D3CR_VOS_MASK,
  326. VOS_SCALE_1 << PWR_D3CR_VOS_SHIFT);
  327. /* Lock supply configuration update */
  328. clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SCUEN);
  329. while (!(readl(pwr_base + PWR_D3CR) & PWR_D3CR_VOSREADY))
  330. ;
  331. /* disable HSE to configure it */
  332. clrbits_le32(&regs->cr, RCC_CR_HSEON);
  333. while ((readl(&regs->cr) & RCC_CR_HSERDY))
  334. ;
  335. /* clear HSE bypass and set it ON */
  336. clrbits_le32(&regs->cr, RCC_CR_HSEBYP);
  337. /* Switch on HSE */
  338. setbits_le32(&regs->cr, RCC_CR_HSEON);
  339. while (!(readl(&regs->cr) & RCC_CR_HSERDY))
  340. ;
  341. /* pll setup, disable it */
  342. clrbits_le32(&regs->cr, RCC_CR_PLL1ON);
  343. while ((readl(&regs->cr) & RCC_CR_PLL1RDY))
  344. ;
  345. /* Select HSE as PLL clock source */
  346. pllckselr |= RCC_PLLCKSELR_PLLSRC_HSE;
  347. pllckselr |= sys_pll_psc.divm << RCC_PLLCKSELR_DIVM1_SHIFT;
  348. writel(pllckselr, &regs->pllckselr);
  349. pll1divr |= (sys_pll_psc.divr - 1) << RCC_PLL1DIVR_DIVR1_SHIFT;
  350. pll1divr |= (sys_pll_psc.divq - 1) << RCC_PLL1DIVR_DIVQ1_SHIFT;
  351. pll1divr |= (sys_pll_psc.divp - 1) << RCC_PLL1DIVR_DIVP1_SHIFT;
  352. pll1divr |= (sys_pll_psc.divn - 1);
  353. writel(pll1divr, &regs->pll1divr);
  354. pllcfgr |= PLL1RGE_4_8_MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT;
  355. pllcfgr |= RCC_PLLCFGR_DIVP1EN;
  356. pllcfgr |= RCC_PLLCFGR_DIVQ1EN;
  357. pllcfgr |= RCC_PLLCFGR_DIVR1EN;
  358. writel(pllcfgr, &regs->pllcfgr);
  359. /* pll setup, enable it */
  360. setbits_le32(&regs->cr, RCC_CR_PLL1ON);
  361. /* set HPRE (/2) DI clk --> 125MHz */
  362. clrsetbits_le32(&regs->d1cfgr, RCC_D1CFGR_HPRE_MASK,
  363. RCC_D1CFGR_HPRE_DIV2);
  364. /* select PLL1 as system clock source (sys_ck)*/
  365. clrsetbits_le32(&regs->cfgr, RCC_CFGR_SW_MASK, RCC_CFGR_SW_PLL1);
  366. while ((readl(&regs->cfgr) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL1)
  367. ;
  368. /* sdram: use pll1_q as fmc_k clk */
  369. clrsetbits_le32(&regs->d1ccipr, RCC_D1CCIPR_FMCSRC_MASK,
  370. FMCSRC_PLL1_Q_CK);
  371. return 0;
  372. }
  373. static u32 stm32_get_HSI_divider(struct stm32_rcc_regs *regs)
  374. {
  375. u32 divider;
  376. /* get HSI divider value */
  377. divider = readl(&regs->cr) & RCC_CR_HSIDIV_MASK;
  378. divider = divider >> RCC_CR_HSIDIV_SHIFT;
  379. return divider;
  380. };
  381. enum pllsrc {
  382. HSE,
  383. LSE,
  384. HSI,
  385. CSI,
  386. I2S,
  387. TIMER,
  388. PLLSRC_NB,
  389. };
  390. static const char * const pllsrc_name[PLLSRC_NB] = {
  391. [HSE] = "clk-hse",
  392. [LSE] = "clk-lse",
  393. [HSI] = "clk-hsi",
  394. [CSI] = "clk-csi",
  395. [I2S] = "clk-i2s",
  396. [TIMER] = "timer-clk"
  397. };
  398. static ulong stm32_get_rate(struct stm32_rcc_regs *regs, enum pllsrc pllsrc)
  399. {
  400. struct clk clk;
  401. struct udevice *fixed_clock_dev = NULL;
  402. u32 divider;
  403. int ret;
  404. const char *name = pllsrc_name[pllsrc];
  405. debug("%s name %s\n", __func__, name);
  406. clk.id = 0;
  407. ret = uclass_get_device_by_name(UCLASS_CLK, name, &fixed_clock_dev);
  408. if (ret) {
  409. pr_err("Can't find clk %s (%d)", name, ret);
  410. return 0;
  411. }
  412. ret = clk_request(fixed_clock_dev, &clk);
  413. if (ret) {
  414. pr_err("Can't request %s clk (%d)", name, ret);
  415. return 0;
  416. }
  417. divider = 0;
  418. if (pllsrc == HSI)
  419. divider = stm32_get_HSI_divider(regs);
  420. debug("%s divider %d rate %ld\n", __func__,
  421. divider, clk_get_rate(&clk));
  422. return clk_get_rate(&clk) >> divider;
  423. };
  424. enum pll1_output {
  425. PLL1_P_CK,
  426. PLL1_Q_CK,
  427. PLL1_R_CK,
  428. };
  429. static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs,
  430. enum pll1_output output)
  431. {
  432. ulong pllsrc = 0;
  433. u32 divm1, divn1, divp1, divq1, divr1, fracn1;
  434. ulong vco, rate;
  435. /* get the PLLSRC */
  436. switch (readl(&regs->pllckselr) & RCC_PLLCKSELR_PLLSRC_MASK) {
  437. case RCC_PLLCKSELR_PLLSRC_HSI:
  438. pllsrc = stm32_get_rate(regs, HSI);
  439. break;
  440. case RCC_PLLCKSELR_PLLSRC_CSI:
  441. pllsrc = stm32_get_rate(regs, CSI);
  442. break;
  443. case RCC_PLLCKSELR_PLLSRC_HSE:
  444. pllsrc = stm32_get_rate(regs, HSE);
  445. break;
  446. case RCC_PLLCKSELR_PLLSRC_NO_CLK:
  447. /* shouldn't happen */
  448. pr_err("wrong value for RCC_PLLCKSELR register\n");
  449. pllsrc = 0;
  450. break;
  451. }
  452. /* pllsrc = 0 ? no need to go ahead */
  453. if (!pllsrc)
  454. return pllsrc;
  455. /* get divm1, divp1, divn1 and divr1 */
  456. divm1 = readl(&regs->pllckselr) & RCC_PLLCKSELR_DIVM1_MASK;
  457. divm1 = divm1 >> RCC_PLLCKSELR_DIVM1_SHIFT;
  458. divn1 = (readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVN1_MASK) + 1;
  459. divp1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVP1_MASK;
  460. divp1 = (divp1 >> RCC_PLL1DIVR_DIVP1_SHIFT) + 1;
  461. divq1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVQ1_MASK;
  462. divq1 = (divq1 >> RCC_PLL1DIVR_DIVQ1_SHIFT) + 1;
  463. divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK;
  464. divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1;
  465. fracn1 = readl(&regs->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK;
  466. fracn1 = fracn1 & RCC_PLL1DIVR_DIVR1_SHIFT;
  467. vco = (pllsrc / divm1) * divn1;
  468. rate = (pllsrc * fracn1) / (divm1 * 8192);
  469. debug("%s divm1 = %d divn1 = %d divp1 = %d divq1 = %d divr1 = %d\n",
  470. __func__, divm1, divn1, divp1, divq1, divr1);
  471. debug("%s fracn1 = %d vco = %ld rate = %ld\n",
  472. __func__, fracn1, vco, rate);
  473. switch (output) {
  474. case PLL1_P_CK:
  475. return (vco + rate) / divp1;
  476. break;
  477. case PLL1_Q_CK:
  478. return (vco + rate) / divq1;
  479. break;
  480. case PLL1_R_CK:
  481. return (vco + rate) / divr1;
  482. break;
  483. }
  484. return -EINVAL;
  485. }
  486. static u32 stm32_get_apb_psc(struct stm32_rcc_regs *regs, enum apb apb)
  487. {
  488. u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};
  489. u32 d2cfgr = readl(&regs->d2cfgr);
  490. if (apb == APB1) {
  491. if (d2cfgr & RCC_D2CFGR_D2PPRE1_DIVIDED)
  492. /* get D2 domain APB1 prescaler */
  493. return prescaler_table[
  494. ((d2cfgr & RCC_D2CFGR_D2PPRE1_DIVIDER)
  495. >> RCC_D2CFGR_D2PPRE1_SHIFT)];
  496. } else { /* APB2 */
  497. if (d2cfgr & RCC_D2CFGR_D2PPRE2_DIVIDED)
  498. /* get D2 domain APB2 prescaler */
  499. return prescaler_table[
  500. ((d2cfgr & RCC_D2CFGR_D2PPRE2_DIVIDER)
  501. >> RCC_D2CFGR_D2PPRE2_SHIFT)];
  502. }
  503. return 1;
  504. };
  505. static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk,
  506. enum apb apb)
  507. {
  508. struct stm32_rcc_regs *regs = priv->rcc_base;
  509. u32 psc = stm32_get_apb_psc(regs, apb);
  510. if (readl(&regs->cfgr) & RCC_CFGR_TIMPRE)
  511. /*
  512. * if APB prescaler is configured to a
  513. * division factor of 1, 2 or 4
  514. */
  515. switch (psc) {
  516. case 1:
  517. case 2:
  518. case 4:
  519. return sysclk;
  520. case 8:
  521. return sysclk / 2;
  522. case 16:
  523. return sysclk / 4;
  524. default:
  525. pr_err("unexpected prescaler value (%d)\n", psc);
  526. return 0;
  527. }
  528. else
  529. switch (psc) {
  530. case 1:
  531. return sysclk;
  532. case 2:
  533. case 4:
  534. case 8:
  535. case 16:
  536. return sysclk / psc;
  537. default:
  538. pr_err("unexpected prescaler value (%d)\n", psc);
  539. return 0;
  540. }
  541. };
  542. static ulong stm32_clk_get_rate(struct clk *clk)
  543. {
  544. struct stm32_clk *priv = dev_get_priv(clk->dev);
  545. struct stm32_rcc_regs *regs = priv->rcc_base;
  546. ulong sysclk = 0;
  547. u32 gate_offset;
  548. u32 d1cfgr, d3cfgr;
  549. /* prescaler table lookups for clock computation */
  550. u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};
  551. u8 source, idx;
  552. /*
  553. * get system clock (sys_ck) source
  554. * can be HSI_CK, CSI_CK, HSE_CK or pll1_p_ck
  555. */
  556. source = readl(&regs->cfgr) & RCC_CFGR_SW_MASK;
  557. switch (source) {
  558. case RCC_CFGR_SW_PLL1:
  559. sysclk = stm32_get_PLL1_rate(regs, PLL1_P_CK);
  560. break;
  561. case RCC_CFGR_SW_HSE:
  562. sysclk = stm32_get_rate(regs, HSE);
  563. break;
  564. case RCC_CFGR_SW_CSI:
  565. sysclk = stm32_get_rate(regs, CSI);
  566. break;
  567. case RCC_CFGR_SW_HSI:
  568. sysclk = stm32_get_rate(regs, HSI);
  569. break;
  570. }
  571. /* sysclk = 0 ? no need to go ahead */
  572. if (!sysclk)
  573. return sysclk;
  574. debug("%s system clock: source = %d freq = %ld\n",
  575. __func__, source, sysclk);
  576. d1cfgr = readl(&regs->d1cfgr);
  577. if (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDED) {
  578. /* get D1 domain Core prescaler */
  579. idx = (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDER) >>
  580. RCC_D1CFGR_D1CPRE_SHIFT;
  581. sysclk = sysclk / prescaler_table[idx];
  582. }
  583. if (d1cfgr & RCC_D1CFGR_HPRE_DIVIDED) {
  584. /* get D1 domain AHB prescaler */
  585. idx = d1cfgr & RCC_D1CFGR_HPRE_DIVIDER;
  586. sysclk = sysclk / prescaler_table[idx];
  587. }
  588. gate_offset = clk_map[clk->id].gate_offset;
  589. debug("%s clk->id=%ld gate_offset=0x%x sysclk=%ld\n",
  590. __func__, clk->id, gate_offset, sysclk);
  591. switch (gate_offset) {
  592. case RCC_AHB3ENR:
  593. case RCC_AHB1ENR:
  594. case RCC_AHB2ENR:
  595. case RCC_AHB4ENR:
  596. return sysclk;
  597. break;
  598. case RCC_APB3ENR:
  599. if (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDED) {
  600. /* get D1 domain APB3 prescaler */
  601. idx = (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDER) >>
  602. RCC_D1CFGR_D1PPRE_SHIFT;
  603. sysclk = sysclk / prescaler_table[idx];
  604. }
  605. debug("%s system clock: freq after APB3 prescaler = %ld\n",
  606. __func__, sysclk);
  607. return sysclk;
  608. break;
  609. case RCC_APB4ENR:
  610. d3cfgr = readl(&regs->d3cfgr);
  611. if (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
  612. /* get D3 domain APB4 prescaler */
  613. idx = (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
  614. RCC_D3CFGR_D3PPRE_SHIFT;
  615. sysclk = sysclk / prescaler_table[idx];
  616. }
  617. debug("%s system clock: freq after APB4 prescaler = %ld\n",
  618. __func__, sysclk);
  619. return sysclk;
  620. break;
  621. case RCC_APB1LENR:
  622. case RCC_APB1HENR:
  623. /* special case for GPT timers */
  624. switch (clk->id) {
  625. case TIM14_CK:
  626. case TIM13_CK:
  627. case TIM12_CK:
  628. case TIM7_CK:
  629. case TIM6_CK:
  630. case TIM5_CK:
  631. case TIM4_CK:
  632. case TIM3_CK:
  633. case TIM2_CK:
  634. return stm32_get_timer_rate(priv, sysclk, APB1);
  635. }
  636. debug("%s system clock: freq after APB1 prescaler = %ld\n",
  637. __func__, sysclk);
  638. return (sysclk / stm32_get_apb_psc(regs, APB1));
  639. break;
  640. case RCC_APB2ENR:
  641. /* special case for timers */
  642. switch (clk->id) {
  643. case TIM17_CK:
  644. case TIM16_CK:
  645. case TIM15_CK:
  646. case TIM8_CK:
  647. case TIM1_CK:
  648. return stm32_get_timer_rate(priv, sysclk, APB2);
  649. }
  650. debug("%s system clock: freq after APB2 prescaler = %ld\n",
  651. __func__, sysclk);
  652. return (sysclk / stm32_get_apb_psc(regs, APB2));
  653. break;
  654. default:
  655. pr_err("unexpected gate_offset value (0x%x)\n", gate_offset);
  656. return -EINVAL;
  657. break;
  658. }
  659. }
  660. static int stm32_clk_enable(struct clk *clk)
  661. {
  662. struct stm32_clk *priv = dev_get_priv(clk->dev);
  663. struct stm32_rcc_regs *regs = priv->rcc_base;
  664. u32 gate_offset;
  665. u32 gate_bit_index;
  666. unsigned long clk_id = clk->id;
  667. gate_offset = clk_map[clk_id].gate_offset;
  668. gate_bit_index = clk_map[clk_id].gate_bit_idx;
  669. debug("%s: clkid=%ld gate offset=0x%x bit_index=%d name=%s\n",
  670. __func__, clk->id, gate_offset, gate_bit_index,
  671. clk_map[clk_id].name);
  672. setbits_le32(&regs->cr + (gate_offset / 4), BIT(gate_bit_index));
  673. return 0;
  674. }
  675. static int stm32_clk_probe(struct udevice *dev)
  676. {
  677. struct stm32_clk *priv = dev_get_priv(dev);
  678. struct udevice *syscon;
  679. fdt_addr_t addr;
  680. int err;
  681. addr = dev_read_addr(dev);
  682. if (addr == FDT_ADDR_T_NONE)
  683. return -EINVAL;
  684. priv->rcc_base = (struct stm32_rcc_regs *)addr;
  685. /* get corresponding syscon phandle */
  686. err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
  687. "st,syscfg", &syscon);
  688. if (err) {
  689. pr_err("unable to find syscon device\n");
  690. return err;
  691. }
  692. priv->pwr_regmap = syscon_get_regmap(syscon);
  693. if (!priv->pwr_regmap) {
  694. pr_err("unable to find regmap\n");
  695. return -ENODEV;
  696. }
  697. configure_clocks(dev);
  698. return 0;
  699. }
  700. static int stm32_clk_of_xlate(struct clk *clk,
  701. struct ofnode_phandle_args *args)
  702. {
  703. if (args->args_count != 1) {
  704. debug("Invaild args_count: %d\n", args->args_count);
  705. return -EINVAL;
  706. }
  707. if (args->args_count) {
  708. clk->id = args->args[0];
  709. /*
  710. * this computation convert DT clock index which is used to
  711. * point into 2 separate clock arrays (peripheral and kernel
  712. * clocks bank) (see include/dt-bindings/clock/stm32h7-clks.h)
  713. * into index to point into only one array where peripheral
  714. * and kernel clocks are consecutive
  715. */
  716. if (clk->id >= KERN_BANK) {
  717. clk->id -= KERN_BANK;
  718. clk->id += LAST_PERIF_BANK - PERIF_BANK + 1;
  719. } else {
  720. clk->id -= PERIF_BANK;
  721. }
  722. } else {
  723. clk->id = 0;
  724. }
  725. debug("%s clk->id %ld\n", __func__, clk->id);
  726. return 0;
  727. }
  728. static struct clk_ops stm32_clk_ops = {
  729. .of_xlate = stm32_clk_of_xlate,
  730. .enable = stm32_clk_enable,
  731. .get_rate = stm32_clk_get_rate,
  732. };
  733. U_BOOT_DRIVER(stm32h7_clk) = {
  734. .name = "stm32h7_rcc_clock",
  735. .id = UCLASS_CLK,
  736. .ops = &stm32_clk_ops,
  737. .probe = stm32_clk_probe,
  738. .priv_auto_alloc_size = sizeof(struct stm32_clk),
  739. .flags = DM_FLAG_PRE_RELOC,
  740. };