clk-hsdk-cgu.c 20 KB

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  1. /*
  2. * Synopsys HSDK SDP CGU clock driver
  3. *
  4. * Copyright (C) 2017 Synopsys
  5. * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <common.h>
  12. #include <clk-uclass.h>
  13. #include <div64.h>
  14. #include <dm.h>
  15. #include <linux/io.h>
  16. /*
  17. * Synopsys ARC HSDK clock tree.
  18. *
  19. * ------------------
  20. * | 33.33 MHz xtal |
  21. * ------------------
  22. * |
  23. * | -----------
  24. * |-->| ARC PLL |
  25. * | -----------
  26. * | |
  27. * | |-->|CGU_ARC_IDIV|----------->
  28. * | |-->|CREG_CORE_IF_DIV|------->
  29. * |
  30. * | --------------
  31. * |-->| SYSTEM PLL |
  32. * | --------------
  33. * | |
  34. * | |-->|CGU_SYS_IDIV_APB|------->
  35. * | |-->|CGU_SYS_IDIV_AXI|------->
  36. * | |-->|CGU_SYS_IDIV_*|--------->
  37. * | |-->|CGU_SYS_IDIV_EBI_REF|--->
  38. * |
  39. * | --------------
  40. * |-->| TUNNEL PLL |
  41. * | --------------
  42. * | |
  43. * | |-->|CGU_TUN_IDIV_TUN|----------->
  44. * | |-->|CGU_TUN_IDIV_ROM|----------->
  45. * | |-->|CGU_TUN_IDIV_PWM|----------->
  46. * |
  47. * | -----------
  48. * |-->| DDR PLL |
  49. * -----------
  50. * |
  51. * |---------------------------->
  52. *
  53. * ------------------
  54. * | 27.00 MHz xtal |
  55. * ------------------
  56. * |
  57. * | ------------
  58. * |-->| HDMI PLL |
  59. * ------------
  60. * |
  61. * |-->|CGU_HDMI_IDIV_APB|------>
  62. */
  63. #define CGU_ARC_IDIV 0x080
  64. #define CGU_TUN_IDIV_TUN 0x380
  65. #define CGU_TUN_IDIV_ROM 0x390
  66. #define CGU_TUN_IDIV_PWM 0x3A0
  67. #define CGU_TUN_IDIV_TIMER 0x3B0
  68. #define CGU_HDMI_IDIV_APB 0x480
  69. #define CGU_SYS_IDIV_APB 0x180
  70. #define CGU_SYS_IDIV_AXI 0x190
  71. #define CGU_SYS_IDIV_ETH 0x1A0
  72. #define CGU_SYS_IDIV_USB 0x1B0
  73. #define CGU_SYS_IDIV_SDIO 0x1C0
  74. #define CGU_SYS_IDIV_HDMI 0x1D0
  75. #define CGU_SYS_IDIV_GFX_CORE 0x1E0
  76. #define CGU_SYS_IDIV_GFX_DMA 0x1F0
  77. #define CGU_SYS_IDIV_GFX_CFG 0x200
  78. #define CGU_SYS_IDIV_DMAC_CORE 0x210
  79. #define CGU_SYS_IDIV_DMAC_CFG 0x220
  80. #define CGU_SYS_IDIV_SDIO_REF 0x230
  81. #define CGU_SYS_IDIV_SPI_REF 0x240
  82. #define CGU_SYS_IDIV_I2C_REF 0x250
  83. #define CGU_SYS_IDIV_UART_REF 0x260
  84. #define CGU_SYS_IDIV_EBI_REF 0x270
  85. #define CGU_IDIV_MASK 0xFF /* All idiv have 8 significant bits */
  86. #define CGU_ARC_PLL 0x0
  87. #define CGU_SYS_PLL 0x10
  88. #define CGU_DDR_PLL 0x20
  89. #define CGU_TUN_PLL 0x30
  90. #define CGU_HDMI_PLL 0x40
  91. #define CGU_PLL_CTRL 0x000 /* ARC PLL control register */
  92. #define CGU_PLL_STATUS 0x004 /* ARC PLL status register */
  93. #define CGU_PLL_FMEAS 0x008 /* ARC PLL frequency measurement register */
  94. #define CGU_PLL_MON 0x00C /* ARC PLL monitor register */
  95. #define CGU_PLL_CTRL_ODIV_SHIFT 2
  96. #define CGU_PLL_CTRL_IDIV_SHIFT 4
  97. #define CGU_PLL_CTRL_FBDIV_SHIFT 9
  98. #define CGU_PLL_CTRL_BAND_SHIFT 20
  99. #define CGU_PLL_CTRL_ODIV_MASK GENMASK(3, CGU_PLL_CTRL_ODIV_SHIFT)
  100. #define CGU_PLL_CTRL_IDIV_MASK GENMASK(8, CGU_PLL_CTRL_IDIV_SHIFT)
  101. #define CGU_PLL_CTRL_FBDIV_MASK GENMASK(15, CGU_PLL_CTRL_FBDIV_SHIFT)
  102. #define CGU_PLL_CTRL_PD BIT(0)
  103. #define CGU_PLL_CTRL_BYPASS BIT(1)
  104. #define CGU_PLL_STATUS_LOCK BIT(0)
  105. #define CGU_PLL_STATUS_ERR BIT(1)
  106. #define HSDK_PLL_MAX_LOCK_TIME 100 /* 100 us */
  107. #define CREG_CORE_IF_DIV 0x000 /* ARC CORE interface divider */
  108. #define CORE_IF_CLK_THRESHOLD_HZ 500000000
  109. #define CREG_CORE_IF_CLK_DIV_1 0x0
  110. #define CREG_CORE_IF_CLK_DIV_2 0x1
  111. #define MIN_PLL_RATE 100000000 /* 100 MHz */
  112. #define PARENT_RATE_33 33333333 /* fixed clock - xtal */
  113. #define PARENT_RATE_27 27000000 /* fixed clock - xtal */
  114. #define CGU_MAX_CLOCKS 27
  115. #define CGU_SYS_CLOCKS 16
  116. #define MAX_AXI_CLOCKS 4
  117. #define CGU_TUN_CLOCKS 4
  118. #define MAX_TUN_CLOCKS 6
  119. struct hsdk_tun_idiv_cfg {
  120. u32 oft;
  121. u8 val[MAX_TUN_CLOCKS];
  122. };
  123. struct hsdk_tun_clk_cfg {
  124. const u32 clk_rate[MAX_TUN_CLOCKS];
  125. const u32 pll_rate[MAX_TUN_CLOCKS];
  126. const struct hsdk_tun_idiv_cfg idiv[CGU_TUN_CLOCKS];
  127. };
  128. static const struct hsdk_tun_clk_cfg tun_clk_cfg = {
  129. { 25000000, 50000000, 75000000, 100000000, 125000000, 150000000 },
  130. { 600000000, 600000000, 600000000, 600000000, 750000000, 600000000 }, {
  131. { CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } },
  132. { CGU_TUN_IDIV_ROM, { 4, 4, 4, 4, 5, 4 } },
  133. { CGU_TUN_IDIV_PWM, { 8, 8, 8, 8, 10, 8 } },
  134. { CGU_TUN_IDIV_TIMER, { 12, 12, 12, 12, 15, 12 } }
  135. }
  136. };
  137. struct hsdk_sys_idiv_cfg {
  138. u32 oft;
  139. u8 val[MAX_AXI_CLOCKS];
  140. };
  141. struct hsdk_axi_clk_cfg {
  142. const u32 clk_rate[MAX_AXI_CLOCKS];
  143. const u32 pll_rate[MAX_AXI_CLOCKS];
  144. const struct hsdk_sys_idiv_cfg idiv[CGU_SYS_CLOCKS];
  145. };
  146. static const struct hsdk_axi_clk_cfg axi_clk_cfg = {
  147. { 200000000, 400000000, 600000000, 800000000 },
  148. { 800000000, 800000000, 600000000, 800000000 }, {
  149. { CGU_SYS_IDIV_APB, { 4, 4, 3, 4 } }, /* APB */
  150. { CGU_SYS_IDIV_AXI, { 4, 2, 1, 1 } }, /* AXI */
  151. { CGU_SYS_IDIV_ETH, { 2, 2, 2, 2 } }, /* ETH */
  152. { CGU_SYS_IDIV_USB, { 2, 2, 2, 2 } }, /* USB */
  153. { CGU_SYS_IDIV_SDIO, { 2, 2, 2, 2 } }, /* SDIO */
  154. { CGU_SYS_IDIV_HDMI, { 2, 2, 2, 2 } }, /* HDMI */
  155. { CGU_SYS_IDIV_GFX_CORE, { 1, 1, 1, 1 } }, /* GPU-CORE */
  156. { CGU_SYS_IDIV_GFX_DMA, { 2, 2, 2, 2 } }, /* GPU-DMA */
  157. { CGU_SYS_IDIV_GFX_CFG, { 4, 4, 3, 4 } }, /* GPU-CFG */
  158. { CGU_SYS_IDIV_DMAC_CORE,{ 2, 2, 2, 2 } }, /* DMAC-CORE */
  159. { CGU_SYS_IDIV_DMAC_CFG, { 4, 4, 3, 4 } }, /* DMAC-CFG */
  160. { CGU_SYS_IDIV_SDIO_REF, { 8, 8, 6, 8 } }, /* SDIO-REF */
  161. { CGU_SYS_IDIV_SPI_REF, { 24, 24, 18, 24 } }, /* SPI-REF */
  162. { CGU_SYS_IDIV_I2C_REF, { 4, 4, 3, 4 } }, /* I2C-REF */
  163. { CGU_SYS_IDIV_UART_REF, { 24, 24, 18, 24 } }, /* UART-REF */
  164. { CGU_SYS_IDIV_EBI_REF, { 16, 16, 12, 16 } } /* EBI-REF */
  165. }
  166. };
  167. struct hsdk_pll_cfg {
  168. u32 rate;
  169. u32 idiv;
  170. u32 fbdiv;
  171. u32 odiv;
  172. u32 band;
  173. };
  174. static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
  175. { 100000000, 0, 11, 3, 0 },
  176. { 125000000, 0, 14, 3, 0 },
  177. { 133000000, 0, 15, 3, 0 },
  178. { 150000000, 0, 17, 3, 0 },
  179. { 200000000, 1, 47, 3, 0 },
  180. { 233000000, 1, 27, 2, 0 },
  181. { 300000000, 1, 35, 2, 0 },
  182. { 333000000, 1, 39, 2, 0 },
  183. { 400000000, 1, 47, 2, 0 },
  184. { 500000000, 0, 14, 1, 0 },
  185. { 600000000, 0, 17, 1, 0 },
  186. { 700000000, 0, 20, 1, 0 },
  187. { 750000000, 1, 44, 1, 0 },
  188. { 800000000, 0, 23, 1, 0 },
  189. { 900000000, 1, 26, 0, 0 },
  190. { 1000000000, 1, 29, 0, 0 },
  191. { 1100000000, 1, 32, 0, 0 },
  192. { 1200000000, 1, 35, 0, 0 },
  193. { 1300000000, 1, 38, 0, 0 },
  194. { 1400000000, 1, 41, 0, 0 },
  195. { 1500000000, 1, 44, 0, 0 },
  196. { 1600000000, 1, 47, 0, 0 },
  197. {}
  198. };
  199. static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
  200. { 297000000, 0, 21, 2, 0 },
  201. { 540000000, 0, 19, 1, 0 },
  202. { 594000000, 0, 21, 1, 0 },
  203. {}
  204. };
  205. struct hsdk_cgu_clk {
  206. /* CGU block register */
  207. void __iomem *cgu_regs;
  208. /* CREG block register */
  209. void __iomem *creg_regs;
  210. /* PLLs registers */
  211. void __iomem *regs;
  212. /* PLLs special registers */
  213. void __iomem *spec_regs;
  214. /* PLLs devdata */
  215. const struct hsdk_pll_devdata *pll_devdata;
  216. /* Dividers registers */
  217. void __iomem *idiv_regs;
  218. };
  219. struct hsdk_pll_devdata {
  220. const u32 parent_rate;
  221. const struct hsdk_pll_cfg *pll_cfg;
  222. int (*update_rate)(struct hsdk_cgu_clk *clk, unsigned long rate,
  223. const struct hsdk_pll_cfg *cfg);
  224. };
  225. static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *, unsigned long,
  226. const struct hsdk_pll_cfg *);
  227. static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *, unsigned long,
  228. const struct hsdk_pll_cfg *);
  229. static const struct hsdk_pll_devdata core_pll_dat = {
  230. .parent_rate = PARENT_RATE_33,
  231. .pll_cfg = asdt_pll_cfg,
  232. .update_rate = hsdk_pll_core_update_rate,
  233. };
  234. static const struct hsdk_pll_devdata sdt_pll_dat = {
  235. .parent_rate = PARENT_RATE_33,
  236. .pll_cfg = asdt_pll_cfg,
  237. .update_rate = hsdk_pll_comm_update_rate,
  238. };
  239. static const struct hsdk_pll_devdata hdmi_pll_dat = {
  240. .parent_rate = PARENT_RATE_27,
  241. .pll_cfg = hdmi_pll_cfg,
  242. .update_rate = hsdk_pll_comm_update_rate,
  243. };
  244. static ulong idiv_set(struct clk *, ulong);
  245. static ulong cpu_clk_set(struct clk *, ulong);
  246. static ulong axi_clk_set(struct clk *, ulong);
  247. static ulong tun_clk_set(struct clk *, ulong);
  248. static ulong idiv_get(struct clk *);
  249. static int idiv_off(struct clk *);
  250. static ulong pll_set(struct clk *, ulong);
  251. static ulong pll_get(struct clk *);
  252. struct hsdk_cgu_clock_map {
  253. u32 cgu_pll_oft;
  254. u32 creg_div_oft;
  255. u32 cgu_div_oft;
  256. const struct hsdk_pll_devdata *pll_devdata;
  257. ulong (*get_rate)(struct clk *clk);
  258. ulong (*set_rate)(struct clk *clk, ulong rate);
  259. int (*disable)(struct clk *clk);
  260. };
  261. static const struct hsdk_cgu_clock_map clock_map[] = {
  262. { CGU_ARC_PLL, 0, 0, &core_pll_dat, pll_get, pll_set, NULL },
  263. { CGU_ARC_PLL, 0, CGU_ARC_IDIV, &core_pll_dat, idiv_get, cpu_clk_set, idiv_off },
  264. { CGU_DDR_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
  265. { CGU_SYS_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
  266. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_APB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  267. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, axi_clk_set, idiv_off },
  268. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_ETH, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  269. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_USB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  270. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  271. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_HDMI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  272. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  273. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_DMA, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  274. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  275. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_DMAC_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  276. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_DMAC_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  277. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  278. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SPI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  279. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_I2C_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  280. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_UART_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  281. { CGU_SYS_PLL, 0, CGU_SYS_IDIV_EBI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  282. { CGU_TUN_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
  283. { CGU_TUN_PLL, 0, CGU_TUN_IDIV_TUN, &sdt_pll_dat, idiv_get, tun_clk_set, idiv_off },
  284. { CGU_TUN_PLL, 0, CGU_TUN_IDIV_ROM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  285. { CGU_TUN_PLL, 0, CGU_TUN_IDIV_PWM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  286. { CGU_TUN_PLL, 0, CGU_TUN_IDIV_TIMER, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
  287. { CGU_HDMI_PLL, 0, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
  288. { CGU_HDMI_PLL, 0, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get, idiv_set, idiv_off }
  289. };
  290. static inline void hsdk_idiv_write(struct hsdk_cgu_clk *clk, u32 val)
  291. {
  292. iowrite32(val, clk->idiv_regs);
  293. }
  294. static inline u32 hsdk_idiv_read(struct hsdk_cgu_clk *clk)
  295. {
  296. return ioread32(clk->idiv_regs);
  297. }
  298. static inline void hsdk_pll_write(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
  299. {
  300. iowrite32(val, clk->regs + reg);
  301. }
  302. static inline u32 hsdk_pll_read(struct hsdk_cgu_clk *clk, u32 reg)
  303. {
  304. return ioread32(clk->regs + reg);
  305. }
  306. static inline void hsdk_pll_spcwrite(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
  307. {
  308. iowrite32(val, clk->spec_regs + reg);
  309. }
  310. static inline u32 hsdk_pll_spcread(struct hsdk_cgu_clk *clk, u32 reg)
  311. {
  312. return ioread32(clk->spec_regs + reg);
  313. }
  314. static inline void hsdk_pll_set_cfg(struct hsdk_cgu_clk *clk,
  315. const struct hsdk_pll_cfg *cfg)
  316. {
  317. u32 val = 0;
  318. /* Powerdown and Bypass bits should be cleared */
  319. val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
  320. val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
  321. val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
  322. val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
  323. pr_debug("write configurarion: %#x\n", val);
  324. hsdk_pll_write(clk, CGU_PLL_CTRL, val);
  325. }
  326. static inline bool hsdk_pll_is_locked(struct hsdk_cgu_clk *clk)
  327. {
  328. return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK);
  329. }
  330. static inline bool hsdk_pll_is_err(struct hsdk_cgu_clk *clk)
  331. {
  332. return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR);
  333. }
  334. static ulong pll_get(struct clk *sclk)
  335. {
  336. u32 val;
  337. u64 rate;
  338. u32 idiv, fbdiv, odiv;
  339. struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
  340. u32 parent_rate = clk->pll_devdata->parent_rate;
  341. val = hsdk_pll_read(clk, CGU_PLL_CTRL);
  342. pr_debug("current configurarion: %#x\n", val);
  343. /* Check if PLL is bypassed */
  344. if (val & CGU_PLL_CTRL_BYPASS)
  345. return parent_rate;
  346. /* Check if PLL is disabled */
  347. if (val & CGU_PLL_CTRL_PD)
  348. return 0;
  349. /* input divider = reg.idiv + 1 */
  350. idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
  351. /* fb divider = 2*(reg.fbdiv + 1) */
  352. fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT));
  353. /* output divider = 2^(reg.odiv) */
  354. odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT);
  355. rate = (u64)parent_rate * fbdiv;
  356. do_div(rate, idiv * odiv);
  357. return rate;
  358. }
  359. static unsigned long hsdk_pll_round_rate(struct clk *sclk, unsigned long rate)
  360. {
  361. int i;
  362. unsigned long best_rate;
  363. struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
  364. const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
  365. if (pll_cfg[0].rate == 0)
  366. return -EINVAL;
  367. best_rate = pll_cfg[0].rate;
  368. for (i = 1; pll_cfg[i].rate != 0; i++) {
  369. if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
  370. best_rate = pll_cfg[i].rate;
  371. }
  372. pr_debug("chosen best rate: %lu\n", best_rate);
  373. return best_rate;
  374. }
  375. static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *clk,
  376. unsigned long rate,
  377. const struct hsdk_pll_cfg *cfg)
  378. {
  379. hsdk_pll_set_cfg(clk, cfg);
  380. /*
  381. * Wait until CGU relocks and check error status.
  382. * If after timeout CGU is unlocked yet return error.
  383. */
  384. udelay(HSDK_PLL_MAX_LOCK_TIME);
  385. if (!hsdk_pll_is_locked(clk))
  386. return -ETIMEDOUT;
  387. if (hsdk_pll_is_err(clk))
  388. return -EINVAL;
  389. return 0;
  390. }
  391. static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *clk,
  392. unsigned long rate,
  393. const struct hsdk_pll_cfg *cfg)
  394. {
  395. /*
  396. * When core clock exceeds 500MHz, the divider for the interface
  397. * clock must be programmed to div-by-2.
  398. */
  399. if (rate > CORE_IF_CLK_THRESHOLD_HZ)
  400. hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_2);
  401. hsdk_pll_set_cfg(clk, cfg);
  402. /*
  403. * Wait until CGU relocks and check error status.
  404. * If after timeout CGU is unlocked yet return error.
  405. */
  406. udelay(HSDK_PLL_MAX_LOCK_TIME);
  407. if (!hsdk_pll_is_locked(clk))
  408. return -ETIMEDOUT;
  409. if (hsdk_pll_is_err(clk))
  410. return -EINVAL;
  411. /*
  412. * Program divider to div-by-1 if we succesfuly set core clock below
  413. * 500MHz threshold.
  414. */
  415. if (rate <= CORE_IF_CLK_THRESHOLD_HZ)
  416. hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_1);
  417. return 0;
  418. }
  419. static ulong pll_set(struct clk *sclk, ulong rate)
  420. {
  421. int i;
  422. unsigned long best_rate;
  423. struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
  424. const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
  425. best_rate = hsdk_pll_round_rate(sclk, rate);
  426. for (i = 0; pll_cfg[i].rate != 0; i++) {
  427. if (pll_cfg[i].rate == best_rate) {
  428. return clk->pll_devdata->update_rate(clk, best_rate,
  429. &pll_cfg[i]);
  430. }
  431. }
  432. pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate,
  433. clk->pll_devdata->parent_rate);
  434. return -EINVAL;
  435. }
  436. static int idiv_off(struct clk *sclk)
  437. {
  438. struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
  439. hsdk_idiv_write(clk, 0);
  440. return 0;
  441. }
  442. static ulong idiv_get(struct clk *sclk)
  443. {
  444. struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
  445. ulong parent_rate = pll_get(sclk);
  446. u32 div_factor = hsdk_idiv_read(clk);
  447. div_factor &= CGU_IDIV_MASK;
  448. pr_debug("current configurarion: %#x (%d)\n", div_factor, div_factor);
  449. if (div_factor == 0)
  450. return 0;
  451. return parent_rate / div_factor;
  452. }
  453. /* Special behavior: wen we set this clock we set both idiv and pll */
  454. static ulong cpu_clk_set(struct clk *sclk, ulong rate)
  455. {
  456. ulong ret;
  457. ret = pll_set(sclk, rate);
  458. idiv_set(sclk, rate);
  459. return ret;
  460. }
  461. /* Special behavior: wen we set this clock we set both idiv and pll and all pll dividers */
  462. static ulong axi_clk_set(struct clk *sclk, ulong rate)
  463. {
  464. struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
  465. ulong pll_rate;
  466. int i, freq_idx = -1;
  467. ulong ret = 0;
  468. pll_rate = pll_get(sclk);
  469. for (i = 0; i < MAX_AXI_CLOCKS; i++) {
  470. if (axi_clk_cfg.clk_rate[i] == rate) {
  471. freq_idx = i;
  472. break;
  473. }
  474. }
  475. if (freq_idx < 0) {
  476. pr_err("axi clk: invalid rate=%ld Hz\n", rate);
  477. return -EINVAL;
  478. }
  479. /* configure PLL before dividers */
  480. if (axi_clk_cfg.pll_rate[freq_idx] < pll_rate)
  481. ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]);
  482. /* configure SYS dividers */
  483. for (i = 0; i < CGU_SYS_CLOCKS; i++) {
  484. clk->idiv_regs = clk->cgu_regs + axi_clk_cfg.idiv[i].oft;
  485. hsdk_idiv_write(clk, axi_clk_cfg.idiv[i].val[freq_idx]);
  486. }
  487. /* configure PLL after dividers */
  488. if (axi_clk_cfg.pll_rate[freq_idx] >= pll_rate)
  489. ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]);
  490. return ret;
  491. }
  492. static ulong tun_clk_set(struct clk *sclk, ulong rate)
  493. {
  494. struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
  495. ulong pll_rate;
  496. int i, freq_idx = -1;
  497. ulong ret = 0;
  498. pll_rate = pll_get(sclk);
  499. for (i = 0; i < MAX_TUN_CLOCKS; i++) {
  500. if (tun_clk_cfg.clk_rate[i] == rate) {
  501. freq_idx = i;
  502. break;
  503. }
  504. }
  505. if (freq_idx < 0) {
  506. pr_err("tun clk: invalid rate=%ld Hz\n", rate);
  507. return -EINVAL;
  508. }
  509. /* configure PLL before dividers */
  510. if (tun_clk_cfg.pll_rate[freq_idx] < pll_rate)
  511. ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]);
  512. /* configure SYS dividers */
  513. for (i = 0; i < CGU_TUN_CLOCKS; i++) {
  514. clk->idiv_regs = clk->cgu_regs + tun_clk_cfg.idiv[i].oft;
  515. hsdk_idiv_write(clk, tun_clk_cfg.idiv[i].val[freq_idx]);
  516. }
  517. /* configure PLL after dividers */
  518. if (tun_clk_cfg.pll_rate[freq_idx] >= pll_rate)
  519. ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]);
  520. return ret;
  521. }
  522. static ulong idiv_set(struct clk *sclk, ulong rate)
  523. {
  524. struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
  525. ulong parent_rate = pll_get(sclk);
  526. u32 div_factor;
  527. div_factor = parent_rate / rate;
  528. if (abs(rate - parent_rate / (div_factor + 1)) <=
  529. abs(rate - parent_rate / div_factor)) {
  530. div_factor += 1;
  531. }
  532. if (div_factor & ~CGU_IDIV_MASK) {
  533. pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: max divider valie is%d\n",
  534. rate, parent_rate, div_factor, CGU_IDIV_MASK);
  535. div_factor = CGU_IDIV_MASK;
  536. }
  537. if (div_factor == 0) {
  538. pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: min divider valie is 1\n",
  539. rate, parent_rate, div_factor);
  540. div_factor = 1;
  541. }
  542. hsdk_idiv_write(clk, div_factor);
  543. return 0;
  544. }
  545. static int hsdk_prepare_clock_tree_branch(struct clk *sclk)
  546. {
  547. struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
  548. if (sclk->id >= CGU_MAX_CLOCKS)
  549. return -EINVAL;
  550. clk->pll_devdata = clock_map[sclk->id].pll_devdata;
  551. clk->regs = clk->cgu_regs + clock_map[sclk->id].cgu_pll_oft;
  552. clk->spec_regs = clk->creg_regs + clock_map[sclk->id].creg_div_oft;
  553. clk->idiv_regs = clk->cgu_regs + clock_map[sclk->id].cgu_div_oft;
  554. return 0;
  555. }
  556. static ulong hsdk_cgu_get_rate(struct clk *sclk)
  557. {
  558. if (hsdk_prepare_clock_tree_branch(sclk))
  559. return -EINVAL;
  560. return clock_map[sclk->id].get_rate(sclk);
  561. }
  562. static ulong hsdk_cgu_set_rate(struct clk *sclk, ulong rate)
  563. {
  564. if (hsdk_prepare_clock_tree_branch(sclk))
  565. return -EINVAL;
  566. return clock_map[sclk->id].set_rate(sclk, rate);
  567. }
  568. static int hsdk_cgu_disable(struct clk *sclk)
  569. {
  570. if (hsdk_prepare_clock_tree_branch(sclk))
  571. return -EINVAL;
  572. if (clock_map[sclk->id].disable)
  573. return clock_map[sclk->id].disable(sclk);
  574. return -ENOTSUPP;
  575. }
  576. static const struct clk_ops hsdk_cgu_ops = {
  577. .set_rate = hsdk_cgu_set_rate,
  578. .get_rate = hsdk_cgu_get_rate,
  579. .disable = hsdk_cgu_disable,
  580. };
  581. static int hsdk_cgu_clk_probe(struct udevice *dev)
  582. {
  583. struct hsdk_cgu_clk *pll_clk = dev_get_priv(dev);
  584. BUILD_BUG_ON(ARRAY_SIZE(clock_map) != CGU_MAX_CLOCKS);
  585. pll_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index(dev, 0);
  586. if (!pll_clk->cgu_regs)
  587. return -EINVAL;
  588. pll_clk->creg_regs = (void __iomem *)devfdt_get_addr_index(dev, 1);
  589. if (!pll_clk->creg_regs)
  590. return -EINVAL;
  591. return 0;
  592. }
  593. static const struct udevice_id hsdk_cgu_clk_id[] = {
  594. { .compatible = "snps,hsdk-cgu-clock" },
  595. { }
  596. };
  597. U_BOOT_DRIVER(hsdk_cgu_clk) = {
  598. .name = "hsdk-cgu-clk",
  599. .id = UCLASS_CLK,
  600. .of_match = hsdk_cgu_clk_id,
  601. .probe = hsdk_cgu_clk_probe,
  602. .priv_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
  603. .ops = &hsdk_cgu_ops,
  604. };