cache-v5l2.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 Andes Technology Corporation
  4. * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <cache.h>
  9. #include <dm.h>
  10. #include <hang.h>
  11. #include <asm/io.h>
  12. #include <dm/ofnode.h>
  13. struct l2cache {
  14. volatile u64 configure;
  15. volatile u64 control;
  16. volatile u64 hpm0;
  17. volatile u64 hpm1;
  18. volatile u64 hpm2;
  19. volatile u64 hpm3;
  20. volatile u64 error_status;
  21. volatile u64 ecc_error;
  22. volatile u64 cctl_command0;
  23. volatile u64 cctl_access_line0;
  24. volatile u64 cctl_command1;
  25. volatile u64 cctl_access_line1;
  26. volatile u64 cctl_command2;
  27. volatile u64 cctl_access_line2;
  28. volatile u64 cctl_command3;
  29. volatile u64 cctl_access_line4;
  30. volatile u64 cctl_status;
  31. };
  32. /* Control Register */
  33. #define L2_ENABLE 0x1
  34. /* prefetch */
  35. #define IPREPETCH_OFF 3
  36. #define DPREPETCH_OFF 5
  37. #define IPREPETCH_MSK (3 << IPREPETCH_OFF)
  38. #define DPREPETCH_MSK (3 << DPREPETCH_OFF)
  39. /* tag ram */
  40. #define TRAMOCTL_OFF 8
  41. #define TRAMICTL_OFF 10
  42. #define TRAMOCTL_MSK (3 << TRAMOCTL_OFF)
  43. #define TRAMICTL_MSK BIT(TRAMICTL_OFF)
  44. /* data ram */
  45. #define DRAMOCTL_OFF 11
  46. #define DRAMICTL_OFF 13
  47. #define DRAMOCTL_MSK (3 << DRAMOCTL_OFF)
  48. #define DRAMICTL_MSK BIT(DRAMICTL_OFF)
  49. /* CCTL Command Register */
  50. #define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * 0x10)
  51. #define L2_WBINVAL_ALL 0x12
  52. /* CCTL Status Register */
  53. #define CCTL_STATUS_MSK(hart) (0xf << ((hart) * 4))
  54. #define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4))
  55. #define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * 4))
  56. #define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * 4))
  57. DECLARE_GLOBAL_DATA_PTR;
  58. struct v5l2_plat {
  59. struct l2cache *regs;
  60. u32 iprefetch;
  61. u32 dprefetch;
  62. u32 tram_ctl[2];
  63. u32 dram_ctl[2];
  64. };
  65. static int v5l2_enable(struct udevice *dev)
  66. {
  67. struct v5l2_plat *plat = dev_get_platdata(dev);
  68. volatile struct l2cache *regs = plat->regs;
  69. if (regs)
  70. setbits_le32(&regs->control, L2_ENABLE);
  71. return 0;
  72. }
  73. static int v5l2_disable(struct udevice *dev)
  74. {
  75. struct v5l2_plat *plat = dev_get_platdata(dev);
  76. volatile struct l2cache *regs = plat->regs;
  77. u8 hart = gd->arch.boot_hart;
  78. void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
  79. if ((regs) && (readl(&regs->control) & L2_ENABLE)) {
  80. writel(L2_WBINVAL_ALL, cctlcmd);
  81. while ((readl(&regs->cctl_status) & CCTL_STATUS_MSK(hart))) {
  82. if ((readl(&regs->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) {
  83. printf("L2 flush illegal! hanging...");
  84. hang();
  85. }
  86. }
  87. clrbits_le32(&regs->control, L2_ENABLE);
  88. }
  89. return 0;
  90. }
  91. static int v5l2_ofdata_to_platdata(struct udevice *dev)
  92. {
  93. struct v5l2_plat *plat = dev_get_platdata(dev);
  94. struct l2cache *regs;
  95. regs = (struct l2cache *)dev_read_addr(dev);
  96. plat->regs = regs;
  97. plat->iprefetch = -EINVAL;
  98. plat->dprefetch = -EINVAL;
  99. plat->tram_ctl[0] = -EINVAL;
  100. plat->dram_ctl[0] = -EINVAL;
  101. /* Instruction and data fetch prefetch depth */
  102. dev_read_u32(dev, "andes,inst-prefetch", &plat->iprefetch);
  103. dev_read_u32(dev, "andes,data-prefetch", &plat->dprefetch);
  104. /* Set tag RAM and data RAM setup and output cycle */
  105. dev_read_u32_array(dev, "andes,tag-ram-ctl", plat->tram_ctl, 2);
  106. dev_read_u32_array(dev, "andes,data-ram-ctl", plat->dram_ctl, 2);
  107. return 0;
  108. }
  109. static int v5l2_probe(struct udevice *dev)
  110. {
  111. struct v5l2_plat *plat = dev_get_platdata(dev);
  112. struct l2cache *regs = plat->regs;
  113. u32 ctl_val;
  114. ctl_val = readl(&regs->control);
  115. if (!(ctl_val & L2_ENABLE))
  116. ctl_val |= L2_ENABLE;
  117. if (plat->iprefetch != -EINVAL) {
  118. ctl_val &= ~(IPREPETCH_MSK);
  119. ctl_val |= (plat->iprefetch << IPREPETCH_OFF);
  120. }
  121. if (plat->dprefetch != -EINVAL) {
  122. ctl_val &= ~(DPREPETCH_MSK);
  123. ctl_val |= (plat->dprefetch << DPREPETCH_OFF);
  124. }
  125. if (plat->tram_ctl[0] != -EINVAL) {
  126. ctl_val &= ~(TRAMOCTL_MSK | TRAMICTL_MSK);
  127. ctl_val |= plat->tram_ctl[0] << TRAMOCTL_OFF;
  128. ctl_val |= plat->tram_ctl[1] << TRAMICTL_OFF;
  129. }
  130. if (plat->dram_ctl[0] != -EINVAL) {
  131. ctl_val &= ~(DRAMOCTL_MSK | DRAMICTL_MSK);
  132. ctl_val |= plat->dram_ctl[0] << DRAMOCTL_OFF;
  133. ctl_val |= plat->dram_ctl[1] << DRAMICTL_OFF;
  134. }
  135. writel(ctl_val, &regs->control);
  136. return 0;
  137. }
  138. static const struct udevice_id v5l2_cache_ids[] = {
  139. { .compatible = "v5l2cache" },
  140. {}
  141. };
  142. static const struct cache_ops v5l2_cache_ops = {
  143. .enable = v5l2_enable,
  144. .disable = v5l2_disable,
  145. };
  146. U_BOOT_DRIVER(v5l2_cache) = {
  147. .name = "v5l2_cache",
  148. .id = UCLASS_CACHE,
  149. .of_match = v5l2_cache_ids,
  150. .ofdata_to_platdata = v5l2_ofdata_to_platdata,
  151. .probe = v5l2_probe,
  152. .platdata_auto_alloc_size = sizeof(struct v5l2_plat),
  153. .ops = &v5l2_cache_ops,
  154. .flags = DM_FLAG_PRE_RELOC,
  155. };