sata_sil3114.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved.
  4. * Author: Tor Krill <tor@excito.com>
  5. *
  6. * This is a driver for Silicon Image sil3114 sata chip modelled on
  7. * the ata_piix driver
  8. */
  9. #include <common.h>
  10. #include <pci.h>
  11. #include <command.h>
  12. #include <config.h>
  13. #include <asm/byteorder.h>
  14. #include <asm/io.h>
  15. #include <ide.h>
  16. #include <sata.h>
  17. #include <libata.h>
  18. #include "sata_sil3114.h"
  19. /* Convert sectorsize to wordsize */
  20. #define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
  21. /* Forwards */
  22. u8 sil3114_spin_up (int num);
  23. u8 sil3114_spin_down (int num);
  24. static int sata_bus_softreset (int num);
  25. static void sata_identify (int num, int dev);
  26. static u8 check_power_mode (int num);
  27. static void sata_port (struct sata_ioports *ioport);
  28. static void set_Feature_cmd (int num, int dev);
  29. static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
  30. unsigned int max, u8 usealtstatus);
  31. static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus);
  32. static void msleep (int count);
  33. static u32 iobase[6] = { 0, 0, 0, 0, 0, 0}; /* PCI BAR registers for device */
  34. static struct sata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
  35. static void output_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
  36. {
  37. while (words--) {
  38. __raw_writew (*sect_buf++, (void *)ioaddr->data_addr);
  39. }
  40. }
  41. static int input_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
  42. {
  43. while (words--) {
  44. *sect_buf++ = __raw_readw ((void *)ioaddr->data_addr);
  45. }
  46. return 0;
  47. }
  48. static int sata_bus_softreset (int num)
  49. {
  50. u8 status = 0;
  51. port[num].dev_mask = 1;
  52. port[num].ctl_reg = 0x08; /*Default value of control reg */
  53. writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
  54. udelay (10);
  55. writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
  56. udelay (10);
  57. writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
  58. /* spec mandates ">= 2ms" before checking status.
  59. * We wait 150ms, because that was the magic delay used for
  60. * ATAPI devices in Hale Landis's ATADRVR, for the period of time
  61. * between when the ATA command register is written, and then
  62. * status is checked. Because waiting for "a while" before
  63. * checking status is fine, post SRST, we perform this magic
  64. * delay here as well.
  65. */
  66. msleep (150);
  67. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300, 0);
  68. while ((status & ATA_BUSY)) {
  69. msleep (100);
  70. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3, 0);
  71. }
  72. if (status & ATA_BUSY) {
  73. printf ("ata%u is slow to respond,plz be patient\n", num);
  74. }
  75. while ((status & ATA_BUSY)) {
  76. msleep (100);
  77. status = sata_chk_status (&port[num].ioaddr, 0);
  78. }
  79. if (status & ATA_BUSY) {
  80. printf ("ata%u failed to respond : ", num);
  81. printf ("bus reset failed\n");
  82. port[num].dev_mask = 0;
  83. return 1;
  84. }
  85. return 0;
  86. }
  87. static void sata_identify (int num, int dev)
  88. {
  89. u8 cmd = 0, status = 0, devno = num;
  90. u16 iobuf[ATA_SECTOR_WORDS];
  91. u64 n_sectors = 0;
  92. memset (iobuf, 0, sizeof (iobuf));
  93. if (!(port[num].dev_mask & 0x01)) {
  94. printf ("dev%d is not present on port#%d\n", dev, num);
  95. return;
  96. }
  97. debug ("port=%d dev=%d\n", num, dev);
  98. status = 0;
  99. cmd = ATA_CMD_ID_ATA; /*Device Identify Command */
  100. writeb (cmd, port[num].ioaddr.command_addr);
  101. readb (port[num].ioaddr.altstatus_addr);
  102. udelay (10);
  103. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000, 0);
  104. if (status & ATA_ERR) {
  105. printf ("\ndevice not responding\n");
  106. port[num].dev_mask &= ~0x01;
  107. return;
  108. }
  109. input_data (&port[num].ioaddr, iobuf, ATA_SECTOR_WORDS);
  110. ata_swap_buf_le16 (iobuf, ATA_SECTOR_WORDS);
  111. debug ("Specific config: %x\n", iobuf[2]);
  112. /* we require LBA and DMA support (bits 8 & 9 of word 49) */
  113. if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
  114. debug ("ata%u: no dma/lba\n", num);
  115. }
  116. #ifdef DEBUG
  117. ata_dump_id (iobuf);
  118. #endif
  119. n_sectors = ata_id_n_sectors (iobuf);
  120. if (n_sectors == 0) {
  121. port[num].dev_mask &= ~0x01;
  122. return;
  123. }
  124. ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].revision,
  125. ATA_ID_FW_REV, sizeof (sata_dev_desc[devno].revision));
  126. ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].vendor,
  127. ATA_ID_PROD, sizeof (sata_dev_desc[devno].vendor));
  128. ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].product,
  129. ATA_ID_SERNO, sizeof (sata_dev_desc[devno].product));
  130. /* TODO - atm we asume harddisk ie not removable */
  131. sata_dev_desc[devno].removable = 0;
  132. sata_dev_desc[devno].lba = (u32) n_sectors;
  133. debug("lba=0x%lx\n", sata_dev_desc[devno].lba);
  134. #ifdef CONFIG_LBA48
  135. if (iobuf[83] & (1 << 10)) {
  136. sata_dev_desc[devno].lba48 = 1;
  137. } else {
  138. sata_dev_desc[devno].lba48 = 0;
  139. }
  140. #endif
  141. /* assuming HD */
  142. sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
  143. sata_dev_desc[devno].blksz = ATA_SECT_SIZE;
  144. sata_dev_desc[devno].lun = 0; /* just to fill something in... */
  145. }
  146. static void set_Feature_cmd (int num, int dev)
  147. {
  148. u8 status = 0;
  149. if (!(port[num].dev_mask & 0x01)) {
  150. debug ("dev%d is not present on port#%d\n", dev, num);
  151. return;
  152. }
  153. writeb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
  154. writeb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
  155. writeb (0, port[num].ioaddr.lbal_addr);
  156. writeb (0, port[num].ioaddr.lbam_addr);
  157. writeb (0, port[num].ioaddr.lbah_addr);
  158. writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
  159. writeb (ATA_CMD_SET_FEATURES, port[num].ioaddr.command_addr);
  160. udelay (50);
  161. msleep (150);
  162. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
  163. if ((status & (ATA_BUSY | ATA_ERR))) {
  164. printf ("Error : status 0x%02x\n", status);
  165. port[num].dev_mask &= ~0x01;
  166. }
  167. }
  168. u8 sil3114_spin_down (int num)
  169. {
  170. u8 status = 0;
  171. debug ("Spin down disk\n");
  172. if (!(port[num].dev_mask & 0x01)) {
  173. debug ("Device ata%d is not present\n", num);
  174. return 1;
  175. }
  176. if ((status = check_power_mode (num)) == 0x00) {
  177. debug ("Already in standby\n");
  178. return 0;
  179. }
  180. if (status == 0x01) {
  181. printf ("Failed to check power mode on ata%d\n", num);
  182. return 1;
  183. }
  184. if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
  185. printf ("Device ata%d not ready\n", num);
  186. return 1;
  187. }
  188. writeb (0x00, port[num].ioaddr.feature_addr);
  189. writeb (0x00, port[num].ioaddr.nsect_addr);
  190. writeb (0x00, port[num].ioaddr.lbal_addr);
  191. writeb (0x00, port[num].ioaddr.lbam_addr);
  192. writeb (0x00, port[num].ioaddr.lbah_addr);
  193. writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
  194. writeb (ATA_CMD_STANDBY, port[num].ioaddr.command_addr);
  195. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
  196. if ((status & (ATA_BUSY | ATA_ERR))) {
  197. printf ("Error waiting for disk spin down: status 0x%02x\n",
  198. status);
  199. port[num].dev_mask &= ~0x01;
  200. return 1;
  201. }
  202. return 0;
  203. }
  204. u8 sil3114_spin_up (int num)
  205. {
  206. u8 status = 0;
  207. debug ("Spin up disk\n");
  208. if (!(port[num].dev_mask & 0x01)) {
  209. debug ("Device ata%d is not present\n", num);
  210. return 1;
  211. }
  212. if ((status = check_power_mode (num)) != 0x00) {
  213. if (status == 0x01) {
  214. printf ("Failed to check power mode on ata%d\n", num);
  215. return 1;
  216. } else {
  217. /* should be up and running already */
  218. return 0;
  219. }
  220. }
  221. if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
  222. printf ("Device ata%d not ready\n", num);
  223. return 1;
  224. }
  225. debug ("Stautus of device check: %d\n", status);
  226. writeb (0x00, port[num].ioaddr.feature_addr);
  227. writeb (0x00, port[num].ioaddr.nsect_addr);
  228. writeb (0x00, port[num].ioaddr.lbal_addr);
  229. writeb (0x00, port[num].ioaddr.lbam_addr);
  230. writeb (0x00, port[num].ioaddr.lbah_addr);
  231. writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
  232. writeb (ATA_CMD_IDLE, port[num].ioaddr.command_addr);
  233. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
  234. if ((status & (ATA_BUSY | ATA_ERR))) {
  235. printf ("Error waiting for disk spin up: status 0x%02x\n",
  236. status);
  237. port[num].dev_mask &= ~0x01;
  238. return 1;
  239. }
  240. /* Wait for disk to enter Active state */
  241. do {
  242. msleep (10);
  243. status = check_power_mode (num);
  244. } while ((status == 0x00) || (status == 0x80));
  245. if (status == 0x01) {
  246. printf ("Falied waiting for disk to spin up\n");
  247. return 1;
  248. }
  249. return 0;
  250. }
  251. /* Return value is not the usual here
  252. * 0x00 - Device stand by
  253. * 0x01 - Operation failed
  254. * 0x80 - Device idle
  255. * 0xff - Device active
  256. */
  257. static u8 check_power_mode (int num)
  258. {
  259. u8 status = 0;
  260. u8 res = 0;
  261. if (!(port[num].dev_mask & 0x01)) {
  262. debug ("Device ata%d is not present\n", num);
  263. return 1;
  264. }
  265. if (!(sata_chk_status (&port[num].ioaddr, 0) & ATA_DRDY)) {
  266. printf ("Device ata%d not ready\n", num);
  267. return 1;
  268. }
  269. writeb (0, port[num].ioaddr.feature_addr);
  270. writeb (0, port[num].ioaddr.nsect_addr);
  271. writeb (0, port[num].ioaddr.lbal_addr);
  272. writeb (0, port[num].ioaddr.lbam_addr);
  273. writeb (0, port[num].ioaddr.lbah_addr);
  274. writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
  275. writeb (ATA_CMD_CHK_POWER, port[num].ioaddr.command_addr);
  276. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
  277. if ((status & (ATA_BUSY | ATA_ERR))) {
  278. printf
  279. ("Error waiting for check power mode complete : status 0x%02x\n",
  280. status);
  281. port[num].dev_mask &= ~0x01;
  282. return 1;
  283. }
  284. res = readb (port[num].ioaddr.nsect_addr);
  285. debug ("Check powermode: %d\n", res);
  286. return res;
  287. }
  288. static void sata_port (struct sata_ioports *ioport)
  289. {
  290. ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
  291. ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
  292. ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
  293. ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
  294. ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
  295. ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
  296. ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
  297. ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
  298. ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
  299. ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
  300. }
  301. static u8 wait_for_irq (int num, unsigned int max)
  302. {
  303. u32 port = iobase[5];
  304. switch (num) {
  305. case 0:
  306. port += VND_TF_CNST_CH0;
  307. break;
  308. case 1:
  309. port += VND_TF_CNST_CH1;
  310. break;
  311. case 2:
  312. port += VND_TF_CNST_CH2;
  313. break;
  314. case 3:
  315. port += VND_TF_CNST_CH3;
  316. break;
  317. default:
  318. return 1;
  319. }
  320. do {
  321. if (readl (port) & VND_TF_CNST_INTST) {
  322. break;
  323. }
  324. udelay (1000);
  325. max--;
  326. } while ((max > 0));
  327. return (max == 0);
  328. }
  329. static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
  330. unsigned int max, u8 usealtstatus)
  331. {
  332. u8 status;
  333. do {
  334. if (!((status = sata_chk_status (ioaddr, usealtstatus)) & bits)) {
  335. break;
  336. }
  337. udelay (1000);
  338. max--;
  339. } while ((status & bits) && (max > 0));
  340. return status;
  341. }
  342. static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus)
  343. {
  344. if (!usealtstatus) {
  345. return readb (ioaddr->status_addr);
  346. } else {
  347. return readb (ioaddr->altstatus_addr);
  348. }
  349. }
  350. static void msleep (int count)
  351. {
  352. int i;
  353. for (i = 0; i < count; i++)
  354. udelay (1000);
  355. }
  356. /* Read up to 255 sectors
  357. *
  358. * Returns sectors read
  359. */
  360. static u8 do_one_read (int device, ulong block, u8 blkcnt, u16 * buff,
  361. uchar lba48)
  362. {
  363. u8 sr = 0;
  364. u8 status;
  365. u64 blknr = (u64) block;
  366. if (!(sata_chk_status (&port[device].ioaddr, 0) & ATA_DRDY)) {
  367. printf ("Device ata%d not ready\n", device);
  368. return 0;
  369. }
  370. /* Set up transfer */
  371. #ifdef CONFIG_LBA48
  372. if (lba48) {
  373. /* write high bits */
  374. writeb (0, port[device].ioaddr.nsect_addr);
  375. writeb ((blknr >> 24) & 0xFF, port[device].ioaddr.lbal_addr);
  376. writeb ((blknr >> 32) & 0xFF, port[device].ioaddr.lbam_addr);
  377. writeb ((blknr >> 40) & 0xFF, port[device].ioaddr.lbah_addr);
  378. }
  379. #endif
  380. writeb (blkcnt, port[device].ioaddr.nsect_addr);
  381. writeb (((blknr) >> 0) & 0xFF, port[device].ioaddr.lbal_addr);
  382. writeb ((blknr >> 8) & 0xFF, port[device].ioaddr.lbam_addr);
  383. writeb ((blknr >> 16) & 0xFF, port[device].ioaddr.lbah_addr);
  384. #ifdef CONFIG_LBA48
  385. if (lba48) {
  386. writeb (ATA_LBA, port[device].ioaddr.device_addr);
  387. writeb (ATA_CMD_PIO_READ_EXT, port[device].ioaddr.command_addr);
  388. } else
  389. #endif
  390. {
  391. writeb (ATA_LBA | ((blknr >> 24) & 0xF),
  392. port[device].ioaddr.device_addr);
  393. writeb (ATA_CMD_PIO_READ, port[device].ioaddr.command_addr);
  394. }
  395. status = sata_busy_wait (&port[device].ioaddr, ATA_BUSY, 10000, 1);
  396. if (status & ATA_BUSY) {
  397. u8 err = 0;
  398. printf ("Device %d not responding status %d\n", device, status);
  399. err = readb (port[device].ioaddr.error_addr);
  400. printf ("Error reg = 0x%x\n", err);
  401. return (sr);
  402. }
  403. while (blkcnt--) {
  404. if (wait_for_irq (device, 500)) {
  405. printf ("ata%u irq failed\n", device);
  406. return sr;
  407. }
  408. status = sata_chk_status (&port[device].ioaddr, 0);
  409. if (status & ATA_ERR) {
  410. printf ("ata%u error %d\n", device,
  411. readb (port[device].ioaddr.error_addr));
  412. return sr;
  413. }
  414. /* Read one sector */
  415. input_data (&port[device].ioaddr, buff, ATA_SECTOR_WORDS);
  416. buff += ATA_SECTOR_WORDS;
  417. sr++;
  418. }
  419. return sr;
  420. }
  421. ulong sata_read (int device, ulong block, lbaint_t blkcnt, void *buff)
  422. {
  423. ulong n = 0, sread;
  424. u16 *buffer = (u16 *) buff;
  425. u8 status = 0;
  426. u64 blknr = (u64) block;
  427. unsigned char lba48 = 0;
  428. #ifdef CONFIG_LBA48
  429. if (blknr > 0xfffffff) {
  430. if (!sata_dev_desc[device].lba48) {
  431. printf ("Drive doesn't support 48-bit addressing\n");
  432. return 0;
  433. }
  434. /* more than 28 bits used, use 48bit mode */
  435. lba48 = 1;
  436. }
  437. #endif
  438. while (blkcnt > 0) {
  439. if (blkcnt > 255) {
  440. sread = 255;
  441. } else {
  442. sread = blkcnt;
  443. }
  444. status = do_one_read (device, blknr, sread, buffer, lba48);
  445. if (status != sread) {
  446. printf ("Read failed\n");
  447. return n;
  448. }
  449. blkcnt -= sread;
  450. blknr += sread;
  451. n += sread;
  452. buffer += sread * ATA_SECTOR_WORDS;
  453. }
  454. return n;
  455. }
  456. ulong sata_write (int device, ulong block, lbaint_t blkcnt, const void *buff)
  457. {
  458. ulong n = 0;
  459. u16 *buffer = (u16 *) buff;
  460. unsigned char status = 0, num = 0;
  461. u64 blknr = (u64) block;
  462. #ifdef CONFIG_LBA48
  463. unsigned char lba48 = 0;
  464. if (blknr > 0xfffffff) {
  465. if (!sata_dev_desc[device].lba48) {
  466. printf ("Drive doesn't support 48-bit addressing\n");
  467. return 0;
  468. }
  469. /* more than 28 bits used, use 48bit mode */
  470. lba48 = 1;
  471. }
  472. #endif
  473. /*Port Number */
  474. num = device;
  475. while (blkcnt-- > 0) {
  476. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500, 0);
  477. if (status & ATA_BUSY) {
  478. printf ("ata%u failed to respond\n", port[num].port_no);
  479. return n;
  480. }
  481. #ifdef CONFIG_LBA48
  482. if (lba48) {
  483. /* write high bits */
  484. writeb (0, port[num].ioaddr.nsect_addr);
  485. writeb ((blknr >> 24) & 0xFF,
  486. port[num].ioaddr.lbal_addr);
  487. writeb ((blknr >> 32) & 0xFF,
  488. port[num].ioaddr.lbam_addr);
  489. writeb ((blknr >> 40) & 0xFF,
  490. port[num].ioaddr.lbah_addr);
  491. }
  492. #endif
  493. writeb (1, port[num].ioaddr.nsect_addr);
  494. writeb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
  495. writeb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
  496. writeb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
  497. #ifdef CONFIG_LBA48
  498. if (lba48) {
  499. writeb (ATA_LBA, port[num].ioaddr.device_addr);
  500. writeb (ATA_CMD_PIO_WRITE_EXT, port[num].ioaddr.command_addr);
  501. } else
  502. #endif
  503. {
  504. writeb (ATA_LBA | ((blknr >> 24) & 0xF),
  505. port[num].ioaddr.device_addr);
  506. writeb (ATA_CMD_PIO_WRITE, port[num].ioaddr.command_addr);
  507. }
  508. msleep (50);
  509. /*may take up to 4 sec */
  510. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000, 0);
  511. if ((status & (ATA_DRQ | ATA_BUSY | ATA_ERR)) != ATA_DRQ) {
  512. printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
  513. device, (ulong) blknr, status);
  514. return (n);
  515. }
  516. output_data (&port[num].ioaddr, buffer, ATA_SECTOR_WORDS);
  517. readb (port[num].ioaddr.altstatus_addr);
  518. udelay (50);
  519. ++n;
  520. ++blknr;
  521. buffer += ATA_SECTOR_WORDS;
  522. }
  523. return n;
  524. }
  525. /* Driver implementation */
  526. static u8 sil_get_device_cache_line (pci_dev_t pdev)
  527. {
  528. u8 cache_line = 0;
  529. pci_read_config_byte (pdev, PCI_CACHE_LINE_SIZE, &cache_line);
  530. return cache_line;
  531. }
  532. int init_sata (int dev)
  533. {
  534. static u8 init_done = 0;
  535. static int res = 1;
  536. pci_dev_t devno;
  537. u8 cls = 0;
  538. u16 cmd = 0;
  539. u32 sconf = 0;
  540. if (init_done) {
  541. return res;
  542. }
  543. init_done = 1;
  544. if ((devno = pci_find_device (SIL_VEND_ID, SIL3114_DEVICE_ID, 0)) == -1) {
  545. res = 1;
  546. return res;
  547. }
  548. /* Read out all BARs, even though we only use MMIO from BAR5 */
  549. pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase[0]);
  550. pci_read_config_dword (devno, PCI_BASE_ADDRESS_1, &iobase[1]);
  551. pci_read_config_dword (devno, PCI_BASE_ADDRESS_2, &iobase[2]);
  552. pci_read_config_dword (devno, PCI_BASE_ADDRESS_3, &iobase[3]);
  553. pci_read_config_dword (devno, PCI_BASE_ADDRESS_4, &iobase[4]);
  554. pci_read_config_dword (devno, PCI_BASE_ADDRESS_5, &iobase[5]);
  555. if ((iobase[0] == 0xFFFFFFFF) || (iobase[1] == 0xFFFFFFFF) ||
  556. (iobase[2] == 0xFFFFFFFF) || (iobase[3] == 0xFFFFFFFF) ||
  557. (iobase[4] == 0xFFFFFFFF) || (iobase[5] == 0xFFFFFFFF)) {
  558. printf ("Error no base addr for SATA controller\n");
  559. res = 1;
  560. return res;
  561. }
  562. /* mask off unused bits */
  563. iobase[0] &= 0xfffffffc;
  564. iobase[1] &= 0xfffffff8;
  565. iobase[2] &= 0xfffffffc;
  566. iobase[3] &= 0xfffffff8;
  567. iobase[4] &= 0xfffffff0;
  568. iobase[5] &= 0xfffffc00;
  569. /* from sata_sil in Linux kernel */
  570. cls = sil_get_device_cache_line (devno);
  571. if (cls) {
  572. cls >>= 3;
  573. cls++; /* cls = (line_size/8)+1 */
  574. writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH0);
  575. writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH1);
  576. writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH2);
  577. writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH3);
  578. } else {
  579. printf ("Cache line not set. Driver may not function\n");
  580. }
  581. /* Enable operation */
  582. pci_read_config_word (devno, PCI_COMMAND, &cmd);
  583. cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
  584. pci_write_config_word (devno, PCI_COMMAND, cmd);
  585. /* Disable interrupt usage */
  586. pci_read_config_dword (devno, VND_SYSCONFSTAT, &sconf);
  587. sconf |= (VND_SYSCONFSTAT_CHN_0_INTBLOCK | VND_SYSCONFSTAT_CHN_1_INTBLOCK);
  588. pci_write_config_dword (devno, VND_SYSCONFSTAT, sconf);
  589. res = 0;
  590. return res;
  591. }
  592. int reset_sata(int dev)
  593. {
  594. return 0;
  595. }
  596. /* Check if device is connected to port */
  597. int sata_bus_probe (int portno)
  598. {
  599. u32 port = iobase[5];
  600. u32 val;
  601. switch (portno) {
  602. case 0:
  603. port += VND_SSTATUS_CH0;
  604. break;
  605. case 1:
  606. port += VND_SSTATUS_CH1;
  607. break;
  608. case 2:
  609. port += VND_SSTATUS_CH2;
  610. break;
  611. case 3:
  612. port += VND_SSTATUS_CH3;
  613. break;
  614. default:
  615. return 0;
  616. }
  617. val = readl (port);
  618. if ((val & SATA_DET_PRES) == SATA_DET_PRES) {
  619. return 1;
  620. } else {
  621. return 0;
  622. }
  623. }
  624. int sata_phy_reset (int portno)
  625. {
  626. u32 port = iobase[5];
  627. u32 val;
  628. switch (portno) {
  629. case 0:
  630. port += VND_SCONTROL_CH0;
  631. break;
  632. case 1:
  633. port += VND_SCONTROL_CH1;
  634. break;
  635. case 2:
  636. port += VND_SCONTROL_CH2;
  637. break;
  638. case 3:
  639. port += VND_SCONTROL_CH3;
  640. break;
  641. default:
  642. return 0;
  643. }
  644. val = readl (port);
  645. writel (val | SATA_SC_DET_RST, port);
  646. msleep (150);
  647. writel (val & ~SATA_SC_DET_RST, port);
  648. return 0;
  649. }
  650. int scan_sata (int dev)
  651. {
  652. /* A bit brain dead, but the code has a legacy */
  653. switch (dev) {
  654. case 0:
  655. port[0].port_no = 0;
  656. port[0].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH0;
  657. port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
  658. (iobase[5] + VND_TF2_CH0) | ATA_PCI_CTL_OFS;
  659. port[0].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH0;
  660. break;
  661. #if (CONFIG_SYS_SATA_MAX_DEVICE >= 1)
  662. case 1:
  663. port[1].port_no = 0;
  664. port[1].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH1;
  665. port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
  666. (iobase[5] + VND_TF2_CH1) | ATA_PCI_CTL_OFS;
  667. port[1].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH1;
  668. break;
  669. #elif (CONFIG_SYS_SATA_MAX_DEVICE >= 2)
  670. case 2:
  671. port[2].port_no = 0;
  672. port[2].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH2;
  673. port[2].ioaddr.altstatus_addr = port[2].ioaddr.ctl_addr =
  674. (iobase[5] + VND_TF2_CH2) | ATA_PCI_CTL_OFS;
  675. port[2].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH2;
  676. break;
  677. #elif (CONFIG_SYS_SATA_MAX_DEVICE >= 3)
  678. case 3:
  679. port[3].port_no = 0;
  680. port[3].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH3;
  681. port[3].ioaddr.altstatus_addr = port[3].ioaddr.ctl_addr =
  682. (iobase[5] + VND_TF2_CH3) | ATA_PCI_CTL_OFS;
  683. port[3].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH3;
  684. break;
  685. #endif
  686. default:
  687. printf ("Tried to scan unknown port: ata%d\n", dev);
  688. return 1;
  689. }
  690. /* Initialize other registers */
  691. sata_port (&port[dev].ioaddr);
  692. /* Check for attached device */
  693. if (!sata_bus_probe (dev)) {
  694. port[dev].port_state = 0;
  695. debug ("SATA#%d port is not present\n", dev);
  696. } else {
  697. debug ("SATA#%d port is present\n", dev);
  698. if (sata_bus_softreset (dev)) {
  699. /* soft reset failed, try a hard one */
  700. sata_phy_reset (dev);
  701. if (sata_bus_softreset (dev)) {
  702. port[dev].port_state = 0;
  703. } else {
  704. port[dev].port_state = 1;
  705. }
  706. } else {
  707. port[dev].port_state = 1;
  708. }
  709. }
  710. if (port[dev].port_state == 1) {
  711. /* Probe device and set xfer mode */
  712. sata_identify (dev, 0);
  713. set_Feature_cmd (dev, 0);
  714. }
  715. return 0;
  716. }