sata_ceva.c 5.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2015 - 2016 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <ahci.h>
  9. #include <scsi.h>
  10. #include <asm/io.h>
  11. #include <linux/ioport.h>
  12. /* Vendor Specific Register Offsets */
  13. #define AHCI_VEND_PCFG 0xA4
  14. #define AHCI_VEND_PPCFG 0xA8
  15. #define AHCI_VEND_PP2C 0xAC
  16. #define AHCI_VEND_PP3C 0xB0
  17. #define AHCI_VEND_PP4C 0xB4
  18. #define AHCI_VEND_PP5C 0xB8
  19. #define AHCI_VEND_AXICC 0xBc
  20. #define AHCI_VEND_PAXIC 0xC0
  21. #define AHCI_VEND_PTC 0xC8
  22. /* Vendor Specific Register bit definitions */
  23. #define PAXIC_ADBW_BW64 0x1
  24. #define PAXIC_MAWIDD (1 << 8)
  25. #define PAXIC_MARIDD (1 << 16)
  26. #define PAXIC_OTL (0x4 << 20)
  27. #define PCFG_TPSS_VAL (0x32 << 16)
  28. #define PCFG_TPRS_VAL (0x2 << 12)
  29. #define PCFG_PAD_VAL 0x2
  30. #define PPCFG_TTA 0x1FFFE
  31. #define PPCFG_PSSO_EN (1 << 28)
  32. #define PPCFG_PSS_EN (1 << 29)
  33. #define PPCFG_ESDF_EN (1 << 31)
  34. #define PP2C_CIBGMN 0x0F
  35. #define PP2C_CIBGMX (0x25 << 8)
  36. #define PP2C_CIBGN (0x18 << 16)
  37. #define PP2C_CINMP (0x29 << 24)
  38. #define PP3C_CWBGMN 0x04
  39. #define PP3C_CWBGMX (0x0B << 8)
  40. #define PP3C_CWBGN (0x08 << 16)
  41. #define PP3C_CWNMP (0x0F << 24)
  42. #define PP4C_BMX 0x0a
  43. #define PP4C_BNM (0x08 << 8)
  44. #define PP4C_SFD (0x4a << 16)
  45. #define PP4C_PTST (0x06 << 24)
  46. #define PP5C_RIT 0x60216
  47. #define PP5C_RCT (0x7f0 << 20)
  48. #define PTC_RX_WM_VAL 0x40
  49. #define PTC_RSVD (1 << 27)
  50. #define PORT0_BASE 0x100
  51. #define PORT1_BASE 0x180
  52. /* Port Control Register Bit Definitions */
  53. #define PORT_SCTL_SPD_GEN3 (0x3 << 4)
  54. #define PORT_SCTL_SPD_GEN2 (0x2 << 4)
  55. #define PORT_SCTL_SPD_GEN1 (0x1 << 4)
  56. #define PORT_SCTL_IPM (0x3 << 8)
  57. #define PORT_BASE 0x100
  58. #define PORT_OFFSET 0x80
  59. #define NR_PORTS 2
  60. #define DRV_NAME "ahci-ceva"
  61. #define CEVA_FLAG_BROKEN_GEN2 1
  62. /* flag bit definition */
  63. #define FLAG_COHERENT 1
  64. /* register config value */
  65. #define CEVA_PHY1_CFG 0xa003fffe
  66. #define CEVA_PHY2_CFG 0x28184d1f
  67. #define CEVA_PHY3_CFG 0x0e081509
  68. #define CEVA_TRANS_CFG 0x08000029
  69. #define CEVA_AXICC_CFG 0x3fffffff
  70. /* for ls1021a */
  71. #define LS1021_AHCI_VEND_AXICC 0xC0
  72. #define LS1021_CEVA_PHY2_CFG 0x28183414
  73. #define LS1021_CEVA_PHY3_CFG 0x0e080e06
  74. #define LS1021_CEVA_PHY4_CFG 0x064a080b
  75. #define LS1021_CEVA_PHY5_CFG 0x2aa86470
  76. /* ecc val pair */
  77. #define ECC_DIS_VAL_CH1 0x00020000
  78. #define ECC_DIS_VAL_CH2 0x80000000
  79. #define ECC_DIS_VAL_CH3 0x40000000
  80. enum ceva_soc {
  81. CEVA_1V84,
  82. CEVA_LS1012A,
  83. CEVA_LS1021A,
  84. CEVA_LS1028A,
  85. CEVA_LS1043A,
  86. CEVA_LS1046A,
  87. CEVA_LS1088A,
  88. CEVA_LS2080A,
  89. };
  90. struct ceva_sata_priv {
  91. ulong base;
  92. ulong ecc_base;
  93. enum ceva_soc soc;
  94. ulong flag;
  95. };
  96. static int ceva_init_sata(struct ceva_sata_priv *priv)
  97. {
  98. ulong ecc_addr = priv->ecc_base;
  99. ulong base = priv->base;
  100. ulong tmp;
  101. switch (priv->soc) {
  102. case CEVA_1V84:
  103. tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
  104. writel(tmp, base + AHCI_VEND_PAXIC);
  105. tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | PCFG_PAD_VAL;
  106. writel(tmp, base + AHCI_VEND_PCFG);
  107. tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
  108. writel(tmp, base + AHCI_VEND_PPCFG);
  109. tmp = PTC_RX_WM_VAL | PTC_RSVD;
  110. writel(tmp, base + AHCI_VEND_PTC);
  111. break;
  112. case CEVA_LS1021A:
  113. if (!ecc_addr)
  114. return -EINVAL;
  115. writel(ECC_DIS_VAL_CH1, ecc_addr);
  116. writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
  117. writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C);
  118. writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C);
  119. writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C);
  120. writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C);
  121. writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
  122. break;
  123. case CEVA_LS1012A:
  124. case CEVA_LS1043A:
  125. case CEVA_LS1046A:
  126. if (!ecc_addr)
  127. return -EINVAL;
  128. writel(ECC_DIS_VAL_CH2, ecc_addr);
  129. /* fallthrough */
  130. case CEVA_LS2080A:
  131. writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
  132. writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
  133. break;
  134. case CEVA_LS1028A:
  135. case CEVA_LS1088A:
  136. if (!ecc_addr)
  137. return -EINVAL;
  138. writel(ECC_DIS_VAL_CH3, ecc_addr);
  139. writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
  140. writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
  141. break;
  142. }
  143. if (priv->flag & FLAG_COHERENT)
  144. writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
  145. return 0;
  146. }
  147. static int sata_ceva_bind(struct udevice *dev)
  148. {
  149. struct udevice *scsi_dev;
  150. return ahci_bind_scsi(dev, &scsi_dev);
  151. }
  152. static int sata_ceva_probe(struct udevice *dev)
  153. {
  154. struct ceva_sata_priv *priv = dev_get_priv(dev);
  155. ceva_init_sata(priv);
  156. return ahci_probe_scsi(dev, priv->base);
  157. }
  158. static const struct udevice_id sata_ceva_ids[] = {
  159. { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
  160. { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
  161. { .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A },
  162. { .compatible = "fsl,ls1028a-ahci", .data = CEVA_LS1028A },
  163. { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
  164. { .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A },
  165. { .compatible = "fsl,ls1088a-ahci", .data = CEVA_LS1088A },
  166. { .compatible = "fsl,ls2080a-ahci", .data = CEVA_LS2080A },
  167. { }
  168. };
  169. static int sata_ceva_ofdata_to_platdata(struct udevice *dev)
  170. {
  171. struct ceva_sata_priv *priv = dev_get_priv(dev);
  172. struct resource res_regs;
  173. int ret;
  174. if (dev_read_bool(dev, "dma-coherent"))
  175. priv->flag |= FLAG_COHERENT;
  176. priv->base = dev_read_addr(dev);
  177. if (priv->base == FDT_ADDR_T_NONE)
  178. return -EINVAL;
  179. ret = dev_read_resource_byname(dev, "ecc-addr", &res_regs);
  180. if (ret)
  181. priv->ecc_base = 0;
  182. else
  183. priv->ecc_base = res_regs.start;
  184. priv->soc = dev_get_driver_data(dev);
  185. debug("ccsr-sata-base %lx\t ecc-base %lx\n",
  186. priv->base,
  187. priv->ecc_base);
  188. return 0;
  189. }
  190. U_BOOT_DRIVER(ceva_host_blk) = {
  191. .name = "ceva_sata",
  192. .id = UCLASS_AHCI,
  193. .of_match = sata_ceva_ids,
  194. .bind = sata_ceva_bind,
  195. .ops = &scsi_ops,
  196. .priv_auto_alloc_size = sizeof(struct ceva_sata_priv),
  197. .probe = sata_ceva_probe,
  198. .ofdata_to_platdata = sata_ceva_ofdata_to_platdata,
  199. };