dwc_ahsata.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  4. * Terry Lv <r65388@freescale.com>
  5. */
  6. #include <common.h>
  7. #include <ahci.h>
  8. #include <cpu_func.h>
  9. #include <dm.h>
  10. #include <dwc_ahsata.h>
  11. #include <fis.h>
  12. #include <libata.h>
  13. #include <malloc.h>
  14. #include <memalign.h>
  15. #include <sata.h>
  16. #include <asm/io.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <asm/mach-imx/sata.h>
  20. #include <linux/bitops.h>
  21. #include <linux/ctype.h>
  22. #include <linux/errno.h>
  23. #include "dwc_ahsata_priv.h"
  24. struct sata_port_regs {
  25. u32 clb;
  26. u32 clbu;
  27. u32 fb;
  28. u32 fbu;
  29. u32 is;
  30. u32 ie;
  31. u32 cmd;
  32. u32 res1[1];
  33. u32 tfd;
  34. u32 sig;
  35. u32 ssts;
  36. u32 sctl;
  37. u32 serr;
  38. u32 sact;
  39. u32 ci;
  40. u32 sntf;
  41. u32 res2[1];
  42. u32 dmacr;
  43. u32 res3[1];
  44. u32 phycr;
  45. u32 physr;
  46. };
  47. struct sata_host_regs {
  48. u32 cap;
  49. u32 ghc;
  50. u32 is;
  51. u32 pi;
  52. u32 vs;
  53. u32 ccc_ctl;
  54. u32 ccc_ports;
  55. u32 res1[2];
  56. u32 cap2;
  57. u32 res2[30];
  58. u32 bistafr;
  59. u32 bistcr;
  60. u32 bistfctr;
  61. u32 bistsr;
  62. u32 bistdecr;
  63. u32 res3[2];
  64. u32 oobr;
  65. u32 res4[8];
  66. u32 timer1ms;
  67. u32 res5[1];
  68. u32 gparam1r;
  69. u32 gparam2r;
  70. u32 pparamr;
  71. u32 testr;
  72. u32 versionr;
  73. u32 idr;
  74. };
  75. #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
  76. #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
  77. #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
  78. static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
  79. {
  80. return base + 0x100 + (port * 0x80);
  81. }
  82. static int waiting_for_cmd_completed(u8 *offset,
  83. int timeout_msec,
  84. u32 sign)
  85. {
  86. int i;
  87. u32 status;
  88. for (i = 0;
  89. ((status = readl(offset)) & sign) && i < timeout_msec;
  90. ++i)
  91. mdelay(1);
  92. return (i < timeout_msec) ? 0 : -1;
  93. }
  94. static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk)
  95. {
  96. struct sata_host_regs *host_mmio = uc_priv->mmio_base;
  97. writel(SATA_HOST_OOBR_WE, &host_mmio->oobr);
  98. writel(0x02060b14, &host_mmio->oobr);
  99. return 0;
  100. }
  101. static int ahci_host_init(struct ahci_uc_priv *uc_priv)
  102. {
  103. u32 tmp, cap_save, num_ports;
  104. int i, j, timeout = 1000;
  105. struct sata_port_regs *port_mmio = NULL;
  106. struct sata_host_regs *host_mmio = uc_priv->mmio_base;
  107. int clk = mxc_get_clock(MXC_SATA_CLK);
  108. cap_save = readl(&host_mmio->cap);
  109. cap_save |= SATA_HOST_CAP_SSS;
  110. /* global controller reset */
  111. tmp = readl(&host_mmio->ghc);
  112. if ((tmp & SATA_HOST_GHC_HR) == 0)
  113. writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc);
  114. while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout)
  115. ;
  116. if (timeout <= 0) {
  117. debug("controller reset failed (0x%x)\n", tmp);
  118. return -1;
  119. }
  120. /* Set timer 1ms */
  121. writel(clk / 1000, &host_mmio->timer1ms);
  122. ahci_setup_oobr(uc_priv, 0);
  123. writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc);
  124. writel(cap_save, &host_mmio->cap);
  125. num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
  126. writel_with_flush((1 << num_ports) - 1, &host_mmio->pi);
  127. /*
  128. * Determine which Ports are implemented by the DWC_ahsata,
  129. * by reading the PI register. This bit map value aids the
  130. * software to determine how many Ports are available and
  131. * which Port registers need to be initialized.
  132. */
  133. uc_priv->cap = readl(&host_mmio->cap);
  134. uc_priv->port_map = readl(&host_mmio->pi);
  135. /* Determine how many command slots the HBA supports */
  136. uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1;
  137. debug("cap 0x%x port_map 0x%x n_ports %d\n",
  138. uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
  139. for (i = 0; i < uc_priv->n_ports; i++) {
  140. uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i);
  141. port_mmio = uc_priv->port[i].port_mmio;
  142. /* Ensure that the DWC_ahsata is in idle state */
  143. tmp = readl(&port_mmio->cmd);
  144. /*
  145. * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
  146. * are all cleared, the Port is in an idle state.
  147. */
  148. if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
  149. SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
  150. /*
  151. * System software places a Port into the idle state by
  152. * clearing P#CMD.ST and waiting for P#CMD.CR to return
  153. * 0 when read.
  154. */
  155. tmp &= ~SATA_PORT_CMD_ST;
  156. writel_with_flush(tmp, &port_mmio->cmd);
  157. /*
  158. * spec says 500 msecs for each bit, so
  159. * this is slightly incorrect.
  160. */
  161. mdelay(500);
  162. timeout = 1000;
  163. while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR)
  164. && --timeout)
  165. ;
  166. if (timeout <= 0) {
  167. debug("port reset failed (0x%x)\n", tmp);
  168. return -1;
  169. }
  170. }
  171. /* Spin-up device */
  172. tmp = readl(&port_mmio->cmd);
  173. writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd);
  174. /* Wait for spin-up to finish */
  175. timeout = 1000;
  176. while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD)
  177. && --timeout)
  178. ;
  179. if (timeout <= 0) {
  180. debug("Spin-Up can't finish!\n");
  181. return -1;
  182. }
  183. for (j = 0; j < 100; ++j) {
  184. mdelay(10);
  185. tmp = readl(&port_mmio->ssts);
  186. if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
  187. ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
  188. break;
  189. }
  190. /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
  191. timeout = 1000;
  192. while (!(readl(&port_mmio->serr) | SATA_PORT_SERR_DIAG_X)
  193. && --timeout)
  194. ;
  195. if (timeout <= 0) {
  196. debug("Can't find DIAG_X set!\n");
  197. return -1;
  198. }
  199. /*
  200. * For each implemented Port, clear the P#SERR
  201. * register, by writing ones to each implemented\
  202. * bit location.
  203. */
  204. tmp = readl(&port_mmio->serr);
  205. debug("P#SERR 0x%x\n",
  206. tmp);
  207. writel(tmp, &port_mmio->serr);
  208. /* Ack any pending irq events for this port */
  209. tmp = readl(&host_mmio->is);
  210. debug("IS 0x%x\n", tmp);
  211. if (tmp)
  212. writel(tmp, &host_mmio->is);
  213. writel(1 << i, &host_mmio->is);
  214. /* set irq mask (enables interrupts) */
  215. writel(DEF_PORT_IRQ, &port_mmio->ie);
  216. /* register linkup ports */
  217. tmp = readl(&port_mmio->ssts);
  218. debug("Port %d status: 0x%x\n", i, tmp);
  219. if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
  220. uc_priv->link_port_map |= (0x01 << i);
  221. }
  222. tmp = readl(&host_mmio->ghc);
  223. debug("GHC 0x%x\n", tmp);
  224. writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc);
  225. tmp = readl(&host_mmio->ghc);
  226. debug("GHC 0x%x\n", tmp);
  227. return 0;
  228. }
  229. static void ahci_print_info(struct ahci_uc_priv *uc_priv)
  230. {
  231. struct sata_host_regs *host_mmio = uc_priv->mmio_base;
  232. u32 vers, cap, impl, speed;
  233. const char *speed_s;
  234. const char *scc_s;
  235. vers = readl(&host_mmio->vs);
  236. cap = uc_priv->cap;
  237. impl = uc_priv->port_map;
  238. speed = (cap & SATA_HOST_CAP_ISS_MASK)
  239. >> SATA_HOST_CAP_ISS_OFFSET;
  240. if (speed == 1)
  241. speed_s = "1.5";
  242. else if (speed == 2)
  243. speed_s = "3";
  244. else
  245. speed_s = "?";
  246. scc_s = "SATA";
  247. printf("AHCI %02x%02x.%02x%02x "
  248. "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
  249. (vers >> 24) & 0xff,
  250. (vers >> 16) & 0xff,
  251. (vers >> 8) & 0xff,
  252. vers & 0xff,
  253. ((cap >> 8) & 0x1f) + 1,
  254. (cap & 0x1f) + 1,
  255. speed_s,
  256. impl,
  257. scc_s);
  258. printf("flags: "
  259. "%s%s%s%s%s%s"
  260. "%s%s%s%s%s%s%s\n",
  261. cap & (1 << 31) ? "64bit " : "",
  262. cap & (1 << 30) ? "ncq " : "",
  263. cap & (1 << 28) ? "ilck " : "",
  264. cap & (1 << 27) ? "stag " : "",
  265. cap & (1 << 26) ? "pm " : "",
  266. cap & (1 << 25) ? "led " : "",
  267. cap & (1 << 24) ? "clo " : "",
  268. cap & (1 << 19) ? "nz " : "",
  269. cap & (1 << 18) ? "only " : "",
  270. cap & (1 << 17) ? "pmp " : "",
  271. cap & (1 << 15) ? "pio " : "",
  272. cap & (1 << 14) ? "slum " : "",
  273. cap & (1 << 13) ? "part " : "");
  274. }
  275. static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
  276. unsigned char *buf, int buf_len)
  277. {
  278. struct ahci_ioports *pp = &uc_priv->port[port];
  279. struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
  280. u32 sg_count, max_bytes;
  281. int i;
  282. max_bytes = MAX_DATA_BYTES_PER_SG;
  283. sg_count = ((buf_len - 1) / max_bytes) + 1;
  284. if (sg_count > AHCI_MAX_SG) {
  285. printf("Error:Too much sg!\n");
  286. return -1;
  287. }
  288. for (i = 0; i < sg_count; i++) {
  289. ahci_sg->addr =
  290. cpu_to_le32((u32)buf + i * max_bytes);
  291. ahci_sg->addr_hi = 0;
  292. ahci_sg->flags_size = cpu_to_le32(0x3fffff &
  293. (buf_len < max_bytes
  294. ? (buf_len - 1)
  295. : (max_bytes - 1)));
  296. ahci_sg++;
  297. buf_len -= max_bytes;
  298. }
  299. return sg_count;
  300. }
  301. static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
  302. {
  303. struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
  304. AHCI_CMD_SLOT_SZ * cmd_slot);
  305. memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
  306. cmd_hdr->opts = cpu_to_le32(opts);
  307. cmd_hdr->status = 0;
  308. pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
  309. #ifdef CONFIG_PHYS_64BIT
  310. pp->cmd_slot->tbl_addr_hi =
  311. cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
  312. #endif
  313. }
  314. #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
  315. static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port,
  316. struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len,
  317. s32 is_write)
  318. {
  319. struct ahci_ioports *pp = &uc_priv->port[port];
  320. struct sata_port_regs *port_mmio = pp->port_mmio;
  321. u32 opts;
  322. int sg_count = 0, cmd_slot = 0;
  323. cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci));
  324. if (32 == cmd_slot) {
  325. printf("Can't find empty command slot!\n");
  326. return 0;
  327. }
  328. /* Check xfer length */
  329. if (buf_len > MAX_BYTES_PER_TRANS) {
  330. printf("Max transfer length is %dB\n\r",
  331. MAX_BYTES_PER_TRANS);
  332. return 0;
  333. }
  334. memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
  335. if (buf && buf_len)
  336. sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
  337. opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
  338. if (is_write) {
  339. opts |= 0x40;
  340. flush_cache((ulong)buf, buf_len);
  341. }
  342. ahci_fill_cmd_slot(pp, cmd_slot, opts);
  343. flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
  344. writel_with_flush(1 << cmd_slot, &port_mmio->ci);
  345. if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000,
  346. 0x1 << cmd_slot)) {
  347. printf("timeout exit!\n");
  348. return -1;
  349. }
  350. invalidate_dcache_range((int)(pp->cmd_slot),
  351. (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
  352. debug("ahci_exec_ata_cmd: %d byte transferred.\n",
  353. pp->cmd_slot->status);
  354. if (!is_write)
  355. invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
  356. return buf_len;
  357. }
  358. static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port)
  359. {
  360. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  361. struct sata_fis_h2d *cfis = &h2d;
  362. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  363. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  364. cfis->pm_port_c = 1 << 7;
  365. cfis->command = ATA_CMD_SET_FEATURES;
  366. cfis->features = SETFEATURES_XFER;
  367. cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e;
  368. ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD);
  369. }
  370. static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
  371. {
  372. struct ahci_ioports *pp = &uc_priv->port[port];
  373. struct sata_port_regs *port_mmio = pp->port_mmio;
  374. u32 port_status;
  375. u32 mem;
  376. int timeout = 10000000;
  377. debug("Enter start port: %d\n", port);
  378. port_status = readl(&port_mmio->ssts);
  379. debug("Port %d status: %x\n", port, port_status);
  380. if ((port_status & 0xf) != 0x03) {
  381. printf("No Link on this port!\n");
  382. return -1;
  383. }
  384. mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
  385. if (!mem) {
  386. free(pp);
  387. printf("No mem for table!\n");
  388. return -ENOMEM;
  389. }
  390. mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
  391. memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
  392. /*
  393. * First item in chunk of DMA memory: 32-slot command table,
  394. * 32 bytes each in size
  395. */
  396. pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
  397. debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
  398. mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
  399. /*
  400. * Second item: Received-FIS area, 256-Byte aligned
  401. */
  402. pp->rx_fis = mem;
  403. mem += AHCI_RX_FIS_SZ;
  404. /*
  405. * Third item: data area for storing a single command
  406. * and its scatter-gather table
  407. */
  408. pp->cmd_tbl = mem;
  409. debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl);
  410. mem += AHCI_CMD_TBL_HDR;
  411. writel_with_flush(0x00004444, &port_mmio->dmacr);
  412. pp->cmd_tbl_sg = (struct ahci_sg *)mem;
  413. writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb);
  414. writel_with_flush(pp->rx_fis, &port_mmio->fb);
  415. /* Enable FRE */
  416. writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)),
  417. &port_mmio->cmd);
  418. /* Wait device ready */
  419. while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR |
  420. SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
  421. && --timeout)
  422. ;
  423. if (timeout <= 0) {
  424. debug("Device not ready for BSY, DRQ and"
  425. "ERR in TFD!\n");
  426. return -1;
  427. }
  428. writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
  429. PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
  430. PORT_CMD_START, &port_mmio->cmd);
  431. debug("Exit start port %d\n", port);
  432. return 0;
  433. }
  434. static void dwc_ahsata_print_info(struct blk_desc *pdev)
  435. {
  436. printf("SATA Device Info:\n\r");
  437. printf("S/N: %s\n\rProduct model number: %s\n\r"
  438. "Firmware version: %s\n\rCapacity: " LBAFU " sectors\n\r",
  439. pdev->product, pdev->vendor, pdev->revision, pdev->lba);
  440. }
  441. static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id)
  442. {
  443. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  444. struct sata_fis_h2d *cfis = &h2d;
  445. u8 port = uc_priv->hard_port_no;
  446. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  447. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  448. cfis->pm_port_c = 0x80; /* is command */
  449. cfis->command = ATA_CMD_ID_ATA;
  450. ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2,
  451. READ_CMD);
  452. ata_swap_buf_le16(id, ATA_ID_WORDS);
  453. }
  454. static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id)
  455. {
  456. uc_priv->pio_mask = id[ATA_ID_PIO_MODES];
  457. uc_priv->udma_mask = id[ATA_ID_UDMA_MODES];
  458. debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask);
  459. }
  460. static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start,
  461. u32 blkcnt, u8 *buffer, int is_write)
  462. {
  463. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  464. struct sata_fis_h2d *cfis = &h2d;
  465. u8 port = uc_priv->hard_port_no;
  466. u32 block;
  467. block = start;
  468. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  469. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  470. cfis->pm_port_c = 0x80; /* is command */
  471. cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
  472. cfis->device = ATA_LBA;
  473. cfis->device |= (block >> 24) & 0xf;
  474. cfis->lba_high = (block >> 16) & 0xff;
  475. cfis->lba_mid = (block >> 8) & 0xff;
  476. cfis->lba_low = block & 0xff;
  477. cfis->sector_count = (u8)(blkcnt & 0xff);
  478. if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
  479. ATA_SECT_SIZE * blkcnt, is_write) > 0)
  480. return blkcnt;
  481. else
  482. return 0;
  483. }
  484. static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv)
  485. {
  486. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  487. struct sata_fis_h2d *cfis = &h2d;
  488. u8 port = uc_priv->hard_port_no;
  489. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  490. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  491. cfis->pm_port_c = 0x80; /* is command */
  492. cfis->command = ATA_CMD_FLUSH;
  493. ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
  494. }
  495. static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start,
  496. lbaint_t blkcnt, u8 *buffer, int is_write)
  497. {
  498. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  499. struct sata_fis_h2d *cfis = &h2d;
  500. u8 port = uc_priv->hard_port_no;
  501. u64 block;
  502. block = (u64)start;
  503. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  504. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  505. cfis->pm_port_c = 0x80; /* is command */
  506. cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
  507. : ATA_CMD_READ_EXT;
  508. cfis->lba_high_exp = (block >> 40) & 0xff;
  509. cfis->lba_mid_exp = (block >> 32) & 0xff;
  510. cfis->lba_low_exp = (block >> 24) & 0xff;
  511. cfis->lba_high = (block >> 16) & 0xff;
  512. cfis->lba_mid = (block >> 8) & 0xff;
  513. cfis->lba_low = block & 0xff;
  514. cfis->device = ATA_LBA;
  515. cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
  516. cfis->sector_count = blkcnt & 0xff;
  517. if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
  518. ATA_SECT_SIZE * blkcnt, is_write) > 0)
  519. return blkcnt;
  520. else
  521. return 0;
  522. }
  523. static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv)
  524. {
  525. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  526. struct sata_fis_h2d *cfis = &h2d;
  527. u8 port = uc_priv->hard_port_no;
  528. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  529. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  530. cfis->pm_port_c = 0x80; /* is command */
  531. cfis->command = ATA_CMD_FLUSH_EXT;
  532. ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
  533. }
  534. static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id)
  535. {
  536. if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
  537. uc_priv->flags |= SATA_FLAG_WCACHE;
  538. if (ata_id_has_flush(id))
  539. uc_priv->flags |= SATA_FLAG_FLUSH;
  540. if (ata_id_has_flush_ext(id))
  541. uc_priv->flags |= SATA_FLAG_FLUSH_EXT;
  542. }
  543. static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr,
  544. lbaint_t blkcnt, const void *buffer,
  545. int is_write)
  546. {
  547. u32 start, blks;
  548. u8 *addr;
  549. int max_blks;
  550. start = blknr;
  551. blks = blkcnt;
  552. addr = (u8 *)buffer;
  553. max_blks = ATA_MAX_SECTORS_LBA48;
  554. do {
  555. if (blks > max_blks) {
  556. if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start,
  557. max_blks, addr,
  558. is_write))
  559. return 0;
  560. start += max_blks;
  561. blks -= max_blks;
  562. addr += ATA_SECT_SIZE * max_blks;
  563. } else {
  564. if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks,
  565. addr, is_write))
  566. return 0;
  567. start += blks;
  568. blks = 0;
  569. addr += ATA_SECT_SIZE * blks;
  570. }
  571. } while (blks != 0);
  572. return blkcnt;
  573. }
  574. static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr,
  575. lbaint_t blkcnt, const void *buffer,
  576. int is_write)
  577. {
  578. u32 start, blks;
  579. u8 *addr;
  580. int max_blks;
  581. start = blknr;
  582. blks = blkcnt;
  583. addr = (u8 *)buffer;
  584. max_blks = ATA_MAX_SECTORS;
  585. do {
  586. if (blks > max_blks) {
  587. if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start,
  588. max_blks, addr,
  589. is_write))
  590. return 0;
  591. start += max_blks;
  592. blks -= max_blks;
  593. addr += ATA_SECT_SIZE * max_blks;
  594. } else {
  595. if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks,
  596. addr, is_write))
  597. return 0;
  598. start += blks;
  599. blks = 0;
  600. addr += ATA_SECT_SIZE * blks;
  601. }
  602. } while (blks != 0);
  603. return blkcnt;
  604. }
  605. static int dwc_ahci_start_ports(struct ahci_uc_priv *uc_priv)
  606. {
  607. u32 linkmap;
  608. int i;
  609. linkmap = uc_priv->link_port_map;
  610. if (0 == linkmap) {
  611. printf("No port device detected!\n");
  612. return -ENXIO;
  613. }
  614. for (i = 0; i < uc_priv->n_ports; i++) {
  615. if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
  616. if (ahci_port_start(uc_priv, (u8)i)) {
  617. printf("Can not start port %d\n", i);
  618. return 1;
  619. }
  620. uc_priv->hard_port_no = i;
  621. break;
  622. }
  623. }
  624. return 0;
  625. }
  626. static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv,
  627. struct blk_desc *pdev)
  628. {
  629. u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
  630. u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
  631. u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
  632. u8 port = uc_priv->hard_port_no;
  633. ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS);
  634. /* Identify device to get information */
  635. dwc_ahsata_identify(uc_priv, id);
  636. /* Serial number */
  637. ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
  638. memcpy(pdev->product, serial, sizeof(serial));
  639. /* Firmware version */
  640. ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
  641. memcpy(pdev->revision, firmware, sizeof(firmware));
  642. /* Product model */
  643. ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
  644. memcpy(pdev->vendor, product, sizeof(product));
  645. /* Total sectors */
  646. pdev->lba = ata_id_n_sectors(id);
  647. pdev->type = DEV_TYPE_HARDDISK;
  648. pdev->blksz = ATA_SECT_SIZE;
  649. pdev->lun = 0;
  650. /* Check if support LBA48 */
  651. if (ata_id_has_lba48(id)) {
  652. pdev->lba48 = 1;
  653. debug("Device support LBA48\n\r");
  654. }
  655. /* Get the NCQ queue depth from device */
  656. uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK);
  657. uc_priv->flags |= ata_id_queue_depth(id);
  658. /* Get the xfer mode from device */
  659. dwc_ahsata_xfer_mode(uc_priv, id);
  660. /* Get the write cache status from device */
  661. dwc_ahsata_init_wcache(uc_priv, id);
  662. /* Set the xfer mode to highest speed */
  663. ahci_set_feature(uc_priv, port);
  664. dwc_ahsata_print_info(pdev);
  665. return 0;
  666. }
  667. /*
  668. * SATA interface between low level driver and command layer
  669. */
  670. static ulong sata_read_common(struct ahci_uc_priv *uc_priv,
  671. struct blk_desc *desc, ulong blknr,
  672. lbaint_t blkcnt, void *buffer)
  673. {
  674. u32 rc;
  675. if (desc->lba48)
  676. rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
  677. READ_CMD);
  678. else
  679. rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
  680. READ_CMD);
  681. return rc;
  682. }
  683. static ulong sata_write_common(struct ahci_uc_priv *uc_priv,
  684. struct blk_desc *desc, ulong blknr,
  685. lbaint_t blkcnt, const void *buffer)
  686. {
  687. u32 rc;
  688. u32 flags = uc_priv->flags;
  689. if (desc->lba48) {
  690. rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
  691. WRITE_CMD);
  692. if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH_EXT))
  693. dwc_ahsata_flush_cache_ext(uc_priv);
  694. } else {
  695. rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
  696. WRITE_CMD);
  697. if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH))
  698. dwc_ahsata_flush_cache(uc_priv);
  699. }
  700. return rc;
  701. }
  702. #if !CONFIG_IS_ENABLED(AHCI)
  703. static int ahci_init_one(int pdev)
  704. {
  705. int rc;
  706. struct ahci_uc_priv *uc_priv = NULL;
  707. uc_priv = malloc(sizeof(struct ahci_uc_priv));
  708. memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
  709. uc_priv->dev = pdev;
  710. uc_priv->host_flags = ATA_FLAG_SATA
  711. | ATA_FLAG_NO_LEGACY
  712. | ATA_FLAG_MMIO
  713. | ATA_FLAG_PIO_DMA
  714. | ATA_FLAG_NO_ATAPI;
  715. uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
  716. /* initialize adapter */
  717. rc = ahci_host_init(uc_priv);
  718. if (rc)
  719. goto err_out;
  720. ahci_print_info(uc_priv);
  721. /* Save the uc_private struct to block device struct */
  722. sata_dev_desc[pdev].priv = uc_priv;
  723. return 0;
  724. err_out:
  725. return rc;
  726. }
  727. int init_sata(int dev)
  728. {
  729. struct ahci_uc_priv *uc_priv = NULL;
  730. #if defined(CONFIG_MX6)
  731. if (!is_mx6dq() && !is_mx6dqp())
  732. return 1;
  733. #endif
  734. if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
  735. printf("The sata index %d is out of ranges\n\r", dev);
  736. return -1;
  737. }
  738. ahci_init_one(dev);
  739. uc_priv = sata_dev_desc[dev].priv;
  740. return dwc_ahci_start_ports(uc_priv) ? 1 : 0;
  741. }
  742. int reset_sata(int dev)
  743. {
  744. struct ahci_uc_priv *uc_priv;
  745. struct sata_host_regs *host_mmio;
  746. if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
  747. printf("The sata index %d is out of ranges\n\r", dev);
  748. return -1;
  749. }
  750. uc_priv = sata_dev_desc[dev].priv;
  751. if (NULL == uc_priv)
  752. /* not initialized, so nothing to reset */
  753. return 0;
  754. host_mmio = uc_priv->mmio_base;
  755. setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
  756. while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
  757. udelay(100);
  758. return 0;
  759. }
  760. int sata_port_status(int dev, int port)
  761. {
  762. struct sata_port_regs *port_mmio;
  763. struct ahci_uc_priv *uc_priv = NULL;
  764. if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
  765. return -EINVAL;
  766. if (sata_dev_desc[dev].priv == NULL)
  767. return -ENODEV;
  768. uc_priv = sata_dev_desc[dev].priv;
  769. port_mmio = uc_priv->port[port].port_mmio;
  770. return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK;
  771. }
  772. /*
  773. * SATA interface between low level driver and command layer
  774. */
  775. ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
  776. {
  777. struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
  778. return sata_read_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
  779. buffer);
  780. }
  781. ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
  782. {
  783. struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
  784. return sata_write_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
  785. buffer);
  786. }
  787. int scan_sata(int dev)
  788. {
  789. struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
  790. struct blk_desc *pdev = &sata_dev_desc[dev];
  791. return dwc_ahsata_scan_common(uc_priv, pdev);
  792. }
  793. #endif /* CONFIG_IS_ENABLED(AHCI) */
  794. #if CONFIG_IS_ENABLED(AHCI)
  795. int dwc_ahsata_port_status(struct udevice *dev, int port)
  796. {
  797. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  798. struct sata_port_regs *port_mmio;
  799. port_mmio = uc_priv->port[port].port_mmio;
  800. return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK ? 0 : -ENXIO;
  801. }
  802. int dwc_ahsata_bus_reset(struct udevice *dev)
  803. {
  804. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  805. struct sata_host_regs *host_mmio = uc_priv->mmio_base;
  806. setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
  807. while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
  808. udelay(100);
  809. return 0;
  810. }
  811. int dwc_ahsata_scan(struct udevice *dev)
  812. {
  813. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  814. struct blk_desc *desc;
  815. struct udevice *blk;
  816. int ret;
  817. /*
  818. * Create only one block device and do detection
  819. * to make sure that there won't be a lot of
  820. * block devices created
  821. */
  822. device_find_first_child(dev, &blk);
  823. if (!blk) {
  824. ret = blk_create_devicef(dev, "dwc_ahsata_blk", "blk",
  825. IF_TYPE_SATA, -1, 512, 0, &blk);
  826. if (ret) {
  827. debug("Can't create device\n");
  828. return ret;
  829. }
  830. }
  831. desc = dev_get_uclass_platdata(blk);
  832. ret = dwc_ahsata_scan_common(uc_priv, desc);
  833. if (ret) {
  834. debug("%s: Failed to scan bus\n", __func__);
  835. return ret;
  836. }
  837. return 0;
  838. }
  839. int dwc_ahsata_probe(struct udevice *dev)
  840. {
  841. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  842. int ret;
  843. #if defined(CONFIG_MX6)
  844. setup_sata();
  845. #endif
  846. uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  847. ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
  848. uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev);
  849. /* initialize adapter */
  850. ret = ahci_host_init(uc_priv);
  851. if (ret)
  852. return ret;
  853. ahci_print_info(uc_priv);
  854. return dwc_ahci_start_ports(uc_priv);
  855. }
  856. static ulong dwc_ahsata_read(struct udevice *blk, lbaint_t blknr,
  857. lbaint_t blkcnt, void *buffer)
  858. {
  859. struct blk_desc *desc = dev_get_uclass_platdata(blk);
  860. struct udevice *dev = dev_get_parent(blk);
  861. struct ahci_uc_priv *uc_priv;
  862. uc_priv = dev_get_uclass_priv(dev);
  863. return sata_read_common(uc_priv, desc, blknr, blkcnt, buffer);
  864. }
  865. static ulong dwc_ahsata_write(struct udevice *blk, lbaint_t blknr,
  866. lbaint_t blkcnt, const void *buffer)
  867. {
  868. struct blk_desc *desc = dev_get_uclass_platdata(blk);
  869. struct udevice *dev = dev_get_parent(blk);
  870. struct ahci_uc_priv *uc_priv;
  871. uc_priv = dev_get_uclass_priv(dev);
  872. return sata_write_common(uc_priv, desc, blknr, blkcnt, buffer);
  873. }
  874. static const struct blk_ops dwc_ahsata_blk_ops = {
  875. .read = dwc_ahsata_read,
  876. .write = dwc_ahsata_write,
  877. };
  878. U_BOOT_DRIVER(dwc_ahsata_blk) = {
  879. .name = "dwc_ahsata_blk",
  880. .id = UCLASS_BLK,
  881. .ops = &dwc_ahsata_blk_ops,
  882. };
  883. #if CONFIG_IS_ENABLED(DWC_AHSATA_AHCI)
  884. struct ahci_ops dwc_ahsata_ahci_ops = {
  885. .port_status = dwc_ahsata_port_status,
  886. .reset = dwc_ahsata_bus_reset,
  887. .scan = dwc_ahsata_scan,
  888. };
  889. static const struct udevice_id dwc_ahsata_ahci_ids[] = {
  890. { .compatible = "fsl,imx6q-ahci" },
  891. { }
  892. };
  893. U_BOOT_DRIVER(dwc_ahsata_ahci) = {
  894. .name = "dwc_ahsata_ahci",
  895. .id = UCLASS_AHCI,
  896. .of_match = dwc_ahsata_ahci_ids,
  897. .ops = &dwc_ahsata_ahci_ops,
  898. .probe = dwc_ahsata_probe,
  899. };
  900. #endif
  901. #endif