ahci_sunxi.c 2.7 KB

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  1. #include <common.h>
  2. #include <ahci.h>
  3. #include <dm.h>
  4. #include <scsi.h>
  5. #include <errno.h>
  6. #include <asm/io.h>
  7. #include <asm/gpio.h>
  8. #define AHCI_PHYCS0R 0x00c0
  9. #define AHCI_PHYCS1R 0x00c4
  10. #define AHCI_PHYCS2R 0x00c8
  11. #define AHCI_RWCR 0x00fc
  12. /* This magic PHY initialisation was taken from the Allwinner releases
  13. * and Linux driver, but is completely undocumented.
  14. */
  15. static int sunxi_ahci_phy_init(u8 *reg_base)
  16. {
  17. u32 reg_val;
  18. int timeout;
  19. writel(0, reg_base + AHCI_RWCR);
  20. mdelay(5);
  21. setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19);
  22. clrsetbits_le32(reg_base + AHCI_PHYCS0R,
  23. (0x7 << 24),
  24. (0x5 << 24) | (0x1 << 23) | (0x1 << 18));
  25. clrsetbits_le32(reg_base + AHCI_PHYCS1R,
  26. (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
  27. (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
  28. setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15));
  29. clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19));
  30. clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20));
  31. clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5));
  32. mdelay(5);
  33. setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19));
  34. timeout = 250; /* Power up takes approx 50 us */
  35. for (;;) {
  36. reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28);
  37. if (reg_val == (0x2 << 28))
  38. break;
  39. if (--timeout == 0) {
  40. printf("AHCI PHY power up failed.\n");
  41. return -EIO;
  42. }
  43. udelay(1);
  44. };
  45. setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24));
  46. timeout = 100; /* Calibration takes approx 10 us */
  47. for (;;) {
  48. reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24);
  49. if (reg_val == 0x0)
  50. break;
  51. if (--timeout == 0) {
  52. printf("AHCI PHY calibration failed.\n");
  53. return -EIO;
  54. }
  55. udelay(1);
  56. }
  57. mdelay(15);
  58. writel(0x7, reg_base + AHCI_RWCR);
  59. return 0;
  60. }
  61. static int sunxi_sata_probe(struct udevice *dev)
  62. {
  63. ulong base;
  64. u8 *reg;
  65. int ret;
  66. base = dev_read_addr(dev);
  67. if (base == FDT_ADDR_T_NONE) {
  68. debug("%s: Failed to find address (err=%d\n)", __func__, ret);
  69. return -EINVAL;
  70. }
  71. reg = (u8 *)base;
  72. ret = sunxi_ahci_phy_init(reg);
  73. if (ret) {
  74. debug("%s: Failed to init phy (err=%d\n)", __func__, ret);
  75. return ret;
  76. }
  77. ret = ahci_probe_scsi(dev, base);
  78. if (ret) {
  79. debug("%s: Failed to probe (err=%d\n)", __func__, ret);
  80. return ret;
  81. }
  82. return 0;
  83. }
  84. static int sunxi_sata_bind(struct udevice *dev)
  85. {
  86. struct udevice *scsi_dev;
  87. int ret;
  88. ret = ahci_bind_scsi(dev, &scsi_dev);
  89. if (ret) {
  90. debug("%s: Failed to bind (err=%d\n)", __func__, ret);
  91. return ret;
  92. }
  93. return 0;
  94. }
  95. static const struct udevice_id sunxi_ahci_ids[] = {
  96. { .compatible = "allwinner,sun4i-a10-ahci" },
  97. { .compatible = "allwinner,sun8i-r40-ahci" },
  98. { }
  99. };
  100. U_BOOT_DRIVER(ahci_sunxi_drv) = {
  101. .name = "ahci_sunxi",
  102. .id = UCLASS_AHCI,
  103. .of_match = sunxi_ahci_ids,
  104. .bind = sunxi_sata_bind,
  105. .probe = sunxi_sata_probe,
  106. };