ahci.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006.
  4. * Author: Jason Jin<Jason.jin@freescale.com>
  5. * Zhang Wei<wei.zhang@freescale.com>
  6. *
  7. * with the reference on libata and ahci drvier in kernel
  8. *
  9. * This driver provides a SCSI interface to SATA.
  10. */
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <command.h>
  14. #include <dm.h>
  15. #include <pci.h>
  16. #include <asm/processor.h>
  17. #include <linux/errno.h>
  18. #include <asm/io.h>
  19. #include <malloc.h>
  20. #include <memalign.h>
  21. #include <pci.h>
  22. #include <scsi.h>
  23. #include <libata.h>
  24. #include <linux/ctype.h>
  25. #include <ahci.h>
  26. #include <dm/device-internal.h>
  27. #include <dm/lists.h>
  28. static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);
  29. #ifndef CONFIG_DM_SCSI
  30. struct ahci_uc_priv *probe_ent = NULL;
  31. #endif
  32. #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
  33. /*
  34. * Some controllers limit number of blocks they can read/write at once.
  35. * Contemporary SSD devices work much faster if the read/write size is aligned
  36. * to a power of 2. Let's set default to 128 and allowing to be overwritten if
  37. * needed.
  38. */
  39. #ifndef MAX_SATA_BLOCKS_READ_WRITE
  40. #define MAX_SATA_BLOCKS_READ_WRITE 0x80
  41. #endif
  42. /* Maximum timeouts for each event */
  43. #define WAIT_MS_SPINUP 20000
  44. #define WAIT_MS_DATAIO 10000
  45. #define WAIT_MS_FLUSH 5000
  46. #define WAIT_MS_LINKUP 200
  47. #define AHCI_CAP_S64A BIT(31)
  48. __weak void __iomem *ahci_port_base(void __iomem *base, u32 port)
  49. {
  50. return base + 0x100 + (port * 0x80);
  51. }
  52. #define msleep(a) udelay(a * 1000)
  53. static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
  54. {
  55. const unsigned long start = begin;
  56. const unsigned long end = start + len;
  57. debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
  58. flush_dcache_range(start, end);
  59. }
  60. /*
  61. * SATA controller DMAs to physical RAM. Ensure data from the
  62. * controller is invalidated from dcache; next access comes from
  63. * physical RAM.
  64. */
  65. static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
  66. {
  67. const unsigned long start = begin;
  68. const unsigned long end = start + len;
  69. debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
  70. invalidate_dcache_range(start, end);
  71. }
  72. /*
  73. * Ensure data for SATA controller is flushed out of dcache and
  74. * written to physical memory.
  75. */
  76. static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
  77. {
  78. ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
  79. AHCI_PORT_PRIV_DMA_SZ);
  80. }
  81. static int waiting_for_cmd_completed(void __iomem *offset,
  82. int timeout_msec,
  83. u32 sign)
  84. {
  85. int i;
  86. u32 status;
  87. for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
  88. msleep(1);
  89. return (i < timeout_msec) ? 0 : -1;
  90. }
  91. int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, u8 port)
  92. {
  93. u32 tmp;
  94. int j = 0;
  95. void __iomem *port_mmio = uc_priv->port[port].port_mmio;
  96. /*
  97. * Bring up SATA link.
  98. * SATA link bringup time is usually less than 1 ms; only very
  99. * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
  100. */
  101. while (j < WAIT_MS_LINKUP) {
  102. tmp = readl(port_mmio + PORT_SCR_STAT);
  103. tmp &= PORT_SCR_STAT_DET_MASK;
  104. if (tmp == PORT_SCR_STAT_DET_PHYRDY)
  105. return 0;
  106. udelay(1000);
  107. j++;
  108. }
  109. return 1;
  110. }
  111. #ifdef CONFIG_SUNXI_AHCI
  112. /* The sunxi AHCI controller requires this undocumented setup */
  113. static void sunxi_dma_init(void __iomem *port_mmio)
  114. {
  115. clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
  116. }
  117. #endif
  118. int ahci_reset(void __iomem *base)
  119. {
  120. int i = 1000;
  121. u32 __iomem *host_ctl_reg = base + HOST_CTL;
  122. u32 tmp = readl(host_ctl_reg); /* global controller reset */
  123. if ((tmp & HOST_RESET) == 0)
  124. writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
  125. /*
  126. * reset must complete within 1 second, or
  127. * the hardware should be considered fried.
  128. */
  129. do {
  130. udelay(1000);
  131. tmp = readl(host_ctl_reg);
  132. i--;
  133. } while ((i > 0) && (tmp & HOST_RESET));
  134. if (i == 0) {
  135. printf("controller reset failed (0x%x)\n", tmp);
  136. return -1;
  137. }
  138. return 0;
  139. }
  140. static int ahci_host_init(struct ahci_uc_priv *uc_priv)
  141. {
  142. #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
  143. # ifdef CONFIG_DM_PCI
  144. struct udevice *dev = uc_priv->dev;
  145. struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
  146. # else
  147. pci_dev_t pdev = uc_priv->dev;
  148. unsigned short vendor;
  149. # endif
  150. u16 tmp16;
  151. #endif
  152. void __iomem *mmio = uc_priv->mmio_base;
  153. u32 tmp, cap_save, cmd;
  154. int i, j, ret;
  155. void __iomem *port_mmio;
  156. u32 port_map;
  157. debug("ahci_host_init: start\n");
  158. cap_save = readl(mmio + HOST_CAP);
  159. cap_save &= ((1 << 28) | (1 << 17));
  160. cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
  161. ret = ahci_reset(uc_priv->mmio_base);
  162. if (ret)
  163. return ret;
  164. writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
  165. writel(cap_save, mmio + HOST_CAP);
  166. writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
  167. #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
  168. # ifdef CONFIG_DM_PCI
  169. if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
  170. u16 tmp16;
  171. dm_pci_read_config16(dev, 0x92, &tmp16);
  172. dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
  173. }
  174. # else
  175. pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
  176. if (vendor == PCI_VENDOR_ID_INTEL) {
  177. u16 tmp16;
  178. pci_read_config_word(pdev, 0x92, &tmp16);
  179. tmp16 |= 0xf;
  180. pci_write_config_word(pdev, 0x92, tmp16);
  181. }
  182. # endif
  183. #endif
  184. uc_priv->cap = readl(mmio + HOST_CAP);
  185. uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);
  186. port_map = uc_priv->port_map;
  187. uc_priv->n_ports = (uc_priv->cap & 0x1f) + 1;
  188. debug("cap 0x%x port_map 0x%x n_ports %d\n",
  189. uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
  190. #if !defined(CONFIG_DM_SCSI)
  191. if (uc_priv->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
  192. uc_priv->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
  193. #endif
  194. for (i = 0; i < uc_priv->n_ports; i++) {
  195. if (!(port_map & (1 << i)))
  196. continue;
  197. uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);
  198. port_mmio = (u8 *)uc_priv->port[i].port_mmio;
  199. /* make sure port is not active */
  200. tmp = readl(port_mmio + PORT_CMD);
  201. if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
  202. PORT_CMD_FIS_RX | PORT_CMD_START)) {
  203. debug("Port %d is active. Deactivating.\n", i);
  204. tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
  205. PORT_CMD_FIS_RX | PORT_CMD_START);
  206. writel_with_flush(tmp, port_mmio + PORT_CMD);
  207. /* spec says 500 msecs for each bit, so
  208. * this is slightly incorrect.
  209. */
  210. msleep(500);
  211. }
  212. #ifdef CONFIG_SUNXI_AHCI
  213. sunxi_dma_init(port_mmio);
  214. #endif
  215. /* Add the spinup command to whatever mode bits may
  216. * already be on in the command register.
  217. */
  218. cmd = readl(port_mmio + PORT_CMD);
  219. cmd |= PORT_CMD_SPIN_UP;
  220. writel_with_flush(cmd, port_mmio + PORT_CMD);
  221. /* Bring up SATA link. */
  222. ret = ahci_link_up(uc_priv, i);
  223. if (ret) {
  224. printf("SATA link %d timeout.\n", i);
  225. continue;
  226. } else {
  227. debug("SATA link ok.\n");
  228. }
  229. /* Clear error status */
  230. tmp = readl(port_mmio + PORT_SCR_ERR);
  231. if (tmp)
  232. writel(tmp, port_mmio + PORT_SCR_ERR);
  233. debug("Spinning up device on SATA port %d... ", i);
  234. j = 0;
  235. while (j < WAIT_MS_SPINUP) {
  236. tmp = readl(port_mmio + PORT_TFDATA);
  237. if (!(tmp & (ATA_BUSY | ATA_DRQ)))
  238. break;
  239. udelay(1000);
  240. tmp = readl(port_mmio + PORT_SCR_STAT);
  241. tmp &= PORT_SCR_STAT_DET_MASK;
  242. if (tmp == PORT_SCR_STAT_DET_PHYRDY)
  243. break;
  244. j++;
  245. }
  246. tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
  247. if (tmp == PORT_SCR_STAT_DET_COMINIT) {
  248. debug("SATA link %d down (COMINIT received), retrying...\n", i);
  249. i--;
  250. continue;
  251. }
  252. printf("Target spinup took %d ms.\n", j);
  253. if (j == WAIT_MS_SPINUP)
  254. debug("timeout.\n");
  255. else
  256. debug("ok.\n");
  257. tmp = readl(port_mmio + PORT_SCR_ERR);
  258. debug("PORT_SCR_ERR 0x%x\n", tmp);
  259. writel(tmp, port_mmio + PORT_SCR_ERR);
  260. /* ack any pending irq events for this port */
  261. tmp = readl(port_mmio + PORT_IRQ_STAT);
  262. debug("PORT_IRQ_STAT 0x%x\n", tmp);
  263. if (tmp)
  264. writel(tmp, port_mmio + PORT_IRQ_STAT);
  265. writel(1 << i, mmio + HOST_IRQ_STAT);
  266. /* register linkup ports */
  267. tmp = readl(port_mmio + PORT_SCR_STAT);
  268. debug("SATA port %d status: 0x%x\n", i, tmp);
  269. if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
  270. uc_priv->link_port_map |= (0x01 << i);
  271. }
  272. tmp = readl(mmio + HOST_CTL);
  273. debug("HOST_CTL 0x%x\n", tmp);
  274. writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
  275. tmp = readl(mmio + HOST_CTL);
  276. debug("HOST_CTL 0x%x\n", tmp);
  277. #if !defined(CONFIG_DM_SCSI)
  278. #ifndef CONFIG_SCSI_AHCI_PLAT
  279. # ifdef CONFIG_DM_PCI
  280. dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
  281. tmp |= PCI_COMMAND_MASTER;
  282. dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
  283. # else
  284. pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
  285. tmp |= PCI_COMMAND_MASTER;
  286. pci_write_config_word(pdev, PCI_COMMAND, tmp16);
  287. # endif
  288. #endif
  289. #endif
  290. return 0;
  291. }
  292. static void ahci_print_info(struct ahci_uc_priv *uc_priv)
  293. {
  294. #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
  295. # if defined(CONFIG_DM_PCI)
  296. struct udevice *dev = uc_priv->dev;
  297. # else
  298. pci_dev_t pdev = uc_priv->dev;
  299. # endif
  300. u16 cc;
  301. #endif
  302. void __iomem *mmio = uc_priv->mmio_base;
  303. u32 vers, cap, cap2, impl, speed;
  304. const char *speed_s;
  305. const char *scc_s;
  306. vers = readl(mmio + HOST_VERSION);
  307. cap = uc_priv->cap;
  308. cap2 = readl(mmio + HOST_CAP2);
  309. impl = uc_priv->port_map;
  310. speed = (cap >> 20) & 0xf;
  311. if (speed == 1)
  312. speed_s = "1.5";
  313. else if (speed == 2)
  314. speed_s = "3";
  315. else if (speed == 3)
  316. speed_s = "6";
  317. else
  318. speed_s = "?";
  319. #if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
  320. scc_s = "SATA";
  321. #else
  322. # ifdef CONFIG_DM_PCI
  323. dm_pci_read_config16(dev, 0x0a, &cc);
  324. # else
  325. pci_read_config_word(pdev, 0x0a, &cc);
  326. # endif
  327. if (cc == 0x0101)
  328. scc_s = "IDE";
  329. else if (cc == 0x0106)
  330. scc_s = "SATA";
  331. else if (cc == 0x0104)
  332. scc_s = "RAID";
  333. else
  334. scc_s = "unknown";
  335. #endif
  336. printf("AHCI %02x%02x.%02x%02x "
  337. "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
  338. (vers >> 24) & 0xff,
  339. (vers >> 16) & 0xff,
  340. (vers >> 8) & 0xff,
  341. vers & 0xff,
  342. ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
  343. printf("flags: "
  344. "%s%s%s%s%s%s%s"
  345. "%s%s%s%s%s%s%s"
  346. "%s%s%s%s%s%s\n",
  347. cap & (1 << 31) ? "64bit " : "",
  348. cap & (1 << 30) ? "ncq " : "",
  349. cap & (1 << 28) ? "ilck " : "",
  350. cap & (1 << 27) ? "stag " : "",
  351. cap & (1 << 26) ? "pm " : "",
  352. cap & (1 << 25) ? "led " : "",
  353. cap & (1 << 24) ? "clo " : "",
  354. cap & (1 << 19) ? "nz " : "",
  355. cap & (1 << 18) ? "only " : "",
  356. cap & (1 << 17) ? "pmp " : "",
  357. cap & (1 << 16) ? "fbss " : "",
  358. cap & (1 << 15) ? "pio " : "",
  359. cap & (1 << 14) ? "slum " : "",
  360. cap & (1 << 13) ? "part " : "",
  361. cap & (1 << 7) ? "ccc " : "",
  362. cap & (1 << 6) ? "ems " : "",
  363. cap & (1 << 5) ? "sxs " : "",
  364. cap2 & (1 << 2) ? "apst " : "",
  365. cap2 & (1 << 1) ? "nvmp " : "",
  366. cap2 & (1 << 0) ? "boh " : "");
  367. }
  368. #if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT)
  369. # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
  370. static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
  371. # else
  372. static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev)
  373. # endif
  374. {
  375. #if !defined(CONFIG_DM_SCSI)
  376. u16 vendor;
  377. #endif
  378. int rc;
  379. uc_priv->dev = dev;
  380. uc_priv->host_flags = ATA_FLAG_SATA
  381. | ATA_FLAG_NO_LEGACY
  382. | ATA_FLAG_MMIO
  383. | ATA_FLAG_PIO_DMA
  384. | ATA_FLAG_NO_ATAPI;
  385. uc_priv->pio_mask = 0x1f;
  386. uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
  387. #if !defined(CONFIG_DM_SCSI)
  388. #ifdef CONFIG_DM_PCI
  389. uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
  390. PCI_REGION_MEM);
  391. /* Take from kernel:
  392. * JMicron-specific fixup:
  393. * make sure we're in AHCI mode
  394. */
  395. dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
  396. if (vendor == 0x197b)
  397. dm_pci_write_config8(dev, 0x41, 0xa1);
  398. #else
  399. uc_priv->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5,
  400. PCI_REGION_MEM);
  401. /* Take from kernel:
  402. * JMicron-specific fixup:
  403. * make sure we're in AHCI mode
  404. */
  405. pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
  406. if (vendor == 0x197b)
  407. pci_write_config_byte(dev, 0x41, 0xa1);
  408. #endif
  409. #else
  410. struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
  411. uc_priv->mmio_base = (void *)plat->base;
  412. #endif
  413. debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base);
  414. /* initialize adapter */
  415. rc = ahci_host_init(uc_priv);
  416. if (rc)
  417. goto err_out;
  418. ahci_print_info(uc_priv);
  419. return 0;
  420. err_out:
  421. return rc;
  422. }
  423. #endif
  424. #define MAX_DATA_BYTE_COUNT (4*1024*1024)
  425. static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
  426. unsigned char *buf, int buf_len)
  427. {
  428. struct ahci_ioports *pp = &(uc_priv->port[port]);
  429. struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
  430. u32 sg_count;
  431. int i;
  432. sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
  433. if (sg_count > AHCI_MAX_SG) {
  434. printf("Error:Too much sg!\n");
  435. return -1;
  436. }
  437. for (i = 0; i < sg_count; i++) {
  438. /* We assume virt=phys */
  439. phys_addr_t pa = (unsigned long)buf + i * MAX_DATA_BYTE_COUNT;
  440. ahci_sg->addr = cpu_to_le32(lower_32_bits(pa));
  441. ahci_sg->addr_hi = cpu_to_le32(upper_32_bits(pa));
  442. if (ahci_sg->addr_hi && !(uc_priv->cap & AHCI_CAP_S64A)) {
  443. printf("Error: DMA address too high\n");
  444. return -1;
  445. }
  446. ahci_sg->flags_size = cpu_to_le32(0x3fffff &
  447. (buf_len < MAX_DATA_BYTE_COUNT
  448. ? (buf_len - 1)
  449. : (MAX_DATA_BYTE_COUNT - 1)));
  450. ahci_sg++;
  451. buf_len -= MAX_DATA_BYTE_COUNT;
  452. }
  453. return sg_count;
  454. }
  455. static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
  456. {
  457. pp->cmd_slot->opts = cpu_to_le32(opts);
  458. pp->cmd_slot->status = 0;
  459. pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
  460. #ifdef CONFIG_PHYS_64BIT
  461. pp->cmd_slot->tbl_addr_hi =
  462. cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
  463. #endif
  464. }
  465. static int wait_spinup(void __iomem *port_mmio)
  466. {
  467. ulong start;
  468. u32 tf_data;
  469. start = get_timer(0);
  470. do {
  471. tf_data = readl(port_mmio + PORT_TFDATA);
  472. if (!(tf_data & ATA_BUSY))
  473. return 0;
  474. } while (get_timer(start) < WAIT_MS_SPINUP);
  475. return -ETIMEDOUT;
  476. }
  477. static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
  478. {
  479. struct ahci_ioports *pp = &(uc_priv->port[port]);
  480. void __iomem *port_mmio = pp->port_mmio;
  481. u64 dma_addr;
  482. u32 port_status;
  483. void __iomem *mem;
  484. debug("Enter start port: %d\n", port);
  485. port_status = readl(port_mmio + PORT_SCR_STAT);
  486. debug("Port %d status: %x\n", port, port_status);
  487. if ((port_status & 0xf) != 0x03) {
  488. printf("No Link on this port!\n");
  489. return -1;
  490. }
  491. mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
  492. if (!mem) {
  493. free(pp);
  494. printf("%s: No mem for table!\n", __func__);
  495. return -ENOMEM;
  496. }
  497. memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
  498. /*
  499. * First item in chunk of DMA memory: 32-slot command table,
  500. * 32 bytes each in size
  501. */
  502. pp->cmd_slot =
  503. (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
  504. debug("cmd_slot = %p\n", pp->cmd_slot);
  505. mem += (AHCI_CMD_SLOT_SZ + 224);
  506. /*
  507. * Second item: Received-FIS area
  508. */
  509. pp->rx_fis = virt_to_phys((void *)mem);
  510. mem += AHCI_RX_FIS_SZ;
  511. /*
  512. * Third item: data area for storing a single command
  513. * and its scatter-gather table
  514. */
  515. pp->cmd_tbl = virt_to_phys((void *)mem);
  516. debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
  517. mem += AHCI_CMD_TBL_HDR;
  518. pp->cmd_tbl_sg =
  519. (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
  520. dma_addr = (ulong)pp->cmd_slot;
  521. writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR);
  522. writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI);
  523. dma_addr = (ulong)pp->rx_fis;
  524. writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR);
  525. writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI);
  526. #ifdef CONFIG_SUNXI_AHCI
  527. sunxi_dma_init(port_mmio);
  528. #endif
  529. writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
  530. PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
  531. PORT_CMD_START, port_mmio + PORT_CMD);
  532. debug("Exit start port %d\n", port);
  533. /*
  534. * Make sure interface is not busy based on error and status
  535. * information from task file data register before proceeding
  536. */
  537. return wait_spinup(port_mmio);
  538. }
  539. static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis,
  540. int fis_len, u8 *buf, int buf_len, u8 is_write)
  541. {
  542. struct ahci_ioports *pp = &(uc_priv->port[port]);
  543. void __iomem *port_mmio = pp->port_mmio;
  544. u32 opts;
  545. u32 port_status;
  546. int sg_count;
  547. debug("Enter %s: for port %d\n", __func__, port);
  548. if (port > uc_priv->n_ports) {
  549. printf("Invalid port number %d\n", port);
  550. return -1;
  551. }
  552. port_status = readl(port_mmio + PORT_SCR_STAT);
  553. if ((port_status & 0xf) != 0x03) {
  554. debug("No Link on port %d!\n", port);
  555. return -1;
  556. }
  557. memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
  558. sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
  559. opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
  560. ahci_fill_cmd_slot(pp, opts);
  561. ahci_dcache_flush_sata_cmd(pp);
  562. ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
  563. writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
  564. if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
  565. WAIT_MS_DATAIO, 0x1)) {
  566. printf("timeout exit!\n");
  567. return -1;
  568. }
  569. ahci_dcache_invalidate_range((unsigned long)buf,
  570. (unsigned long)buf_len);
  571. debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
  572. return 0;
  573. }
  574. static char *ata_id_strcpy(u16 *target, u16 *src, int len)
  575. {
  576. int i;
  577. for (i = 0; i < len / 2; i++)
  578. target[i] = swab16(src[i]);
  579. return (char *)target;
  580. }
  581. /*
  582. * SCSI INQUIRY command operation.
  583. */
  584. static int ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
  585. struct scsi_cmd *pccb)
  586. {
  587. static const u8 hdr[] = {
  588. 0,
  589. 0,
  590. 0x5, /* claim SPC-3 version compatibility */
  591. 2,
  592. 95 - 4,
  593. };
  594. u8 fis[20];
  595. u16 *idbuf;
  596. ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
  597. u8 port;
  598. /* Clean ccb data buffer */
  599. memset(pccb->pdata, 0, pccb->datalen);
  600. memcpy(pccb->pdata, hdr, sizeof(hdr));
  601. if (pccb->datalen <= 35)
  602. return 0;
  603. memset(fis, 0, sizeof(fis));
  604. /* Construct the FIS */
  605. fis[0] = 0x27; /* Host to device FIS. */
  606. fis[1] = 1 << 7; /* Command FIS. */
  607. fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
  608. /* Read id from sata */
  609. port = pccb->target;
  610. if (ahci_device_data_io(uc_priv, port, (u8 *)&fis, sizeof(fis),
  611. (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) {
  612. debug("scsi_ahci: SCSI inquiry command failure.\n");
  613. return -EIO;
  614. }
  615. if (!uc_priv->ataid[port]) {
  616. uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2);
  617. if (!uc_priv->ataid[port]) {
  618. printf("%s: No memory for ataid[port]\n", __func__);
  619. return -ENOMEM;
  620. }
  621. }
  622. idbuf = uc_priv->ataid[port];
  623. memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
  624. ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
  625. memcpy(&pccb->pdata[8], "ATA ", 8);
  626. ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
  627. ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
  628. #ifdef DEBUG
  629. ata_dump_id(idbuf);
  630. #endif
  631. return 0;
  632. }
  633. /*
  634. * SCSI READ10/WRITE10 command operation.
  635. */
  636. static int ata_scsiop_read_write(struct ahci_uc_priv *uc_priv,
  637. struct scsi_cmd *pccb, u8 is_write)
  638. {
  639. lbaint_t lba = 0;
  640. u16 blocks = 0;
  641. u8 fis[20];
  642. u8 *user_buffer = pccb->pdata;
  643. u32 user_buffer_size = pccb->datalen;
  644. /* Retrieve the base LBA number from the ccb structure. */
  645. if (pccb->cmd[0] == SCSI_READ16) {
  646. memcpy(&lba, pccb->cmd + 2, 8);
  647. lba = be64_to_cpu(lba);
  648. } else {
  649. u32 temp;
  650. memcpy(&temp, pccb->cmd + 2, 4);
  651. lba = be32_to_cpu(temp);
  652. }
  653. /*
  654. * Retrieve the base LBA number and the block count from
  655. * the ccb structure.
  656. *
  657. * For 10-byte and 16-byte SCSI R/W commands, transfer
  658. * length 0 means transfer 0 block of data.
  659. * However, for ATA R/W commands, sector count 0 means
  660. * 256 or 65536 sectors, not 0 sectors as in SCSI.
  661. *
  662. * WARNING: one or two older ATA drives treat 0 as 0...
  663. */
  664. if (pccb->cmd[0] == SCSI_READ16)
  665. blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
  666. else
  667. blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
  668. debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
  669. is_write ? "write" : "read", blocks, lba);
  670. /* Preset the FIS */
  671. memset(fis, 0, sizeof(fis));
  672. fis[0] = 0x27; /* Host to device FIS. */
  673. fis[1] = 1 << 7; /* Command FIS. */
  674. /* Command byte (read/write). */
  675. fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
  676. while (blocks) {
  677. u16 now_blocks; /* number of blocks per iteration */
  678. u32 transfer_size; /* number of bytes per iteration */
  679. now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
  680. transfer_size = ATA_SECT_SIZE * now_blocks;
  681. if (transfer_size > user_buffer_size) {
  682. printf("scsi_ahci: Error: buffer too small.\n");
  683. return -EIO;
  684. }
  685. /*
  686. * LBA48 SATA command but only use 32bit address range within
  687. * that (unless we've enabled 64bit LBA support). The next
  688. * smaller command range (28bit) is too small.
  689. */
  690. fis[4] = (lba >> 0) & 0xff;
  691. fis[5] = (lba >> 8) & 0xff;
  692. fis[6] = (lba >> 16) & 0xff;
  693. fis[7] = 1 << 6; /* device reg: set LBA mode */
  694. fis[8] = ((lba >> 24) & 0xff);
  695. #ifdef CONFIG_SYS_64BIT_LBA
  696. if (pccb->cmd[0] == SCSI_READ16) {
  697. fis[9] = ((lba >> 32) & 0xff);
  698. fis[10] = ((lba >> 40) & 0xff);
  699. }
  700. #endif
  701. fis[3] = 0xe0; /* features */
  702. /* Block (sector) count */
  703. fis[12] = (now_blocks >> 0) & 0xff;
  704. fis[13] = (now_blocks >> 8) & 0xff;
  705. /* Read/Write from ahci */
  706. if (ahci_device_data_io(uc_priv, pccb->target, (u8 *)&fis,
  707. sizeof(fis), user_buffer, transfer_size,
  708. is_write)) {
  709. debug("scsi_ahci: SCSI %s10 command failure.\n",
  710. is_write ? "WRITE" : "READ");
  711. return -EIO;
  712. }
  713. /* If this transaction is a write, do a following flush.
  714. * Writes in u-boot are so rare, and the logic to know when is
  715. * the last write and do a flush only there is sufficiently
  716. * difficult. Just do a flush after every write. This incurs,
  717. * usually, one extra flush when the rare writes do happen.
  718. */
  719. if (is_write) {
  720. if (-EIO == ata_io_flush(uc_priv, pccb->target))
  721. return -EIO;
  722. }
  723. user_buffer += transfer_size;
  724. user_buffer_size -= transfer_size;
  725. blocks -= now_blocks;
  726. lba += now_blocks;
  727. }
  728. return 0;
  729. }
  730. /*
  731. * SCSI READ CAPACITY10 command operation.
  732. */
  733. static int ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
  734. struct scsi_cmd *pccb)
  735. {
  736. u32 cap;
  737. u64 cap64;
  738. u32 block_size;
  739. if (!uc_priv->ataid[pccb->target]) {
  740. printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
  741. "\tNo ATA info!\n"
  742. "\tPlease run SCSI command INQUIRY first!\n");
  743. return -EPERM;
  744. }
  745. cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
  746. if (cap64 > 0x100000000ULL)
  747. cap64 = 0xffffffff;
  748. cap = cpu_to_be32(cap64);
  749. memcpy(pccb->pdata, &cap, sizeof(cap));
  750. block_size = cpu_to_be32((u32)512);
  751. memcpy(&pccb->pdata[4], &block_size, 4);
  752. return 0;
  753. }
  754. /*
  755. * SCSI READ CAPACITY16 command operation.
  756. */
  757. static int ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
  758. struct scsi_cmd *pccb)
  759. {
  760. u64 cap;
  761. u64 block_size;
  762. if (!uc_priv->ataid[pccb->target]) {
  763. printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
  764. "\tNo ATA info!\n"
  765. "\tPlease run SCSI command INQUIRY first!\n");
  766. return -EPERM;
  767. }
  768. cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
  769. cap = cpu_to_be64(cap);
  770. memcpy(pccb->pdata, &cap, sizeof(cap));
  771. block_size = cpu_to_be64((u64)512);
  772. memcpy(&pccb->pdata[8], &block_size, 8);
  773. return 0;
  774. }
  775. /*
  776. * SCSI TEST UNIT READY command operation.
  777. */
  778. static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
  779. struct scsi_cmd *pccb)
  780. {
  781. return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
  782. }
  783. static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
  784. {
  785. struct ahci_uc_priv *uc_priv;
  786. #ifdef CONFIG_DM_SCSI
  787. uc_priv = dev_get_uclass_priv(dev->parent);
  788. #else
  789. uc_priv = probe_ent;
  790. #endif
  791. int ret;
  792. switch (pccb->cmd[0]) {
  793. case SCSI_READ16:
  794. case SCSI_READ10:
  795. ret = ata_scsiop_read_write(uc_priv, pccb, 0);
  796. break;
  797. case SCSI_WRITE10:
  798. ret = ata_scsiop_read_write(uc_priv, pccb, 1);
  799. break;
  800. case SCSI_RD_CAPAC10:
  801. ret = ata_scsiop_read_capacity10(uc_priv, pccb);
  802. break;
  803. case SCSI_RD_CAPAC16:
  804. ret = ata_scsiop_read_capacity16(uc_priv, pccb);
  805. break;
  806. case SCSI_TST_U_RDY:
  807. ret = ata_scsiop_test_unit_ready(uc_priv, pccb);
  808. break;
  809. case SCSI_INQUIRY:
  810. ret = ata_scsiop_inquiry(uc_priv, pccb);
  811. break;
  812. default:
  813. printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
  814. return -ENOTSUPP;
  815. }
  816. if (ret) {
  817. debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
  818. return ret;
  819. }
  820. return 0;
  821. }
  822. static int ahci_start_ports(struct ahci_uc_priv *uc_priv)
  823. {
  824. u32 linkmap;
  825. int i;
  826. linkmap = uc_priv->link_port_map;
  827. for (i = 0; i < uc_priv->n_ports; i++) {
  828. if (((linkmap >> i) & 0x01)) {
  829. if (ahci_port_start(uc_priv, (u8) i)) {
  830. printf("Can not start port %d\n", i);
  831. continue;
  832. }
  833. }
  834. }
  835. return 0;
  836. }
  837. #ifndef CONFIG_DM_SCSI
  838. void scsi_low_level_init(int busdevfunc)
  839. {
  840. struct ahci_uc_priv *uc_priv;
  841. #ifndef CONFIG_SCSI_AHCI_PLAT
  842. probe_ent = calloc(1, sizeof(struct ahci_uc_priv));
  843. if (!probe_ent) {
  844. printf("%s: No memory for uc_priv\n", __func__);
  845. return;
  846. }
  847. uc_priv = probe_ent;
  848. # if defined(CONFIG_DM_PCI)
  849. struct udevice *dev;
  850. int ret;
  851. ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
  852. if (ret)
  853. return;
  854. ahci_init_one(uc_priv, dev);
  855. # else
  856. ahci_init_one(uc_priv, busdevfunc);
  857. # endif
  858. #else
  859. uc_priv = probe_ent;
  860. #endif
  861. ahci_start_ports(uc_priv);
  862. }
  863. #endif
  864. #ifndef CONFIG_SCSI_AHCI_PLAT
  865. # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
  866. int ahci_init_one_dm(struct udevice *dev)
  867. {
  868. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  869. return ahci_init_one(uc_priv, dev);
  870. }
  871. #endif
  872. #endif
  873. int ahci_start_ports_dm(struct udevice *dev)
  874. {
  875. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  876. return ahci_start_ports(uc_priv);
  877. }
  878. #ifdef CONFIG_SCSI_AHCI_PLAT
  879. static int ahci_init_common(struct ahci_uc_priv *uc_priv, void __iomem *base)
  880. {
  881. int rc;
  882. uc_priv->host_flags = ATA_FLAG_SATA
  883. | ATA_FLAG_NO_LEGACY
  884. | ATA_FLAG_MMIO
  885. | ATA_FLAG_PIO_DMA
  886. | ATA_FLAG_NO_ATAPI;
  887. uc_priv->pio_mask = 0x1f;
  888. uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
  889. uc_priv->mmio_base = base;
  890. /* initialize adapter */
  891. rc = ahci_host_init(uc_priv);
  892. if (rc)
  893. goto err_out;
  894. ahci_print_info(uc_priv);
  895. rc = ahci_start_ports(uc_priv);
  896. err_out:
  897. return rc;
  898. }
  899. #ifndef CONFIG_DM_SCSI
  900. int ahci_init(void __iomem *base)
  901. {
  902. struct ahci_uc_priv *uc_priv;
  903. probe_ent = malloc(sizeof(struct ahci_uc_priv));
  904. if (!probe_ent) {
  905. printf("%s: No memory for uc_priv\n", __func__);
  906. return -ENOMEM;
  907. }
  908. uc_priv = probe_ent;
  909. memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
  910. return ahci_init_common(uc_priv, base);
  911. }
  912. #endif
  913. int ahci_init_dm(struct udevice *dev, void __iomem *base)
  914. {
  915. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  916. return ahci_init_common(uc_priv, base);
  917. }
  918. void __weak scsi_init(void)
  919. {
  920. }
  921. #endif /* CONFIG_SCSI_AHCI_PLAT */
  922. /*
  923. * In the general case of generic rotating media it makes sense to have a
  924. * flush capability. It probably even makes sense in the case of SSDs because
  925. * one cannot always know for sure what kind of internal cache/flush mechanism
  926. * is embodied therein. At first it was planned to invoke this after the last
  927. * write to disk and before rebooting. In practice, knowing, a priori, which
  928. * is the last write is difficult. Because writing to the disk in u-boot is
  929. * very rare, this flush command will be invoked after every block write.
  930. */
  931. static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port)
  932. {
  933. u8 fis[20];
  934. struct ahci_ioports *pp = &(uc_priv->port[port]);
  935. void __iomem *port_mmio = pp->port_mmio;
  936. u32 cmd_fis_len = 5; /* five dwords */
  937. /* Preset the FIS */
  938. memset(fis, 0, 20);
  939. fis[0] = 0x27; /* Host to device FIS. */
  940. fis[1] = 1 << 7; /* Command FIS. */
  941. fis[2] = ATA_CMD_FLUSH_EXT;
  942. memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
  943. ahci_fill_cmd_slot(pp, cmd_fis_len);
  944. ahci_dcache_flush_sata_cmd(pp);
  945. writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
  946. if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
  947. WAIT_MS_FLUSH, 0x1)) {
  948. debug("scsi_ahci: flush command timeout on port %d.\n", port);
  949. return -EIO;
  950. }
  951. return 0;
  952. }
  953. static int ahci_scsi_bus_reset(struct udevice *dev)
  954. {
  955. /* Not implemented */
  956. return 0;
  957. }
  958. #ifdef CONFIG_DM_SCSI
  959. int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp)
  960. {
  961. struct udevice *dev;
  962. int ret;
  963. ret = device_bind_driver(ahci_dev, "ahci_scsi", "ahci_scsi", &dev);
  964. if (ret)
  965. return ret;
  966. *devp = dev;
  967. return 0;
  968. }
  969. int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
  970. {
  971. struct ahci_uc_priv *uc_priv;
  972. struct scsi_platdata *uc_plat;
  973. struct udevice *dev;
  974. int ret;
  975. device_find_first_child(ahci_dev, &dev);
  976. if (!dev)
  977. return -ENODEV;
  978. uc_plat = dev_get_uclass_platdata(dev);
  979. uc_plat->base = base;
  980. uc_plat->max_lun = 1;
  981. uc_plat->max_id = 2;
  982. uc_priv = dev_get_uclass_priv(ahci_dev);
  983. ret = ahci_init_one(uc_priv, dev);
  984. if (ret)
  985. return ret;
  986. ret = ahci_start_ports(uc_priv);
  987. if (ret)
  988. return ret;
  989. /*
  990. * scsi_scan_dev() scans devices up-to the number of max_id.
  991. * Update max_id if the number of detected ports exceeds max_id.
  992. * This allows SCSI to scan all detected ports.
  993. */
  994. uc_plat->max_id = max_t(unsigned long, uc_priv->n_ports,
  995. uc_plat->max_id);
  996. return 0;
  997. }
  998. #ifdef CONFIG_DM_PCI
  999. int ahci_probe_scsi_pci(struct udevice *ahci_dev)
  1000. {
  1001. ulong base;
  1002. base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5,
  1003. PCI_REGION_MEM);
  1004. return ahci_probe_scsi(ahci_dev, base);
  1005. }
  1006. #endif
  1007. struct scsi_ops scsi_ops = {
  1008. .exec = ahci_scsi_exec,
  1009. .bus_reset = ahci_scsi_bus_reset,
  1010. };
  1011. U_BOOT_DRIVER(ahci_scsi) = {
  1012. .name = "ahci_scsi",
  1013. .id = UCLASS_SCSI,
  1014. .ops = &scsi_ops,
  1015. };
  1016. #else
  1017. int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
  1018. {
  1019. return ahci_scsi_exec(dev, pccb);
  1020. }
  1021. __weak int scsi_bus_reset(struct udevice *dev)
  1022. {
  1023. return ahci_scsi_bus_reset(dev);
  1024. return 0;
  1025. }
  1026. #endif