meson-saradc.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
  4. * Copyright (C) 2018 BayLibre, SAS
  5. * Author: Neil Armstrong <narmstrong@baylibre.com>
  6. *
  7. * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
  8. */
  9. #include <common.h>
  10. #include <adc.h>
  11. #include <clk.h>
  12. #include <dm.h>
  13. #include <regmap.h>
  14. #include <errno.h>
  15. #include <asm/io.h>
  16. #include <linux/math64.h>
  17. #include <linux/bitfield.h>
  18. #define MESON_SAR_ADC_REG0 0x00
  19. #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
  20. #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
  21. #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
  22. #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
  23. #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
  24. #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
  25. #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
  26. #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
  27. #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
  28. #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
  29. #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
  30. #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
  31. #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
  32. #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
  33. #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
  34. #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
  35. #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
  36. #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
  37. #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
  38. #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
  39. #define MESON_SAR_ADC_CHAN_LIST 0x04
  40. #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
  41. #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
  42. (GENMASK(2, 0) << ((_chan) * 3))
  43. #define MESON_SAR_ADC_AVG_CNTL 0x08
  44. #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
  45. (16 + ((_chan) * 2))
  46. #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
  47. (GENMASK(17, 16) << ((_chan) * 2))
  48. #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
  49. (0 + ((_chan) * 2))
  50. #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
  51. (GENMASK(1, 0) << ((_chan) * 2))
  52. #define MESON_SAR_ADC_REG3 0x0c
  53. #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
  54. #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
  55. #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
  56. #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
  57. #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
  58. #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
  59. #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
  60. #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
  61. #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
  62. #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
  63. #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
  64. #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
  65. #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
  66. #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
  67. #define MESON_SAR_ADC_DELAY 0x10
  68. #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
  69. #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
  70. #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
  71. #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
  72. #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
  73. #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
  74. #define MESON_SAR_ADC_LAST_RD 0x14
  75. #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
  76. #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
  77. #define MESON_SAR_ADC_FIFO_RD 0x18
  78. #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
  79. #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
  80. #define MESON_SAR_ADC_AUX_SW 0x1c
  81. #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan) \
  82. (8 + (((_chan) - 2) * 3))
  83. #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
  84. #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
  85. #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
  86. #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
  87. #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
  88. #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
  89. #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
  90. #define MESON_SAR_ADC_CHAN_10_SW 0x20
  91. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
  92. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
  93. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
  94. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
  95. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
  96. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
  97. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
  98. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
  99. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
  100. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
  101. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
  102. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
  103. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
  104. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
  105. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
  106. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
  107. #define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
  108. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
  109. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
  110. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
  111. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
  112. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
  113. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
  114. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
  115. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
  116. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
  117. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
  118. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
  119. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
  120. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
  121. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
  122. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
  123. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
  124. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
  125. #define MESON_SAR_ADC_DELTA_10 0x28
  126. #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
  127. #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
  128. #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
  129. #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
  130. #define MESON_SAR_ADC_DELTA_10_TS_C_SHIFT 11
  131. #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
  132. #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
  133. #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
  134. /*
  135. * NOTE: registers from here are undocumented (the vendor Linux kernel driver
  136. * and u-boot source served as reference). These only seem to be relevant on
  137. * GXBB and newer.
  138. */
  139. #define MESON_SAR_ADC_REG11 0x2c
  140. #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
  141. #define MESON_SAR_ADC_REG13 0x34
  142. #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
  143. #define MESON_SAR_ADC_MAX_FIFO_SIZE 32
  144. #define MESON_SAR_ADC_TIMEOUT 100 /* ms */
  145. #define NUM_CHANNELS 8
  146. #define MILLION 1000000
  147. struct meson_saradc_data {
  148. int num_bits;
  149. };
  150. struct meson_saradc_priv {
  151. const struct meson_saradc_data *data;
  152. struct regmap *regmap;
  153. struct clk core_clk;
  154. struct clk adc_clk;
  155. bool initialized;
  156. int active_channel;
  157. int calibbias;
  158. int calibscale;
  159. };
  160. static unsigned int
  161. meson_saradc_get_fifo_count(struct meson_saradc_priv *priv)
  162. {
  163. u32 regval;
  164. regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
  165. return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
  166. }
  167. static int meson_saradc_lock(struct meson_saradc_priv *priv)
  168. {
  169. uint val, timeout = 10000;
  170. /* prevent BL30 from using the SAR ADC while we are using it */
  171. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  172. MESON_SAR_ADC_DELAY_KERNEL_BUSY,
  173. MESON_SAR_ADC_DELAY_KERNEL_BUSY);
  174. /*
  175. * wait until BL30 releases it's lock (so we can use the SAR ADC)
  176. */
  177. do {
  178. udelay(1);
  179. regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
  180. } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
  181. if (timeout < 0) {
  182. printf("Timeout while waiting for BL30 unlock\n");
  183. return -ETIMEDOUT;
  184. }
  185. return 0;
  186. }
  187. static void meson_saradc_unlock(struct meson_saradc_priv *priv)
  188. {
  189. /* allow BL30 to use the SAR ADC again */
  190. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  191. MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
  192. }
  193. static void meson_saradc_clear_fifo(struct meson_saradc_priv *priv)
  194. {
  195. unsigned int count, tmp;
  196. for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
  197. if (!meson_saradc_get_fifo_count(priv))
  198. break;
  199. regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);
  200. }
  201. }
  202. static int meson_saradc_calib_val(struct meson_saradc_priv *priv, int val)
  203. {
  204. int tmp;
  205. /* use val_calib = scale * val_raw + offset calibration function */
  206. tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;
  207. return clamp(tmp, 0, (1 << priv->data->num_bits) - 1);
  208. }
  209. static int meson_saradc_wait_busy_clear(struct meson_saradc_priv *priv)
  210. {
  211. uint regval, timeout = 10000;
  212. /*
  213. * NOTE: we need a small delay before reading the status, otherwise
  214. * the sample engine may not have started internally (which would
  215. * seem to us that sampling is already finished).
  216. */
  217. do {
  218. udelay(1);
  219. regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
  220. } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
  221. if (timeout < 0)
  222. return -ETIMEDOUT;
  223. return 0;
  224. }
  225. static int meson_saradc_read_raw_sample(struct meson_saradc_priv *priv,
  226. unsigned int channel, uint *val)
  227. {
  228. uint regval, fifo_chan, fifo_val, count;
  229. int ret;
  230. ret = meson_saradc_wait_busy_clear(priv);
  231. if (ret)
  232. return ret;
  233. count = meson_saradc_get_fifo_count(priv);
  234. if (count != 1) {
  235. printf("ADC FIFO has %d element(s) instead of one\n", count);
  236. return -EINVAL;
  237. }
  238. regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &regval);
  239. fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
  240. if (fifo_chan != channel) {
  241. printf("ADC FIFO entry belongs to channel %d instead of %d\n",
  242. fifo_chan, channel);
  243. return -EINVAL;
  244. }
  245. fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);
  246. fifo_val &= GENMASK(priv->data->num_bits - 1, 0);
  247. *val = meson_saradc_calib_val(priv, fifo_val);
  248. return 0;
  249. }
  250. static void meson_saradc_start_sample_engine(struct meson_saradc_priv *priv)
  251. {
  252. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  253. MESON_SAR_ADC_REG0_FIFO_IRQ_EN,
  254. MESON_SAR_ADC_REG0_FIFO_IRQ_EN);
  255. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  256. MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
  257. MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
  258. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  259. MESON_SAR_ADC_REG0_SAMPLING_START,
  260. MESON_SAR_ADC_REG0_SAMPLING_START);
  261. }
  262. static void meson_saradc_stop_sample_engine(struct meson_saradc_priv *priv)
  263. {
  264. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  265. MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 0);
  266. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  267. MESON_SAR_ADC_REG0_SAMPLING_STOP,
  268. MESON_SAR_ADC_REG0_SAMPLING_STOP);
  269. /* wait until all modules are stopped */
  270. meson_saradc_wait_busy_clear(priv);
  271. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  272. MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
  273. }
  274. enum meson_saradc_avg_mode {
  275. NO_AVERAGING = 0x0,
  276. MEAN_AVERAGING = 0x1,
  277. MEDIAN_AVERAGING = 0x2,
  278. };
  279. enum meson_saradc_num_samples {
  280. ONE_SAMPLE = 0x0,
  281. TWO_SAMPLES = 0x1,
  282. FOUR_SAMPLES = 0x2,
  283. EIGHT_SAMPLES = 0x3,
  284. };
  285. static void meson_saradc_set_averaging(struct meson_saradc_priv *priv,
  286. unsigned int channel,
  287. enum meson_saradc_avg_mode mode,
  288. enum meson_saradc_num_samples samples)
  289. {
  290. int val;
  291. val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(channel);
  292. regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
  293. MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(channel),
  294. val);
  295. val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(channel);
  296. regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
  297. MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(channel), val);
  298. }
  299. static void meson_saradc_enable_channel(struct meson_saradc_priv *priv,
  300. unsigned int channel)
  301. {
  302. uint regval;
  303. /*
  304. * the SAR ADC engine allows sampling multiple channels at the same
  305. * time. to keep it simple we're only working with one *internal*
  306. * channel, which starts counting at index 0 (which means: count = 1).
  307. */
  308. regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
  309. regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
  310. MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
  311. /* map channel index 0 to the channel which we want to read */
  312. regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), channel);
  313. regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
  314. MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
  315. regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
  316. channel);
  317. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
  318. MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
  319. regval);
  320. regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
  321. channel);
  322. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
  323. MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
  324. regval);
  325. if (channel == 6)
  326. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
  327. MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0);
  328. }
  329. static int meson_saradc_get_sample(struct meson_saradc_priv *priv,
  330. int chan, uint *val)
  331. {
  332. int ret;
  333. ret = meson_saradc_lock(priv);
  334. if (ret)
  335. return ret;
  336. /* clear the FIFO to make sure we're not reading old values */
  337. meson_saradc_clear_fifo(priv);
  338. meson_saradc_set_averaging(priv, chan, MEAN_AVERAGING, EIGHT_SAMPLES);
  339. meson_saradc_enable_channel(priv, chan);
  340. meson_saradc_start_sample_engine(priv);
  341. ret = meson_saradc_read_raw_sample(priv, chan, val);
  342. meson_saradc_stop_sample_engine(priv);
  343. meson_saradc_unlock(priv);
  344. if (ret) {
  345. printf("failed to read sample for channel %d: %d\n",
  346. chan, ret);
  347. return ret;
  348. }
  349. return 0;
  350. }
  351. static int meson_saradc_channel_data(struct udevice *dev, int channel,
  352. unsigned int *data)
  353. {
  354. struct meson_saradc_priv *priv = dev_get_priv(dev);
  355. if (channel != priv->active_channel) {
  356. pr_err("Requested channel is not active!");
  357. return -EINVAL;
  358. }
  359. return meson_saradc_get_sample(priv, channel, data);
  360. }
  361. enum meson_saradc_chan7_mux_sel {
  362. CHAN7_MUX_VSS = 0x0,
  363. CHAN7_MUX_VDD_DIV4 = 0x1,
  364. CHAN7_MUX_VDD_DIV2 = 0x2,
  365. CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
  366. CHAN7_MUX_VDD = 0x4,
  367. CHAN7_MUX_CH7_INPUT = 0x7,
  368. };
  369. static void meson_saradc_set_chan7_mux(struct meson_saradc_priv *priv,
  370. enum meson_saradc_chan7_mux_sel sel)
  371. {
  372. u32 regval;
  373. regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
  374. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
  375. MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
  376. udelay(20);
  377. }
  378. static int meson_saradc_calib(struct meson_saradc_priv *priv)
  379. {
  380. uint nominal0, nominal1, value0, value1;
  381. int ret;
  382. /* use points 25% and 75% for calibration */
  383. nominal0 = (1 << priv->data->num_bits) / 4;
  384. nominal1 = (1 << priv->data->num_bits) * 3 / 4;
  385. meson_saradc_set_chan7_mux(priv, CHAN7_MUX_VDD_DIV4);
  386. udelay(20);
  387. ret = meson_saradc_get_sample(priv, 7, &value0);
  388. if (ret < 0)
  389. goto out;
  390. meson_saradc_set_chan7_mux(priv, CHAN7_MUX_VDD_MUL3_DIV4);
  391. udelay(20);
  392. ret = meson_saradc_get_sample(priv, 7, &value1);
  393. if (ret < 0)
  394. goto out;
  395. if (value1 <= value0) {
  396. ret = -EINVAL;
  397. goto out;
  398. }
  399. priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,
  400. value1 - value0);
  401. priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,
  402. MILLION);
  403. ret = 0;
  404. out:
  405. meson_saradc_set_chan7_mux(priv, CHAN7_MUX_CH7_INPUT);
  406. return ret;
  407. }
  408. static int meson_saradc_init(struct meson_saradc_priv *priv)
  409. {
  410. uint regval;
  411. int ret, i;
  412. priv->calibscale = MILLION;
  413. /*
  414. * make sure we start at CH7 input since the other muxes are only used
  415. * for internal calibration.
  416. */
  417. meson_saradc_set_chan7_mux(priv, CHAN7_MUX_CH7_INPUT);
  418. /*
  419. * leave sampling delay and the input clocks as configured by
  420. * BL30 to make sure BL30 gets the values it expects when
  421. * reading the temperature sensor.
  422. */
  423. regmap_read(priv->regmap, MESON_SAR_ADC_REG3, &regval);
  424. if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
  425. return 0;
  426. meson_saradc_stop_sample_engine(priv);
  427. /* update the channel 6 MUX to select the temperature sensor */
  428. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  429. MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
  430. MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
  431. /* disable all channels by default */
  432. regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
  433. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
  434. MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
  435. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
  436. MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
  437. MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
  438. /* delay between two samples = (10+1) * 1uS */
  439. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  440. MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
  441. FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
  442. 10));
  443. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  444. MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
  445. FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
  446. 0));
  447. /* delay between two samples = (10+1) * 1uS */
  448. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  449. MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
  450. FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
  451. 10));
  452. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  453. MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
  454. FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
  455. 1));
  456. /*
  457. * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW
  458. * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1)
  459. */
  460. regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0);
  461. regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
  462. MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK,
  463. regval);
  464. regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1);
  465. regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
  466. MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
  467. regval);
  468. /*
  469. * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
  470. * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
  471. * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and
  472. * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver.
  473. */
  474. regval = 0;
  475. for (i = 2; i <= 7; i++)
  476. regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i);
  477. regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW;
  478. regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW;
  479. regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);
  480. ret = meson_saradc_lock(priv);
  481. if (ret)
  482. return ret;
  483. #if CONFIG_IS_ENABLED(CLK)
  484. ret = clk_enable(&priv->core_clk);
  485. if (ret)
  486. return ret;
  487. #endif
  488. regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
  489. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  490. MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
  491. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
  492. MESON_SAR_ADC_REG11_BANDGAP_EN,
  493. MESON_SAR_ADC_REG11_BANDGAP_EN);
  494. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
  495. MESON_SAR_ADC_REG3_ADC_EN,
  496. MESON_SAR_ADC_REG3_ADC_EN);
  497. udelay(5);
  498. #if CONFIG_IS_ENABLED(CLK)
  499. ret = clk_enable(&priv->adc_clk);
  500. if (ret)
  501. return ret;
  502. #endif
  503. meson_saradc_unlock(priv);
  504. ret = meson_saradc_calib(priv);
  505. if (ret) {
  506. printf("calibration failed\n");
  507. return -EIO;
  508. }
  509. return 0;
  510. }
  511. static int meson_saradc_start_channel(struct udevice *dev, int channel)
  512. {
  513. struct meson_saradc_priv *priv = dev_get_priv(dev);
  514. if (channel < 0 || channel >= NUM_CHANNELS) {
  515. printf("Requested channel is invalid!");
  516. return -EINVAL;
  517. }
  518. if (!priv->initialized) {
  519. int ret;
  520. ret = meson_saradc_init(priv);
  521. if (ret)
  522. return ret;
  523. priv->initialized = true;
  524. }
  525. priv->active_channel = channel;
  526. return 0;
  527. }
  528. static int meson_saradc_stop(struct udevice *dev)
  529. {
  530. struct meson_saradc_priv *priv = dev_get_priv(dev);
  531. priv->active_channel = -1;
  532. return 0;
  533. }
  534. static int meson_saradc_probe(struct udevice *dev)
  535. {
  536. struct meson_saradc_priv *priv = dev_get_priv(dev);
  537. int ret;
  538. ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
  539. if (ret)
  540. return ret;
  541. #if CONFIG_IS_ENABLED(CLK)
  542. ret = clk_get_by_name(dev, "core", &priv->core_clk);
  543. if (ret)
  544. return ret;
  545. ret = clk_get_by_name(dev, "adc_clk", &priv->adc_clk);
  546. if (ret)
  547. return ret;
  548. #endif
  549. priv->active_channel = -1;
  550. return 0;
  551. }
  552. int meson_saradc_ofdata_to_platdata(struct udevice *dev)
  553. {
  554. struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
  555. struct meson_saradc_priv *priv = dev_get_priv(dev);
  556. priv->data = (struct meson_saradc_data *)dev_get_driver_data(dev);
  557. uc_pdata->data_mask = GENMASK(priv->data->num_bits - 1, 0);
  558. uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
  559. uc_pdata->data_timeout_us = MESON_SAR_ADC_TIMEOUT * 1000;
  560. uc_pdata->channel_mask = GENMASK(NUM_CHANNELS - 1, 0);
  561. return 0;
  562. }
  563. static const struct adc_ops meson_saradc_ops = {
  564. .start_channel = meson_saradc_start_channel,
  565. .channel_data = meson_saradc_channel_data,
  566. .stop = meson_saradc_stop,
  567. };
  568. static const struct meson_saradc_data gxbb_saradc_data = {
  569. .num_bits = 10,
  570. };
  571. static const struct meson_saradc_data gxl_saradc_data = {
  572. .num_bits = 12,
  573. };
  574. static const struct udevice_id meson_saradc_ids[] = {
  575. { .compatible = "amlogic,meson-gxbb-saradc",
  576. .data = (ulong)&gxbb_saradc_data },
  577. { .compatible = "amlogic,meson-gxl-saradc",
  578. .data = (ulong)&gxl_saradc_data },
  579. { .compatible = "amlogic,meson-gxm-saradc",
  580. .data = (ulong)&gxl_saradc_data },
  581. { }
  582. };
  583. U_BOOT_DRIVER(meson_saradc) = {
  584. .name = "meson_saradc",
  585. .id = UCLASS_ADC,
  586. .of_match = meson_saradc_ids,
  587. .ops = &meson_saradc_ops,
  588. .probe = meson_saradc_probe,
  589. .ofdata_to_platdata = meson_saradc_ofdata_to_platdata,
  590. .priv_auto_alloc_size = sizeof(struct meson_saradc_priv),
  591. };