board.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
  4. * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  5. *
  6. * (C) Copyright 2007-2011
  7. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  8. * Tom Cubie <tangliang@allwinnertech.com>
  9. *
  10. * Some board init for the Allwinner A10-evb board.
  11. */
  12. #include <common.h>
  13. #include <dm.h>
  14. #include <env.h>
  15. #include <hang.h>
  16. #include <init.h>
  17. #include <mmc.h>
  18. #include <axp_pmic.h>
  19. #include <generic-phy.h>
  20. #include <phy-sun4i-usb.h>
  21. #include <asm/arch/clock.h>
  22. #include <asm/arch/cpu.h>
  23. #include <asm/arch/display.h>
  24. #include <asm/arch/dram.h>
  25. #include <asm/arch/gpio.h>
  26. #include <asm/arch/mmc.h>
  27. #include <asm/arch/spl.h>
  28. #include <u-boot/crc.h>
  29. #ifndef CONFIG_ARM64
  30. #include <asm/armv7.h>
  31. #endif
  32. #include <asm/gpio.h>
  33. #include <asm/io.h>
  34. #include <u-boot/crc.h>
  35. #include <env_internal.h>
  36. #include <linux/libfdt.h>
  37. #include <nand.h>
  38. #include <net.h>
  39. #include <spl.h>
  40. #include <sy8106a.h>
  41. #include <asm/setup.h>
  42. #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
  43. /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
  44. int soft_i2c_gpio_sda;
  45. int soft_i2c_gpio_scl;
  46. static int soft_i2c_board_init(void)
  47. {
  48. int ret;
  49. soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
  50. if (soft_i2c_gpio_sda < 0) {
  51. printf("Error invalid soft i2c sda pin: '%s', err %d\n",
  52. CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
  53. return soft_i2c_gpio_sda;
  54. }
  55. ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
  56. if (ret) {
  57. printf("Error requesting soft i2c sda pin: '%s', err %d\n",
  58. CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
  59. return ret;
  60. }
  61. soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
  62. if (soft_i2c_gpio_scl < 0) {
  63. printf("Error invalid soft i2c scl pin: '%s', err %d\n",
  64. CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
  65. return soft_i2c_gpio_scl;
  66. }
  67. ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
  68. if (ret) {
  69. printf("Error requesting soft i2c scl pin: '%s', err %d\n",
  70. CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
  71. return ret;
  72. }
  73. return 0;
  74. }
  75. #else
  76. static int soft_i2c_board_init(void) { return 0; }
  77. #endif
  78. DECLARE_GLOBAL_DATA_PTR;
  79. void i2c_init_board(void)
  80. {
  81. #ifdef CONFIG_I2C0_ENABLE
  82. #if defined(CONFIG_MACH_SUN4I) || \
  83. defined(CONFIG_MACH_SUN5I) || \
  84. defined(CONFIG_MACH_SUN7I) || \
  85. defined(CONFIG_MACH_SUN8I_R40)
  86. sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
  87. sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
  88. clock_twi_onoff(0, 1);
  89. #elif defined(CONFIG_MACH_SUN6I)
  90. sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
  91. sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
  92. clock_twi_onoff(0, 1);
  93. #elif defined(CONFIG_MACH_SUN8I)
  94. sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
  95. sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
  96. clock_twi_onoff(0, 1);
  97. #elif defined(CONFIG_MACH_SUN50I)
  98. sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
  99. sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
  100. clock_twi_onoff(0, 1);
  101. #endif
  102. #endif
  103. #ifdef CONFIG_I2C1_ENABLE
  104. #if defined(CONFIG_MACH_SUN4I) || \
  105. defined(CONFIG_MACH_SUN7I) || \
  106. defined(CONFIG_MACH_SUN8I_R40)
  107. sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
  108. sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
  109. clock_twi_onoff(1, 1);
  110. #elif defined(CONFIG_MACH_SUN5I)
  111. sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
  112. sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
  113. clock_twi_onoff(1, 1);
  114. #elif defined(CONFIG_MACH_SUN6I)
  115. sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
  116. sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
  117. clock_twi_onoff(1, 1);
  118. #elif defined(CONFIG_MACH_SUN8I)
  119. sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
  120. sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
  121. clock_twi_onoff(1, 1);
  122. #elif defined(CONFIG_MACH_SUN50I)
  123. sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
  124. sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
  125. clock_twi_onoff(1, 1);
  126. #endif
  127. #endif
  128. #ifdef CONFIG_I2C2_ENABLE
  129. #if defined(CONFIG_MACH_SUN4I) || \
  130. defined(CONFIG_MACH_SUN7I) || \
  131. defined(CONFIG_MACH_SUN8I_R40)
  132. sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
  133. sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
  134. clock_twi_onoff(2, 1);
  135. #elif defined(CONFIG_MACH_SUN5I)
  136. sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
  137. sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
  138. clock_twi_onoff(2, 1);
  139. #elif defined(CONFIG_MACH_SUN6I)
  140. sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
  141. sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
  142. clock_twi_onoff(2, 1);
  143. #elif defined(CONFIG_MACH_SUN8I)
  144. sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
  145. sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
  146. clock_twi_onoff(2, 1);
  147. #elif defined(CONFIG_MACH_SUN50I)
  148. sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
  149. sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
  150. clock_twi_onoff(2, 1);
  151. #endif
  152. #endif
  153. #ifdef CONFIG_I2C3_ENABLE
  154. #if defined(CONFIG_MACH_SUN6I)
  155. sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
  156. sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
  157. clock_twi_onoff(3, 1);
  158. #elif defined(CONFIG_MACH_SUN7I) || \
  159. defined(CONFIG_MACH_SUN8I_R40)
  160. sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
  161. sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
  162. clock_twi_onoff(3, 1);
  163. #endif
  164. #endif
  165. #ifdef CONFIG_I2C4_ENABLE
  166. #if defined(CONFIG_MACH_SUN7I) || \
  167. defined(CONFIG_MACH_SUN8I_R40)
  168. sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
  169. sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
  170. clock_twi_onoff(4, 1);
  171. #endif
  172. #endif
  173. #ifdef CONFIG_R_I2C_ENABLE
  174. #ifdef CONFIG_MACH_SUN50I
  175. clock_twi_onoff(5, 1);
  176. sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
  177. sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
  178. #else
  179. clock_twi_onoff(5, 1);
  180. sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
  181. sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
  182. #endif
  183. #endif
  184. }
  185. #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
  186. enum env_location env_get_location(enum env_operation op, int prio)
  187. {
  188. switch (prio) {
  189. case 0:
  190. return ENVL_FAT;
  191. case 1:
  192. return ENVL_MMC;
  193. default:
  194. return ENVL_UNKNOWN;
  195. }
  196. }
  197. #endif
  198. #ifdef CONFIG_DM_MMC
  199. static void mmc_pinmux_setup(int sdc);
  200. #endif
  201. /* add board specific code here */
  202. int board_init(void)
  203. {
  204. __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
  205. gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
  206. #ifndef CONFIG_ARM64
  207. asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
  208. debug("id_pfr1: 0x%08x\n", id_pfr1);
  209. /* Generic Timer Extension available? */
  210. if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
  211. uint32_t freq;
  212. debug("Setting CNTFRQ\n");
  213. /*
  214. * CNTFRQ is a secure register, so we will crash if we try to
  215. * write this from the non-secure world (read is OK, though).
  216. * In case some bootcode has already set the correct value,
  217. * we avoid the risk of writing to it.
  218. */
  219. asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
  220. if (freq != COUNTER_FREQUENCY) {
  221. debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
  222. freq, COUNTER_FREQUENCY);
  223. #ifdef CONFIG_NON_SECURE
  224. printf("arch timer frequency is wrong, but cannot adjust it\n");
  225. #else
  226. asm volatile("mcr p15, 0, %0, c14, c0, 0"
  227. : : "r"(COUNTER_FREQUENCY));
  228. #endif
  229. }
  230. }
  231. #endif /* !CONFIG_ARM64 */
  232. ret = axp_gpio_init();
  233. if (ret)
  234. return ret;
  235. #ifdef CONFIG_SATAPWR
  236. satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
  237. gpio_request(satapwr_pin, "satapwr");
  238. gpio_direction_output(satapwr_pin, 1);
  239. /* Give attached sata device time to power-up to avoid link timeouts */
  240. mdelay(500);
  241. #endif
  242. #ifdef CONFIG_MACPWR
  243. macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
  244. gpio_request(macpwr_pin, "macpwr");
  245. gpio_direction_output(macpwr_pin, 1);
  246. #endif
  247. #ifdef CONFIG_DM_I2C
  248. /*
  249. * Temporary workaround for enabling I2C clocks until proper sunxi DM
  250. * clk, reset and pinctrl drivers land.
  251. */
  252. i2c_init_board();
  253. #endif
  254. #ifdef CONFIG_DM_MMC
  255. /*
  256. * Temporary workaround for enabling MMC clocks until a sunxi DM
  257. * pinctrl driver lands.
  258. */
  259. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
  260. #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
  261. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
  262. #endif
  263. #endif /* CONFIG_DM_MMC */
  264. /* Uses dm gpio code so do this here and not in i2c_init_board() */
  265. return soft_i2c_board_init();
  266. }
  267. /*
  268. * On older SoCs the SPL is actually at address zero, so using NULL as
  269. * an error value does not work.
  270. */
  271. #define INVALID_SPL_HEADER ((void *)~0UL)
  272. static struct boot_file_head * get_spl_header(uint8_t req_version)
  273. {
  274. struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
  275. uint8_t spl_header_version = spl->spl_signature[3];
  276. /* Is there really the SPL header (still) there? */
  277. if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
  278. return INVALID_SPL_HEADER;
  279. if (spl_header_version < req_version) {
  280. printf("sunxi SPL version mismatch: expected %u, got %u\n",
  281. req_version, spl_header_version);
  282. return INVALID_SPL_HEADER;
  283. }
  284. return spl;
  285. }
  286. int dram_init(void)
  287. {
  288. struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
  289. if (spl == INVALID_SPL_HEADER)
  290. gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
  291. PHYS_SDRAM_0_SIZE);
  292. else
  293. gd->ram_size = (phys_addr_t)spl->dram_size << 20;
  294. if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
  295. gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
  296. return 0;
  297. }
  298. #if defined(CONFIG_NAND_SUNXI)
  299. static void nand_pinmux_setup(void)
  300. {
  301. unsigned int pin;
  302. for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
  303. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
  304. #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
  305. for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
  306. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
  307. #endif
  308. /* sun4i / sun7i do have a PC23, but it is not used for nand,
  309. * only sun7i has a PC24 */
  310. #ifdef CONFIG_MACH_SUN7I
  311. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
  312. #endif
  313. }
  314. static void nand_clock_setup(void)
  315. {
  316. struct sunxi_ccm_reg *const ccm =
  317. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  318. setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
  319. #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
  320. defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
  321. setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
  322. #endif
  323. setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
  324. }
  325. void board_nand_init(void)
  326. {
  327. nand_pinmux_setup();
  328. nand_clock_setup();
  329. #ifndef CONFIG_SPL_BUILD
  330. sunxi_nand_init();
  331. #endif
  332. }
  333. #endif
  334. #ifdef CONFIG_MMC
  335. static void mmc_pinmux_setup(int sdc)
  336. {
  337. unsigned int pin;
  338. __maybe_unused int pins;
  339. switch (sdc) {
  340. case 0:
  341. /* SDC0: PF0-PF5 */
  342. for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
  343. sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
  344. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  345. sunxi_gpio_set_drv(pin, 2);
  346. }
  347. break;
  348. case 1:
  349. pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
  350. #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
  351. defined(CONFIG_MACH_SUN8I_R40)
  352. if (pins == SUNXI_GPIO_H) {
  353. /* SDC1: PH22-PH-27 */
  354. for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
  355. sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
  356. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  357. sunxi_gpio_set_drv(pin, 2);
  358. }
  359. } else {
  360. /* SDC1: PG0-PG5 */
  361. for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  362. sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
  363. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  364. sunxi_gpio_set_drv(pin, 2);
  365. }
  366. }
  367. #elif defined(CONFIG_MACH_SUN5I)
  368. /* SDC1: PG3-PG8 */
  369. for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
  370. sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
  371. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  372. sunxi_gpio_set_drv(pin, 2);
  373. }
  374. #elif defined(CONFIG_MACH_SUN6I)
  375. /* SDC1: PG0-PG5 */
  376. for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  377. sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
  378. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  379. sunxi_gpio_set_drv(pin, 2);
  380. }
  381. #elif defined(CONFIG_MACH_SUN8I)
  382. if (pins == SUNXI_GPIO_D) {
  383. /* SDC1: PD2-PD7 */
  384. for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
  385. sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
  386. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  387. sunxi_gpio_set_drv(pin, 2);
  388. }
  389. } else {
  390. /* SDC1: PG0-PG5 */
  391. for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  392. sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
  393. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  394. sunxi_gpio_set_drv(pin, 2);
  395. }
  396. }
  397. #endif
  398. break;
  399. case 2:
  400. pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
  401. #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
  402. /* SDC2: PC6-PC11 */
  403. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
  404. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  405. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  406. sunxi_gpio_set_drv(pin, 2);
  407. }
  408. #elif defined(CONFIG_MACH_SUN5I)
  409. if (pins == SUNXI_GPIO_E) {
  410. /* SDC2: PE4-PE9 */
  411. for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
  412. sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
  413. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  414. sunxi_gpio_set_drv(pin, 2);
  415. }
  416. } else {
  417. /* SDC2: PC6-PC15 */
  418. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  419. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  420. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  421. sunxi_gpio_set_drv(pin, 2);
  422. }
  423. }
  424. #elif defined(CONFIG_MACH_SUN6I)
  425. if (pins == SUNXI_GPIO_A) {
  426. /* SDC2: PA9-PA14 */
  427. for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
  428. sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
  429. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  430. sunxi_gpio_set_drv(pin, 2);
  431. }
  432. } else {
  433. /* SDC2: PC6-PC15, PC24 */
  434. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  435. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  436. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  437. sunxi_gpio_set_drv(pin, 2);
  438. }
  439. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
  440. sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
  441. sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
  442. }
  443. #elif defined(CONFIG_MACH_SUN8I_R40)
  444. /* SDC2: PC6-PC15, PC24 */
  445. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  446. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  447. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  448. sunxi_gpio_set_drv(pin, 2);
  449. }
  450. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
  451. sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
  452. sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
  453. #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
  454. /* SDC2: PC5-PC6, PC8-PC16 */
  455. for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
  456. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  457. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  458. sunxi_gpio_set_drv(pin, 2);
  459. }
  460. for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
  461. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  462. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  463. sunxi_gpio_set_drv(pin, 2);
  464. }
  465. #elif defined(CONFIG_MACH_SUN50I_H6)
  466. /* SDC2: PC4-PC14 */
  467. for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
  468. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  469. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  470. sunxi_gpio_set_drv(pin, 2);
  471. }
  472. #elif defined(CONFIG_MACH_SUN9I)
  473. /* SDC2: PC6-PC16 */
  474. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
  475. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  476. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  477. sunxi_gpio_set_drv(pin, 2);
  478. }
  479. #endif
  480. break;
  481. case 3:
  482. pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
  483. #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
  484. defined(CONFIG_MACH_SUN8I_R40)
  485. /* SDC3: PI4-PI9 */
  486. for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
  487. sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
  488. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  489. sunxi_gpio_set_drv(pin, 2);
  490. }
  491. #elif defined(CONFIG_MACH_SUN6I)
  492. if (pins == SUNXI_GPIO_A) {
  493. /* SDC3: PA9-PA14 */
  494. for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
  495. sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
  496. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  497. sunxi_gpio_set_drv(pin, 2);
  498. }
  499. } else {
  500. /* SDC3: PC6-PC15, PC24 */
  501. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  502. sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
  503. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  504. sunxi_gpio_set_drv(pin, 2);
  505. }
  506. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
  507. sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
  508. sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
  509. }
  510. #endif
  511. break;
  512. default:
  513. printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
  514. break;
  515. }
  516. }
  517. int board_mmc_init(bd_t *bis)
  518. {
  519. __maybe_unused struct mmc *mmc0, *mmc1;
  520. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
  521. mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
  522. if (!mmc0)
  523. return -1;
  524. #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
  525. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
  526. mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
  527. if (!mmc1)
  528. return -1;
  529. #endif
  530. return 0;
  531. }
  532. #endif
  533. #ifdef CONFIG_SPL_BUILD
  534. static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
  535. {
  536. struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
  537. if (spl == INVALID_SPL_HEADER)
  538. return;
  539. /* Promote the header version for U-Boot proper, if needed. */
  540. if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
  541. spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
  542. spl->dram_size = dram_size >> 20;
  543. }
  544. void sunxi_board_init(void)
  545. {
  546. int power_failed = 0;
  547. #ifdef CONFIG_SY8106A_POWER
  548. power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
  549. #endif
  550. #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
  551. defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  552. defined CONFIG_AXP818_POWER
  553. power_failed = axp_init();
  554. #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  555. defined CONFIG_AXP818_POWER
  556. power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
  557. #endif
  558. power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
  559. power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
  560. #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
  561. power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
  562. #endif
  563. #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  564. defined CONFIG_AXP818_POWER
  565. power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
  566. #endif
  567. #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  568. defined CONFIG_AXP818_POWER
  569. power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
  570. #endif
  571. power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
  572. #if !defined(CONFIG_AXP152_POWER)
  573. power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
  574. #endif
  575. #ifdef CONFIG_AXP209_POWER
  576. power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
  577. #endif
  578. #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
  579. defined(CONFIG_AXP818_POWER)
  580. power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
  581. power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
  582. #if !defined CONFIG_AXP809_POWER
  583. power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
  584. power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
  585. #endif
  586. power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
  587. power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
  588. power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
  589. #endif
  590. #ifdef CONFIG_AXP818_POWER
  591. power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
  592. power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
  593. power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
  594. #endif
  595. #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
  596. power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
  597. #endif
  598. #endif
  599. printf("DRAM:");
  600. gd->ram_size = sunxi_dram_init();
  601. printf(" %d MiB\n", (int)(gd->ram_size >> 20));
  602. if (!gd->ram_size)
  603. hang();
  604. sunxi_spl_store_dram_size(gd->ram_size);
  605. /*
  606. * Only clock up the CPU to full speed if we are reasonably
  607. * assured it's being powered with suitable core voltage
  608. */
  609. if (!power_failed)
  610. clock_set_pll1(CONFIG_SYS_CLK_FREQ);
  611. else
  612. printf("Failed to set core voltage! Can't set CPU frequency\n");
  613. }
  614. #endif
  615. #ifdef CONFIG_USB_GADGET
  616. int g_dnl_board_usb_cable_connected(void)
  617. {
  618. struct udevice *dev;
  619. struct phy phy;
  620. int ret;
  621. ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
  622. if (ret) {
  623. pr_err("%s: Cannot find USB device\n", __func__);
  624. return ret;
  625. }
  626. ret = generic_phy_get_by_name(dev, "usb", &phy);
  627. if (ret) {
  628. pr_err("failed to get %s USB PHY\n", dev->name);
  629. return ret;
  630. }
  631. ret = generic_phy_init(&phy);
  632. if (ret) {
  633. pr_err("failed to init %s USB PHY\n", dev->name);
  634. return ret;
  635. }
  636. ret = sun4i_usb_phy_vbus_detect(&phy);
  637. if (ret == 1) {
  638. pr_err("A charger is plugged into the OTG\n");
  639. return -ENODEV;
  640. }
  641. return ret;
  642. }
  643. #endif
  644. #ifdef CONFIG_SERIAL_TAG
  645. void get_board_serial(struct tag_serialnr *serialnr)
  646. {
  647. char *serial_string;
  648. unsigned long long serial;
  649. serial_string = env_get("serial#");
  650. if (serial_string) {
  651. serial = simple_strtoull(serial_string, NULL, 16);
  652. serialnr->high = (unsigned int) (serial >> 32);
  653. serialnr->low = (unsigned int) (serial & 0xffffffff);
  654. } else {
  655. serialnr->high = 0;
  656. serialnr->low = 0;
  657. }
  658. }
  659. #endif
  660. /*
  661. * Check the SPL header for the "sunxi" variant. If found: parse values
  662. * that might have been passed by the loader ("fel" utility), and update
  663. * the environment accordingly.
  664. */
  665. static void parse_spl_header(const uint32_t spl_addr)
  666. {
  667. struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
  668. if (spl == INVALID_SPL_HEADER)
  669. return;
  670. if (!spl->fel_script_address)
  671. return;
  672. if (spl->fel_uEnv_length != 0) {
  673. /*
  674. * data is expected in uEnv.txt compatible format, so "env
  675. * import -t" the string(s) at fel_script_address right away.
  676. */
  677. himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
  678. spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
  679. return;
  680. }
  681. /* otherwise assume .scr format (mkimage-type script) */
  682. env_set_hex("fel_scriptaddr", spl->fel_script_address);
  683. }
  684. /*
  685. * Note this function gets called multiple times.
  686. * It must not make any changes to env variables which already exist.
  687. */
  688. static void setup_environment(const void *fdt)
  689. {
  690. char serial_string[17] = { 0 };
  691. unsigned int sid[4];
  692. uint8_t mac_addr[6];
  693. char ethaddr[16];
  694. int i, ret;
  695. ret = sunxi_get_sid(sid);
  696. if (ret == 0 && sid[0] != 0) {
  697. /*
  698. * The single words 1 - 3 of the SID have quite a few bits
  699. * which are the same on many models, so we take a crc32
  700. * of all 3 words, to get a more unique value.
  701. *
  702. * Note we only do this on newer SoCs as we cannot change
  703. * the algorithm on older SoCs since those have been using
  704. * fixed mac-addresses based on only using word 3 for a
  705. * long time and changing a fixed mac-address with an
  706. * u-boot update is not good.
  707. */
  708. #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
  709. !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
  710. !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
  711. sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
  712. #endif
  713. /* Ensure the NIC specific bytes of the mac are not all 0 */
  714. if ((sid[3] & 0xffffff) == 0)
  715. sid[3] |= 0x800000;
  716. for (i = 0; i < 4; i++) {
  717. sprintf(ethaddr, "ethernet%d", i);
  718. if (!fdt_get_alias(fdt, ethaddr))
  719. continue;
  720. if (i == 0)
  721. strcpy(ethaddr, "ethaddr");
  722. else
  723. sprintf(ethaddr, "eth%daddr", i);
  724. if (env_get(ethaddr))
  725. continue;
  726. /* Non OUI / registered MAC address */
  727. mac_addr[0] = (i << 4) | 0x02;
  728. mac_addr[1] = (sid[0] >> 0) & 0xff;
  729. mac_addr[2] = (sid[3] >> 24) & 0xff;
  730. mac_addr[3] = (sid[3] >> 16) & 0xff;
  731. mac_addr[4] = (sid[3] >> 8) & 0xff;
  732. mac_addr[5] = (sid[3] >> 0) & 0xff;
  733. eth_env_set_enetaddr(ethaddr, mac_addr);
  734. }
  735. if (!env_get("serial#")) {
  736. snprintf(serial_string, sizeof(serial_string),
  737. "%08x%08x", sid[0], sid[3]);
  738. env_set("serial#", serial_string);
  739. }
  740. }
  741. }
  742. int misc_init_r(void)
  743. {
  744. uint boot;
  745. env_set("fel_booted", NULL);
  746. env_set("fel_scriptaddr", NULL);
  747. env_set("mmc_bootdev", NULL);
  748. boot = sunxi_get_boot_device();
  749. /* determine if we are running in FEL mode */
  750. if (boot == BOOT_DEVICE_BOARD) {
  751. env_set("fel_booted", "1");
  752. parse_spl_header(SPL_ADDR);
  753. /* or if we booted from MMC, and which one */
  754. } else if (boot == BOOT_DEVICE_MMC1) {
  755. env_set("mmc_bootdev", "0");
  756. } else if (boot == BOOT_DEVICE_MMC2) {
  757. env_set("mmc_bootdev", "1");
  758. }
  759. setup_environment(gd->fdt_blob);
  760. #ifdef CONFIG_USB_ETHER
  761. usb_ether_init();
  762. #endif
  763. return 0;
  764. }
  765. int ft_board_setup(void *blob, bd_t *bd)
  766. {
  767. int __maybe_unused r;
  768. /*
  769. * Call setup_environment again in case the boot fdt has
  770. * ethernet aliases the u-boot copy does not have.
  771. */
  772. setup_environment(blob);
  773. #ifdef CONFIG_VIDEO_DT_SIMPLEFB
  774. r = sunxi_simplefb_setup(blob);
  775. if (r)
  776. return r;
  777. #endif
  778. return 0;
  779. }
  780. #ifdef CONFIG_SPL_LOAD_FIT
  781. int board_fit_config_name_match(const char *name)
  782. {
  783. struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
  784. const char *cmp_str = (const char *)spl;
  785. /* Check if there is a DT name stored in the SPL header and use that. */
  786. if (spl != INVALID_SPL_HEADER && spl->dt_name_offset) {
  787. cmp_str += spl->dt_name_offset;
  788. } else {
  789. #ifdef CONFIG_DEFAULT_DEVICE_TREE
  790. cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
  791. #else
  792. return 0;
  793. #endif
  794. };
  795. #ifdef CONFIG_PINE64_DT_SELECTION
  796. /* Differentiate the two Pine64 board DTs by their DRAM size. */
  797. if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
  798. if ((gd->ram_size > 512 * 1024 * 1024))
  799. return !strstr(name, "plus");
  800. else
  801. return !!strstr(name, "plus");
  802. } else {
  803. return strcmp(name, cmp_str);
  804. }
  805. #endif
  806. return strcmp(name, cmp_str);
  807. }
  808. #endif