sbc8349.c 5.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * sbc8349.c -- WindRiver SBC8349 board support.
  4. * Copyright (c) 2006-2007 Wind River Systems, Inc.
  5. *
  6. * Paul Gortmaker <paul.gortmaker@windriver.com>
  7. * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
  8. */
  9. #include <common.h>
  10. #include <fdt_support.h>
  11. #include <ioports.h>
  12. #include <mpc83xx.h>
  13. #include <asm/mpc8349_pci.h>
  14. #include <i2c.h>
  15. #include <spd_sdram.h>
  16. #include <miiphy.h>
  17. #if defined(CONFIG_OF_LIBFDT)
  18. #include <linux/libfdt.h>
  19. #endif
  20. DECLARE_GLOBAL_DATA_PTR;
  21. int fixed_sdram(void);
  22. void sdram_init(void);
  23. #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
  24. void ddr_enable_ecc(unsigned int dram_size);
  25. #endif
  26. #ifdef CONFIG_BOARD_EARLY_INIT_F
  27. int board_early_init_f (void)
  28. {
  29. return 0;
  30. }
  31. #endif
  32. #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
  33. int dram_init(void)
  34. {
  35. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  36. u32 msize = 0;
  37. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
  38. return -1;
  39. /* DDR SDRAM - Main SODIMM */
  40. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
  41. #if defined(CONFIG_SPD_EEPROM)
  42. msize = spd_sdram();
  43. #else
  44. msize = fixed_sdram();
  45. #endif
  46. /*
  47. * Initialize SDRAM if it is on local bus.
  48. */
  49. sdram_init();
  50. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  51. /*
  52. * Initialize and enable DDR ECC.
  53. */
  54. ddr_enable_ecc(msize * 1024 * 1024);
  55. #endif
  56. /* set total bus SDRAM size(bytes) -- DDR */
  57. gd->ram_size = msize * 1024 * 1024;
  58. return 0;
  59. }
  60. #if !defined(CONFIG_SPD_EEPROM)
  61. /*************************************************************************
  62. * fixed sdram init -- doesn't use serial presence detect.
  63. ************************************************************************/
  64. int fixed_sdram(void)
  65. {
  66. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  67. u32 msize = CONFIG_SYS_DDR_SIZE;
  68. u32 ddr_size = msize << 20; /* DDR size in bytes */
  69. u32 ddr_size_log2 = __ilog2(msize);
  70. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
  71. im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
  72. #if (CONFIG_SYS_DDR_SIZE != 256)
  73. #warning Currently any ddr size other than 256 is not supported
  74. #endif
  75. #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
  76. #warning Chip select bounds is only configurable in 16MB increments
  77. #endif
  78. im->ddr.csbnds[2].csbnds =
  79. ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  80. (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
  81. CSBNDS_EA_SHIFT) & CSBNDS_EA);
  82. im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
  83. /* currently we use only one CS, so disable the other banks */
  84. im->ddr.cs_config[0] = 0;
  85. im->ddr.cs_config[1] = 0;
  86. im->ddr.cs_config[3] = 0;
  87. im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  88. im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  89. im->ddr.sdram_cfg =
  90. SDRAM_CFG_SREN
  91. #if defined(CONFIG_DDR_2T_TIMING)
  92. | SDRAM_CFG_2T_EN
  93. #endif
  94. | SDRAM_CFG_SDRAM_TYPE_DDR1;
  95. #if defined (CONFIG_DDR_32BIT)
  96. /* for 32-bit mode burst length is 8 */
  97. im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
  98. #endif
  99. im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
  100. im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  101. udelay(200);
  102. /* enable DDR controller */
  103. im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  104. return msize;
  105. }
  106. #endif/*!CONFIG_SYS_SPD_EEPROM*/
  107. int checkboard (void)
  108. {
  109. puts("Board: Wind River SBC834x\n");
  110. return 0;
  111. }
  112. /*
  113. * if board is fitted with SDRAM
  114. */
  115. #if defined(CONFIG_SYS_BR2_PRELIM) \
  116. && defined(CONFIG_SYS_OR2_PRELIM) \
  117. && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
  118. && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
  119. /*
  120. * Initialize SDRAM memory on the Local Bus.
  121. */
  122. void sdram_init(void)
  123. {
  124. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  125. volatile fsl_lbc_t *lbc = &immap->im_lbc;
  126. uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
  127. const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
  128. LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
  129. LSDMR_WRC3 | LSDMR_CL3;
  130. puts("\n SDRAM on Local Bus: ");
  131. print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
  132. /*
  133. * Setup SDRAM Base and Option Registers, already done in cpu_init.c
  134. */
  135. /* setup mtrpt, lsrt and lbcr for LB bus */
  136. lbc->lbcr = 0x00000000;
  137. /* LB refresh timer prescal, 266MHz/32 */
  138. lbc->mrtpr = 0x20000000;
  139. /* LB sdram refresh timer, about 6us */
  140. lbc->lsrt = 0x32000000;
  141. asm("sync");
  142. /*
  143. * Configure the SDRAM controller Machine Mode Register.
  144. */
  145. /* 0x40636733; normal operation */
  146. lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
  147. /* 0x68636733; precharge all the banks */
  148. lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
  149. asm("sync");
  150. *sdram_addr = 0xff;
  151. udelay(100);
  152. /* 0x48636733; auto refresh */
  153. lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
  154. asm("sync");
  155. /*1 times*/
  156. *sdram_addr = 0xff;
  157. udelay(100);
  158. /*2 times*/
  159. *sdram_addr = 0xff;
  160. udelay(100);
  161. /*3 times*/
  162. *sdram_addr = 0xff;
  163. udelay(100);
  164. /*4 times*/
  165. *sdram_addr = 0xff;
  166. udelay(100);
  167. /*5 times*/
  168. *sdram_addr = 0xff;
  169. udelay(100);
  170. /*6 times*/
  171. *sdram_addr = 0xff;
  172. udelay(100);
  173. /*7 times*/
  174. *sdram_addr = 0xff;
  175. udelay(100);
  176. /*8 times*/
  177. *sdram_addr = 0xff;
  178. udelay(100);
  179. /* 0x58636733; mode register write operation */
  180. lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
  181. asm("sync");
  182. *sdram_addr = 0xff;
  183. udelay(100);
  184. /* 0x40636733; normal operation */
  185. lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
  186. asm("sync");
  187. *sdram_addr = 0xff;
  188. udelay(100);
  189. }
  190. #else
  191. void sdram_init(void)
  192. {
  193. puts(" SDRAM on Local Bus: Disabled in config\n");
  194. }
  195. #endif
  196. #if defined(CONFIG_OF_BOARD_SETUP)
  197. int ft_board_setup(void *blob, bd_t *bd)
  198. {
  199. ft_cpu_setup(blob, bd);
  200. #ifdef CONFIG_PCI
  201. ft_pci_setup(blob, bd);
  202. #endif
  203. return 0;
  204. }
  205. #endif