Kconfig 29 KB

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  1. menu "x86 architecture"
  2. depends on X86
  3. config SYS_ARCH
  4. default "x86"
  5. choice
  6. prompt "Run U-Boot in 32/64-bit mode"
  7. default X86_RUN_32BIT
  8. help
  9. U-Boot can be built as a 32-bit binary which runs in 32-bit mode
  10. even on 64-bit machines. In this case SPL is not used, and U-Boot
  11. runs directly from the reset vector (via 16-bit start-up).
  12. Alternatively it can be run as a 64-bit binary, thus requiring a
  13. 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
  14. start-up) then jumps to U-Boot in 64-bit mode.
  15. For now, 32-bit mode is recommended, as 64-bit is still
  16. experimental and is missing a lot of features.
  17. config X86_RUN_32BIT
  18. bool "32-bit"
  19. help
  20. Build U-Boot as a 32-bit binary with no SPL. This is the currently
  21. supported normal setup. U-Boot will stay in 32-bit mode even on
  22. 64-bit machines. When booting a 64-bit kernel, U-Boot will switch
  23. to 64-bit just before starting the kernel. Only the bottom 4GB of
  24. memory can be accessed through normal means, although
  25. arch_phys_memset() can be used for basic access to other memory.
  26. config X86_RUN_64BIT
  27. bool "64-bit"
  28. select X86_64
  29. select SPL
  30. select SPL_SEPARATE_BSS
  31. help
  32. Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
  33. experimental and many features are missing. U-Boot SPL starts up,
  34. runs through the 16-bit and 32-bit init, then switches to 64-bit
  35. mode and jumps to U-Boot proper.
  36. endchoice
  37. config X86_64
  38. bool
  39. config SPL_X86_64
  40. bool
  41. depends on SPL
  42. choice
  43. prompt "Mainboard vendor"
  44. default VENDOR_EMULATION
  45. config VENDOR_ADVANTECH
  46. bool "advantech"
  47. config VENDOR_CONGATEC
  48. bool "congatec"
  49. config VENDOR_COREBOOT
  50. bool "coreboot"
  51. config VENDOR_DFI
  52. bool "dfi"
  53. config VENDOR_EFI
  54. bool "efi"
  55. config VENDOR_EMULATION
  56. bool "emulation"
  57. config VENDOR_GOOGLE
  58. bool "Google"
  59. config VENDOR_INTEL
  60. bool "Intel"
  61. endchoice
  62. # subarchitectures-specific options below
  63. config INTEL_MID
  64. bool "Intel MID platform support"
  65. select REGMAP
  66. select SYSCON
  67. help
  68. Select to build a U-Boot capable of supporting Intel MID
  69. (Mobile Internet Device) platform systems which do not have
  70. the PCI legacy interfaces.
  71. If you are building for a PC class system say N here.
  72. Intel MID platforms are based on an Intel processor and
  73. chipset which consume less power than most of the x86
  74. derivatives.
  75. # board-specific options below
  76. source "board/advantech/Kconfig"
  77. source "board/congatec/Kconfig"
  78. source "board/coreboot/Kconfig"
  79. source "board/dfi/Kconfig"
  80. source "board/efi/Kconfig"
  81. source "board/emulation/Kconfig"
  82. source "board/google/Kconfig"
  83. source "board/intel/Kconfig"
  84. # platform-specific options below
  85. source "arch/x86/cpu/apollolake/Kconfig"
  86. source "arch/x86/cpu/baytrail/Kconfig"
  87. source "arch/x86/cpu/braswell/Kconfig"
  88. source "arch/x86/cpu/broadwell/Kconfig"
  89. source "arch/x86/cpu/coreboot/Kconfig"
  90. source "arch/x86/cpu/ivybridge/Kconfig"
  91. source "arch/x86/cpu/efi/Kconfig"
  92. source "arch/x86/cpu/qemu/Kconfig"
  93. source "arch/x86/cpu/quark/Kconfig"
  94. source "arch/x86/cpu/queensbay/Kconfig"
  95. source "arch/x86/cpu/slimbootloader/Kconfig"
  96. source "arch/x86/cpu/tangier/Kconfig"
  97. # architecture-specific options below
  98. config AHCI
  99. default y
  100. config SYS_MALLOC_F_LEN
  101. default 0x800
  102. config RAMBASE
  103. hex
  104. default 0x100000
  105. config XIP_ROM_SIZE
  106. hex
  107. depends on X86_RESET_VECTOR
  108. default ROM_SIZE
  109. config CPU_ADDR_BITS
  110. int
  111. default 36
  112. config HPET_ADDRESS
  113. hex
  114. default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
  115. config SMM_TSEG
  116. bool
  117. default n
  118. config SMM_TSEG_SIZE
  119. hex
  120. config X86_RESET_VECTOR
  121. bool
  122. default n
  123. select BINMAN
  124. # The following options control where the 16-bit and 32-bit init lies
  125. # If SPL is enabled then it normally holds this init code, and U-Boot proper
  126. # is normally a 64-bit build.
  127. #
  128. # The 16-bit init refers to the reset vector and the small amount of code to
  129. # get the processor into 32-bit mode. It may be in SPL or in U-Boot proper,
  130. # or missing altogether if U-Boot is started from EFI or coreboot.
  131. #
  132. # The 32-bit init refers to processor init, running binary blobs including
  133. # FSP, setting up interrupts and anything else that needs to be done in
  134. # 32-bit code. It is normally in the same place as 16-bit init if that is
  135. # enabled (i.e. they are both in SPL, or both in U-Boot proper).
  136. config X86_16BIT_INIT
  137. bool
  138. depends on X86_RESET_VECTOR
  139. default y if X86_RESET_VECTOR && !SPL
  140. help
  141. This is enabled when 16-bit init is in U-Boot proper
  142. config SPL_X86_16BIT_INIT
  143. bool
  144. depends on X86_RESET_VECTOR
  145. default y if X86_RESET_VECTOR && SPL && !TPL
  146. help
  147. This is enabled when 16-bit init is in SPL
  148. config TPL_X86_16BIT_INIT
  149. bool
  150. depends on X86_RESET_VECTOR
  151. default y if X86_RESET_VECTOR && TPL
  152. help
  153. This is enabled when 16-bit init is in TPL
  154. config X86_32BIT_INIT
  155. bool
  156. depends on X86_RESET_VECTOR
  157. default y if X86_RESET_VECTOR && !SPL
  158. help
  159. This is enabled when 32-bit init is in U-Boot proper
  160. config SPL_X86_32BIT_INIT
  161. bool
  162. depends on X86_RESET_VECTOR
  163. default y if X86_RESET_VECTOR && SPL
  164. help
  165. This is enabled when 32-bit init is in SPL
  166. config RESET_SEG_START
  167. hex
  168. depends on X86_RESET_VECTOR
  169. default 0xffff0000
  170. config RESET_VEC_LOC
  171. hex
  172. depends on X86_RESET_VECTOR
  173. default 0xfffffff0
  174. config SYS_X86_START16
  175. hex
  176. depends on X86_RESET_VECTOR
  177. default 0xfffff800
  178. config HAVE_X86_FIT
  179. bool
  180. help
  181. Enable inclusion of an Intel Firmware Interface Table (FIT) into the
  182. image. This table is supposed to point to microcode and the like. So
  183. far it is just a fixed table with the minimum set of headers, so that
  184. it is actually present.
  185. config X86_LOAD_FROM_32_BIT
  186. bool "Boot from a 32-bit program"
  187. help
  188. Define this to boot U-Boot from a 32-bit program which sets
  189. the GDT differently. This can be used to boot directly from
  190. any stage of coreboot, for example, bypassing the normal
  191. payload-loading feature.
  192. config BOARD_ROMSIZE_KB_512
  193. bool
  194. config BOARD_ROMSIZE_KB_1024
  195. bool
  196. config BOARD_ROMSIZE_KB_2048
  197. bool
  198. config BOARD_ROMSIZE_KB_4096
  199. bool
  200. config BOARD_ROMSIZE_KB_8192
  201. bool
  202. config BOARD_ROMSIZE_KB_16384
  203. bool
  204. choice
  205. prompt "ROM chip size"
  206. depends on X86_RESET_VECTOR
  207. default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
  208. default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
  209. default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
  210. default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
  211. default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
  212. default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
  213. help
  214. Select the size of the ROM chip you intend to flash U-Boot on.
  215. The build system will take care of creating a u-boot.rom file
  216. of the matching size.
  217. config UBOOT_ROMSIZE_KB_512
  218. bool "512 KB"
  219. help
  220. Choose this option if you have a 512 KB ROM chip.
  221. config UBOOT_ROMSIZE_KB_1024
  222. bool "1024 KB (1 MB)"
  223. help
  224. Choose this option if you have a 1024 KB (1 MB) ROM chip.
  225. config UBOOT_ROMSIZE_KB_2048
  226. bool "2048 KB (2 MB)"
  227. help
  228. Choose this option if you have a 2048 KB (2 MB) ROM chip.
  229. config UBOOT_ROMSIZE_KB_4096
  230. bool "4096 KB (4 MB)"
  231. help
  232. Choose this option if you have a 4096 KB (4 MB) ROM chip.
  233. config UBOOT_ROMSIZE_KB_8192
  234. bool "8192 KB (8 MB)"
  235. help
  236. Choose this option if you have a 8192 KB (8 MB) ROM chip.
  237. config UBOOT_ROMSIZE_KB_16384
  238. bool "16384 KB (16 MB)"
  239. help
  240. Choose this option if you have a 16384 KB (16 MB) ROM chip.
  241. endchoice
  242. # Map the config names to an integer (KB).
  243. config UBOOT_ROMSIZE_KB
  244. int
  245. default 512 if UBOOT_ROMSIZE_KB_512
  246. default 1024 if UBOOT_ROMSIZE_KB_1024
  247. default 2048 if UBOOT_ROMSIZE_KB_2048
  248. default 4096 if UBOOT_ROMSIZE_KB_4096
  249. default 8192 if UBOOT_ROMSIZE_KB_8192
  250. default 16384 if UBOOT_ROMSIZE_KB_16384
  251. # Map the config names to a hex value (bytes).
  252. config ROM_SIZE
  253. hex
  254. default 0x80000 if UBOOT_ROMSIZE_KB_512
  255. default 0x100000 if UBOOT_ROMSIZE_KB_1024
  256. default 0x200000 if UBOOT_ROMSIZE_KB_2048
  257. default 0x400000 if UBOOT_ROMSIZE_KB_4096
  258. default 0x800000 if UBOOT_ROMSIZE_KB_8192
  259. default 0xc00000 if UBOOT_ROMSIZE_KB_12288
  260. default 0x1000000 if UBOOT_ROMSIZE_KB_16384
  261. config HAVE_INTEL_ME
  262. bool "Platform requires Intel Management Engine"
  263. help
  264. Newer higher-end devices have an Intel Management Engine (ME)
  265. which is a very large binary blob (typically 1.5MB) which is
  266. required for the platform to work. This enforces a particular
  267. SPI flash format. You will need to supply the me.bin file in
  268. your board directory.
  269. config X86_RAMTEST
  270. bool "Perform a simple RAM test after SDRAM initialisation"
  271. help
  272. If there is something wrong with SDRAM then the platform will
  273. often crash within U-Boot or the kernel. This option enables a
  274. very simple RAM test that quickly checks whether the SDRAM seems
  275. to work correctly. It is not exhaustive but can save time by
  276. detecting obvious failures.
  277. config FLASH_DESCRIPTOR_FILE
  278. string "Flash descriptor binary filename"
  279. depends on HAVE_INTEL_ME || FSP_VERSION2
  280. default "descriptor.bin"
  281. help
  282. The filename of the file to use as flash descriptor in the
  283. board directory.
  284. config INTEL_ME_FILE
  285. string "Intel Management Engine binary filename"
  286. depends on HAVE_INTEL_ME
  287. default "me.bin"
  288. help
  289. The filename of the file to use as Intel Management Engine in the
  290. board directory.
  291. config USE_HOB
  292. bool "Use HOB (Hand-Off Block)"
  293. help
  294. Select this option to access HOB (Hand-Off Block) data structures
  295. and parse HOBs. This HOB infra structure can be reused with
  296. different solutions across different platforms.
  297. config HAVE_FSP
  298. bool "Add an Firmware Support Package binary"
  299. depends on !EFI
  300. select USE_HOB
  301. help
  302. Select this option to add an Firmware Support Package binary to
  303. the resulting U-Boot image. It is a binary blob which U-Boot uses
  304. to set up SDRAM and other chipset specific initialization.
  305. Note: Without this binary U-Boot will not be able to set up its
  306. SDRAM so will not boot.
  307. config USE_CAR
  308. bool "Use Cache-As-RAM (CAR) to get temporary RAM at start-up"
  309. default y if !HAVE_FSP
  310. help
  311. Select this option if your board uses CAR init code, typically in a
  312. car.S file, to get some initial memory for code execution. This is
  313. common with Intel CPUs which don't use FSP.
  314. choice
  315. prompt "FSP version"
  316. depends on HAVE_FSP
  317. default FSP_VERSION1
  318. help
  319. Selects the FSP version to use. Intel has published several versions
  320. of the FSP External Architecture Specification and this allows
  321. selection of the version number used by a particular SoC.
  322. config FSP_VERSION1
  323. bool "FSP version 1.x"
  324. help
  325. This covers versions 1.0 and 1.1a. See here for details:
  326. https://github.com/IntelFsp/fsp/wiki
  327. config FSP_VERSION2
  328. bool "FSP version 2.x"
  329. help
  330. This covers versions 2.0 and 2.1. See here for details:
  331. https://github.com/IntelFsp/fsp/wiki
  332. endchoice
  333. config FSP_FILE
  334. string "Firmware Support Package binary filename"
  335. depends on FSP_VERSION1
  336. default "fsp.bin"
  337. help
  338. The filename of the file to use as Firmware Support Package binary
  339. in the board directory.
  340. config FSP_ADDR
  341. hex "Firmware Support Package binary location"
  342. depends on FSP_VERSION1
  343. default 0xfffc0000
  344. help
  345. FSP is not Position Independent Code (PIC) and the whole FSP has to
  346. be rebased if it is placed at a location which is different from the
  347. perferred base address specified during the FSP build. Use Intel's
  348. Binary Configuration Tool (BCT) to do the rebase.
  349. The default base address of 0xfffc0000 indicates that the binary must
  350. be located at offset 0xc0000 from the beginning of a 1MB flash device.
  351. if FSP_VERSION2
  352. config FSP_FILE_T
  353. string "Firmware Support Package binary filename (Temp RAM)"
  354. default "fsp_t.bin"
  355. help
  356. The filename of the file to use for the temporary-RAM init phase from
  357. the Firmware Support Package binary. Put this in the board directory.
  358. It is used to set up an initial area of RAM which can be used for the
  359. stack and other purposes, while bringing up the main system DRAM.
  360. config FSP_ADDR_T
  361. hex "Firmware Support Package binary location (Temp RAM)"
  362. default 0xffff8000
  363. help
  364. FSP is not Position-Independent Code (PIC) and FSP components have to
  365. be rebased if placed at a location which is different from the
  366. perferred base address specified during the FSP build. Use Intel's
  367. Binary Configuration Tool (BCT) to do the rebase.
  368. config FSP_FILE_M
  369. string "Firmware Support Package binary filename (Memory Init)"
  370. default "fsp_m.bin"
  371. help
  372. The filename of the file to use for the RAM init phase from the
  373. Firmware Support Package binary. Put this in the board directory.
  374. It is used to set up the main system DRAM and runs in SPL, once
  375. temporary RAM (CAR) is working.
  376. config FSP_FILE_S
  377. string "Firmware Support Package binary filename (Silicon Init)"
  378. default "fsp_s.bin"
  379. help
  380. The filename of the file to use for the Silicon init phase from the
  381. Firmware Support Package binary. Put this in the board directory.
  382. It is used to set up the silicon to work correctly and must be
  383. executed after DRAM is running.
  384. config IFWI_INPUT_FILE
  385. string "Filename containing FIT (Firmware Interface Table) with IFWI"
  386. default "fitimage.bin"
  387. help
  388. The IFWI is obtained by running a tool on this file to extract the
  389. IFWI. Put this in the board directory. The IFWI contains U-Boot TPL,
  390. microcode and other internal items.
  391. endif
  392. config FSP_TEMP_RAM_ADDR
  393. hex
  394. depends on FSP_VERSION1
  395. default 0x2000000
  396. help
  397. Stack top address which is used in fsp_init() after DRAM is ready and
  398. CAR is disabled.
  399. config FSP_SYS_MALLOC_F_LEN
  400. hex
  401. depends on FSP_VERSION1
  402. default 0x100000
  403. help
  404. Additional size of malloc() pool before relocation.
  405. config FSP_USE_UPD
  406. bool
  407. depends on FSP_VERSION1
  408. default y
  409. help
  410. Most FSPs use UPD data region for some FSP customization. But there
  411. are still some FSPs that might not even have UPD. For such FSPs,
  412. override this to n in their platform Kconfig files.
  413. config FSP_BROKEN_HOB
  414. bool
  415. depends on FSP_VERSION1
  416. help
  417. Indicate some buggy FSPs that does not report memory used by FSP
  418. itself as reserved in the resource descriptor HOB. Select this to
  419. tell U-Boot to do some additional work to ensure U-Boot relocation
  420. do not overwrite the important boot service data which is used by
  421. FSP, otherwise the subsequent call to fsp_notify() will fail.
  422. config ENABLE_MRC_CACHE
  423. bool "Enable MRC cache"
  424. depends on !EFI && !SYS_COREBOOT
  425. help
  426. Enable this feature to cause MRC data to be cached in NV storage
  427. to be used for speeding up boot time on future reboots and/or
  428. power cycles.
  429. For platforms that use Intel FSP for the memory initialization,
  430. please check FSP output HOB via U-Boot command 'fsp hob' to see
  431. if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp1/fsp_hob.h).
  432. If such GUID does not exist, MRC cache is not available on such
  433. platform (eg: Intel Queensbay), which means selecting this option
  434. here does not make any difference.
  435. config HAVE_MRC
  436. bool "Add a System Agent binary"
  437. depends on !HAVE_FSP
  438. help
  439. Select this option to add a System Agent binary to
  440. the resulting U-Boot image. MRC stands for Memory Reference Code.
  441. It is a binary blob which U-Boot uses to set up SDRAM.
  442. Note: Without this binary U-Boot will not be able to set up its
  443. SDRAM so will not boot.
  444. config CACHE_MRC_BIN
  445. bool
  446. depends on HAVE_MRC
  447. default n
  448. help
  449. Enable caching for the memory reference code binary. This uses an
  450. MTRR (memory type range register) to turn on caching for the section
  451. of SPI flash that contains the memory reference code. This makes
  452. SDRAM init run faster.
  453. config CACHE_MRC_SIZE_KB
  454. int
  455. depends on HAVE_MRC
  456. default 512
  457. help
  458. Sets the size of the cached area for the memory reference code.
  459. This ends at the end of SPI flash (address 0xffffffff) and is
  460. measured in KB. Typically this is set to 512, providing for 0.5MB
  461. of cached space.
  462. config DCACHE_RAM_BASE
  463. hex
  464. depends on HAVE_MRC
  465. help
  466. Sets the base of the data cache area in memory space. This is the
  467. start address of the cache-as-RAM (CAR) area and the address varies
  468. depending on the CPU. Once CAR is set up, read/write memory becomes
  469. available at this address and can be used temporarily until SDRAM
  470. is working.
  471. config DCACHE_RAM_SIZE
  472. hex
  473. depends on HAVE_MRC
  474. default 0x40000
  475. help
  476. Sets the total size of the data cache area in memory space. This
  477. sets the size of the cache-as-RAM (CAR) area. Note that much of the
  478. CAR space is required by the MRC. The CAR space available to U-Boot
  479. is normally at the start and typically extends to 1/4 or 1/2 of the
  480. available size.
  481. config DCACHE_RAM_MRC_VAR_SIZE
  482. hex
  483. depends on HAVE_MRC
  484. help
  485. This is the amount of CAR (Cache as RAM) reserved for use by the
  486. memory reference code. This depends on the implementation of the
  487. memory reference code and must be set correctly or the board will
  488. not boot.
  489. config HAVE_REFCODE
  490. bool "Add a Reference Code binary"
  491. help
  492. Select this option to add a Reference Code binary to the resulting
  493. U-Boot image. This is an Intel binary blob that handles system
  494. initialisation, in this case the PCH and System Agent.
  495. Note: Without this binary (on platforms that need it such as
  496. broadwell) U-Boot will be missing some critical setup steps.
  497. Various peripherals may fail to work.
  498. config HAVE_MICROCODE
  499. bool
  500. default y if !FSP_VERSION2
  501. config SMP
  502. bool "Enable Symmetric Multiprocessing"
  503. default n
  504. help
  505. Enable use of more than one CPU in U-Boot and the Operating System
  506. when loaded. Each CPU will be started up and information can be
  507. obtained using the 'cpu' command. If this option is disabled, then
  508. only one CPU will be enabled regardless of the number of CPUs
  509. available.
  510. config MAX_CPUS
  511. int "Maximum number of CPUs permitted"
  512. depends on SMP
  513. default 4
  514. help
  515. When using multi-CPU chips it is possible for U-Boot to start up
  516. more than one CPU. The stack memory used by all of these CPUs is
  517. pre-allocated so at present U-Boot wants to know the maximum
  518. number of CPUs that may be present. Set this to at least as high
  519. as the number of CPUs in your system (it uses about 4KB of RAM for
  520. each CPU).
  521. config AP_STACK_SIZE
  522. hex
  523. depends on SMP
  524. default 0x1000
  525. help
  526. Each additional CPU started by U-Boot requires its own stack. This
  527. option sets the stack size used by each CPU and directly affects
  528. the memory used by this initialisation process. Typically 4KB is
  529. enough space.
  530. config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
  531. bool
  532. help
  533. This option indicates that the turbo mode setting is not package
  534. scoped. i.e. turbo_enable() needs to be called on not just the
  535. bootstrap processor (BSP).
  536. config HAVE_VGA_BIOS
  537. bool "Add a VGA BIOS image"
  538. help
  539. Select this option if you have a VGA BIOS image that you would
  540. like to add to your ROM.
  541. config VGA_BIOS_FILE
  542. string "VGA BIOS image filename"
  543. depends on HAVE_VGA_BIOS
  544. default "vga.bin"
  545. help
  546. The filename of the VGA BIOS image in the board directory.
  547. config VGA_BIOS_ADDR
  548. hex "VGA BIOS image location"
  549. depends on HAVE_VGA_BIOS
  550. default 0xfff90000
  551. help
  552. The location of VGA BIOS image in the SPI flash. For example, base
  553. address of 0xfff90000 indicates that the image will be put at offset
  554. 0x90000 from the beginning of a 1MB flash device.
  555. config HAVE_VBT
  556. bool "Add a Video BIOS Table (VBT) image"
  557. depends on HAVE_FSP
  558. help
  559. Select this option if you have a Video BIOS Table (VBT) image that
  560. you would like to add to your ROM. This is normally required if you
  561. are using an Intel FSP firmware that is complaint with spec 1.1 or
  562. later to initialize the integrated graphics device (IGD).
  563. Video BIOS Table, or VBT, provides platform and board specific
  564. configuration information to the driver that is not discoverable
  565. or available through other means. By other means the most used
  566. method here is to read EDID table from the attached monitor, over
  567. Display Data Channel (DDC) using two pin I2C serial interface. VBT
  568. configuration is related to display hardware and is available via
  569. the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
  570. config VBT_FILE
  571. string "Video BIOS Table (VBT) image filename"
  572. depends on HAVE_VBT
  573. default "vbt.bin"
  574. help
  575. The filename of the file to use as Video BIOS Table (VBT) image
  576. in the board directory.
  577. config VBT_ADDR
  578. hex "Video BIOS Table (VBT) image location"
  579. depends on HAVE_VBT
  580. default 0xfff90000
  581. help
  582. The location of Video BIOS Table (VBT) image in the SPI flash. For
  583. example, base address of 0xfff90000 indicates that the image will
  584. be put at offset 0x90000 from the beginning of a 1MB flash device.
  585. config VIDEO_FSP
  586. bool "Enable FSP framebuffer driver support"
  587. depends on HAVE_VBT && DM_VIDEO
  588. help
  589. Turn on this option to enable a framebuffer driver when U-Boot is
  590. using Video BIOS Table (VBT) image for FSP firmware to initialize
  591. the integrated graphics device.
  592. config ROM_TABLE_ADDR
  593. hex
  594. default 0xf0000
  595. help
  596. All x86 tables happen to like the address range from 0x0f0000
  597. to 0x100000. We use 0xf0000 as the starting address to store
  598. those tables, including PIRQ routing table, Multi-Processor
  599. table and ACPI table.
  600. config ROM_TABLE_SIZE
  601. hex
  602. default 0x10000
  603. config HAVE_ITSS
  604. bool "Enable ITSS"
  605. help
  606. Select this to include the driver for the Interrupt Timer
  607. Subsystem (ITSS) which is found on several Intel devices.
  608. config HAVE_P2SB
  609. bool "Enable P2SB"
  610. help
  611. Select this to include the driver for the Primary to
  612. Sideband Bridge (P2SB) which is found on several Intel
  613. devices.
  614. menu "System tables"
  615. depends on !EFI && !SYS_COREBOOT
  616. config GENERATE_PIRQ_TABLE
  617. bool "Generate a PIRQ table"
  618. default n
  619. help
  620. Generate a PIRQ routing table for this board. The PIRQ routing table
  621. is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
  622. at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
  623. It specifies the interrupt router information as well how all the PCI
  624. devices' interrupt pins are wired to PIRQs.
  625. config GENERATE_SFI_TABLE
  626. bool "Generate a SFI (Simple Firmware Interface) table"
  627. help
  628. The Simple Firmware Interface (SFI) provides a lightweight method
  629. for platform firmware to pass information to the operating system
  630. via static tables in memory. Kernel SFI support is required to
  631. boot on SFI-only platforms. If you have ACPI tables then these are
  632. used instead.
  633. U-Boot writes this table in write_sfi_table() just before booting
  634. the OS.
  635. For more information, see http://simplefirmware.org
  636. config GENERATE_MP_TABLE
  637. bool "Generate an MP (Multi-Processor) table"
  638. default n
  639. help
  640. Generate an MP (Multi-Processor) table for this board. The MP table
  641. provides a way for the operating system to support for symmetric
  642. multiprocessing as well as symmetric I/O interrupt handling with
  643. the local APIC and I/O APIC.
  644. config GENERATE_ACPI_TABLE
  645. bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
  646. default n
  647. select QFW if QEMU
  648. help
  649. The Advanced Configuration and Power Interface (ACPI) specification
  650. provides an open standard for device configuration and management
  651. by the operating system. It defines platform-independent interfaces
  652. for configuration and power management monitoring.
  653. endmenu
  654. config HAVE_ACPI_RESUME
  655. bool "Enable ACPI S3 resume"
  656. select ENABLE_MRC_CACHE
  657. help
  658. Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping
  659. state where all system context is lost except system memory. U-Boot
  660. is responsible for restoring the machine state as it was before sleep.
  661. It needs restore the memory controller, without overwriting memory
  662. which is not marked as reserved. For the peripherals which lose their
  663. registers, U-Boot needs to write the original value. When everything
  664. is done, U-Boot needs to find out the wakeup vector provided by OSes
  665. and jump there.
  666. config S3_VGA_ROM_RUN
  667. bool "Re-run VGA option ROMs on S3 resume"
  668. depends on HAVE_ACPI_RESUME
  669. help
  670. Execute VGA option ROMs in U-Boot when resuming from S3. Normally
  671. this is needed when graphics console is being used in the kernel.
  672. Turning it off can reduce some resume time, but be aware that your
  673. graphics console won't work without VGA options ROMs. Set it to N
  674. if your kernel is only on a serial console.
  675. config STACK_SIZE
  676. hex
  677. depends on HAVE_ACPI_RESUME
  678. default 0x1000
  679. help
  680. Estimated U-Boot's runtime stack size that needs to be reserved
  681. during an ACPI S3 resume.
  682. config MAX_PIRQ_LINKS
  683. int
  684. default 8
  685. help
  686. This variable specifies the number of PIRQ interrupt links which are
  687. routable. On most older chipsets, this is 4, PIRQA through PIRQD.
  688. Some newer chipsets offer more than four links, commonly up to PIRQH.
  689. config IRQ_SLOT_COUNT
  690. int
  691. default 128
  692. help
  693. U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
  694. which in turns forms a table of exact 4KiB. The default value 128
  695. should be enough for most boards. If this does not fit your board,
  696. change it according to your needs.
  697. config PCIE_ECAM_BASE
  698. hex
  699. default 0xe0000000
  700. help
  701. This is the memory-mapped address of PCI configuration space, which
  702. is only available through the Enhanced Configuration Access
  703. Mechanism (ECAM) with PCI Express. It can be set up almost
  704. anywhere. Before it is set up, it is possible to access PCI
  705. configuration space through I/O access, but memory access is more
  706. convenient. Using this, PCI can be scanned and configured. This
  707. should be set to a region that does not conflict with memory
  708. assigned to PCI devices - i.e. the memory and prefetch regions, as
  709. passed to pci_set_region().
  710. config PCIE_ECAM_SIZE
  711. hex
  712. default 0x10000000
  713. help
  714. This is the size of memory-mapped address of PCI configuration space,
  715. which is only available through the Enhanced Configuration Access
  716. Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
  717. so a default 0x10000000 size covers all of the 256 buses which is the
  718. maximum number of PCI buses as defined by the PCI specification.
  719. config I8259_PIC
  720. bool "Enable Intel 8259 compatible interrupt controller"
  721. default y
  722. help
  723. Intel 8259 ISA compatible chipset incorporates two 8259 (master and
  724. slave) interrupt controllers. Include this to have U-Boot set up
  725. the interrupt correctly.
  726. config APIC
  727. bool "Enable Intel Advanced Programmable Interrupt Controller"
  728. default y
  729. help
  730. The (A)dvanced (P)rogrammable (I)nterrupt (C)ontroller is responsible
  731. for catching interrupts and distributing them to one or more CPU
  732. cores. In most cases there are some LAPICs (local) for each core and
  733. one I/O APIC. This conjunction is found on most modern x86 systems.
  734. config PINCTRL_ICH6
  735. bool
  736. help
  737. Intel ICH6 compatible chipset pinctrl driver. It needs to work
  738. together with the ICH6 compatible gpio driver.
  739. config I8254_TIMER
  740. bool
  741. default y
  742. help
  743. Intel 8254 timer contains three counters which have fixed uses.
  744. Include this to have U-Boot set up the timer correctly.
  745. config SEABIOS
  746. bool "Support booting SeaBIOS"
  747. help
  748. SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
  749. It can run in an emulator or natively on X86 hardware with the use
  750. of coreboot/U-Boot. By turning on this option, U-Boot prepares
  751. all the configuration tables that are necessary to boot SeaBIOS.
  752. Check http://www.seabios.org/SeaBIOS for details.
  753. config HIGH_TABLE_SIZE
  754. hex "Size of configuration tables which reside in high memory"
  755. default 0x10000
  756. depends on SEABIOS
  757. help
  758. SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
  759. configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
  760. puts a copy of configuration tables in high memory region which
  761. is reserved on the stack before relocation. The region size is
  762. determined by this option.
  763. Increse it if the default size does not fit the board's needs.
  764. This is most likely due to a large ACPI DSDT table is used.
  765. config INTEL_CAR_CQOS
  766. bool "Support Intel Cache Quality of Service"
  767. help
  768. Cache Quality of Service allows more fine-grained control of cache
  769. usage. As result, it is possible to set up a portion of L2 cache for
  770. CAR and use the remainder for actual caching.
  771. #
  772. # Each bit in QOS mask controls this many bytes. This is calculated as:
  773. # (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS
  774. #
  775. config CACHE_QOS_SIZE_PER_BIT
  776. hex
  777. depends on INTEL_CAR_CQOS
  778. default 0x20000 # 128 KB
  779. config X86_OFFSET_U_BOOT
  780. hex "Offset of U-Boot in ROM image"
  781. depends on HAVE_SYS_TEXT_BASE
  782. default SYS_TEXT_BASE
  783. config X86_OFFSET_SPL
  784. hex "Offset of SPL in ROM image"
  785. depends on SPL && X86
  786. default SPL_TEXT_BASE
  787. config ACPI_GPE
  788. bool "Support ACPI general-purpose events"
  789. help
  790. Enable a driver for ACPI GPEs to allow peripherals to send interrupts
  791. via ACPI to the OS. In U-Boot this is only used when U-Boot itself
  792. needs access to these interrupts. This can happen when it uses a
  793. peripheral that is set up to use GPEs and so cannot use the normal
  794. GPIO mechanism for polling an input.
  795. See https://queue.acm.org/blogposting.cfm?id=18977 for more info
  796. config SPL_ACPI_GPE
  797. bool "Support ACPI general-purpose events in SPL"
  798. help
  799. Enable a driver for ACPI GPEs to allow peripherals to send interrupts
  800. via ACPI to the OS. In U-Boot this is only used when U-Boot itself
  801. needs access to these interrupts. This can happen when it uses a
  802. peripheral that is set up to use GPEs and so cannot use the normal
  803. GPIO mechanism for polling an input.
  804. See https://queue.acm.org/blogposting.cfm?id=18977 for more info
  805. config TPL_ACPI_GPE
  806. bool "Support ACPI general-purpose events in TPL"
  807. help
  808. Enable a driver for ACPI GPEs to allow peripherals to send interrupts
  809. via ACPI to the OS. In U-Boot this is only used when U-Boot itself
  810. needs access to these interrupts. This can happen when it uses a
  811. peripheral that is set up to use GPEs and so cannot use the normal
  812. GPIO mechanism for polling an input.
  813. See https://queue.acm.org/blogposting.cfm?id=18977 for more info
  814. endmenu