Kconfig 6.2 KB

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  1. menu "RISC-V architecture"
  2. depends on RISCV
  3. config SYS_ARCH
  4. default "riscv"
  5. choice
  6. prompt "Target select"
  7. optional
  8. config TARGET_AX25_AE350
  9. bool "Support ax25-ae350"
  10. config TARGET_MICROCHIP_ICICLE
  11. bool "Support Microchip PolarFire-SoC Icicle Board"
  12. config TARGET_QEMU_VIRT
  13. bool "Support QEMU Virt Board"
  14. config TARGET_SIFIVE_FU540
  15. bool "Support SiFive FU540 Board"
  16. endchoice
  17. config SYS_ICACHE_OFF
  18. bool "Do not enable icache"
  19. default n
  20. help
  21. Do not enable instruction cache in U-Boot.
  22. config SPL_SYS_ICACHE_OFF
  23. bool "Do not enable icache in SPL"
  24. depends on SPL
  25. default SYS_ICACHE_OFF
  26. help
  27. Do not enable instruction cache in SPL.
  28. config SYS_DCACHE_OFF
  29. bool "Do not enable dcache"
  30. default n
  31. help
  32. Do not enable data cache in U-Boot.
  33. config SPL_SYS_DCACHE_OFF
  34. bool "Do not enable dcache in SPL"
  35. depends on SPL
  36. default SYS_DCACHE_OFF
  37. help
  38. Do not enable data cache in SPL.
  39. # board-specific options below
  40. source "board/AndesTech/ax25-ae350/Kconfig"
  41. source "board/emulation/qemu-riscv/Kconfig"
  42. source "board/microchip/mpfs_icicle/Kconfig"
  43. source "board/sifive/fu540/Kconfig"
  44. # platform-specific options below
  45. source "arch/riscv/cpu/ax25/Kconfig"
  46. source "arch/riscv/cpu/generic/Kconfig"
  47. # architecture-specific options below
  48. choice
  49. prompt "Base ISA"
  50. default ARCH_RV32I
  51. config ARCH_RV32I
  52. bool "RV32I"
  53. select 32BIT
  54. help
  55. Choose this option to target the RV32I base integer instruction set.
  56. config ARCH_RV64I
  57. bool "RV64I"
  58. select 64BIT
  59. select PHYS_64BIT
  60. help
  61. Choose this option to target the RV64I base integer instruction set.
  62. endchoice
  63. choice
  64. prompt "Code Model"
  65. default CMODEL_MEDLOW
  66. config CMODEL_MEDLOW
  67. bool "medium low code model"
  68. help
  69. U-Boot and its statically defined symbols must lie within a single 2 GiB
  70. address range and must lie between absolute addresses -2 GiB and +2 GiB.
  71. config CMODEL_MEDANY
  72. bool "medium any code model"
  73. help
  74. U-Boot and its statically defined symbols must be within any single 2 GiB
  75. address range.
  76. endchoice
  77. choice
  78. prompt "Run Mode"
  79. default RISCV_MMODE
  80. config RISCV_MMODE
  81. bool "Machine"
  82. help
  83. Choose this option to build U-Boot for RISC-V M-Mode.
  84. config RISCV_SMODE
  85. bool "Supervisor"
  86. help
  87. Choose this option to build U-Boot for RISC-V S-Mode.
  88. endchoice
  89. choice
  90. prompt "SPL Run Mode"
  91. default SPL_RISCV_MMODE
  92. depends on SPL
  93. config SPL_RISCV_MMODE
  94. bool "Machine"
  95. help
  96. Choose this option to build U-Boot SPL for RISC-V M-Mode.
  97. config SPL_RISCV_SMODE
  98. bool "Supervisor"
  99. help
  100. Choose this option to build U-Boot SPL for RISC-V S-Mode.
  101. endchoice
  102. config RISCV_ISA_C
  103. bool "Emit compressed instructions"
  104. default y
  105. help
  106. Adds "C" to the ISA subsets that the toolchain is allowed to emit
  107. when building U-Boot, which results in compressed instructions in the
  108. U-Boot binary.
  109. config RISCV_ISA_A
  110. def_bool y
  111. config 32BIT
  112. bool
  113. config 64BIT
  114. bool
  115. config SIFIVE_CLINT
  116. bool
  117. depends on RISCV_MMODE || SPL_RISCV_MMODE
  118. select REGMAP
  119. select SYSCON
  120. select SPL_REGMAP if SPL
  121. select SPL_SYSCON if SPL
  122. help
  123. The SiFive CLINT block holds memory-mapped control and status registers
  124. associated with software and timer interrupts.
  125. config ANDES_PLIC
  126. bool
  127. depends on RISCV_MMODE || SPL_RISCV_MMODE
  128. select REGMAP
  129. select SYSCON
  130. select SPL_REGMAP if SPL
  131. select SPL_SYSCON if SPL
  132. help
  133. The Andes PLIC block holds memory-mapped claim and pending registers
  134. associated with software interrupt.
  135. config ANDES_PLMT
  136. bool
  137. depends on RISCV_MMODE || SPL_RISCV_MMODE
  138. select REGMAP
  139. select SYSCON
  140. select SPL_REGMAP if SPL
  141. select SPL_SYSCON if SPL
  142. help
  143. The Andes PLMT block holds memory-mapped mtime register
  144. associated with timer tick.
  145. config RISCV_RDTIME
  146. bool
  147. default y if RISCV_SMODE || SPL_RISCV_SMODE
  148. help
  149. The provides the riscv_get_time() API that is implemented using the
  150. standard rdtime instruction. This is the case for S-mode U-Boot, and
  151. is useful for processors that support rdtime in M-mode too.
  152. config SYS_MALLOC_F_LEN
  153. default 0x1000
  154. config SMP
  155. bool "Symmetric Multi-Processing"
  156. depends on SBI_V01 || !RISCV_SMODE
  157. help
  158. This enables support for systems with more than one CPU. If
  159. you say N here, U-Boot will run on single and multiprocessor
  160. machines, but will use only one CPU of a multiprocessor
  161. machine. If you say Y here, U-Boot will run on many, but not
  162. all, single processor machines.
  163. config SPL_SMP
  164. bool "Symmetric Multi-Processing in SPL"
  165. depends on SPL && SPL_RISCV_MMODE
  166. default y
  167. help
  168. This enables support for systems with more than one CPU in SPL.
  169. If you say N here, U-Boot SPL will run on single and multiprocessor
  170. machines, but will use only one CPU of a multiprocessor
  171. machine. If you say Y here, U-Boot SPL will run on many, but not
  172. all, single processor machines.
  173. config NR_CPUS
  174. int "Maximum number of CPUs (2-32)"
  175. range 2 32
  176. depends on SMP || SPL_SMP
  177. default 8
  178. help
  179. On multiprocessor machines, U-Boot sets up a stack for each CPU.
  180. Stack memory is pre-allocated. U-Boot must therefore know the
  181. maximum number of CPUs that may be present.
  182. config SBI
  183. bool
  184. default y if RISCV_SMODE || SPL_RISCV_SMODE
  185. choice
  186. prompt "SBI support"
  187. default SBI_V02
  188. config SBI_V01
  189. bool "SBI v0.1 support"
  190. depends on SBI
  191. help
  192. This config allows kernel to use SBI v0.1 APIs. This will be
  193. deprecated in future once legacy M-mode software are no longer in use.
  194. config SBI_V02
  195. bool "SBI v0.2 support"
  196. depends on SBI
  197. help
  198. This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
  199. scalable and extendable to handle future needs for RISC-V supervisor
  200. interfaces. For example, with SBI v0.2 HSM extension, only a single
  201. hart need to boot and enter operating system. The booting hart can
  202. bring up secondary harts one by one afterwards.
  203. Choose this option if OpenSBI v0.7 or above release is used together
  204. with U-Boot.
  205. endchoice
  206. config SBI_IPI
  207. bool
  208. depends on SBI
  209. default y if RISCV_SMODE || SPL_RISCV_SMODE
  210. depends on SMP
  211. config XIP
  212. bool "XIP mode"
  213. help
  214. XIP (eXecute In Place) is a method for executing code directly
  215. from a NOR flash memory without copying the code to ram.
  216. Say yes here if U-Boot boots from flash directly.
  217. config SHOW_REGS
  218. bool "Show registers on unhandled exception"
  219. config STACK_SIZE_SHIFT
  220. int
  221. default 14
  222. endmenu