taurus.h 5.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Common board functions for Siemens TAURUS (AT91SAM9G20) based boards
  4. * (C) Copyright 2013 Siemens AG
  5. *
  6. * Based on:
  7. * U-Boot file: include/configs/at91sam9260ek.h
  8. *
  9. * (C) Copyright 2007-2008
  10. * Stelian Pop <stelian@popies.net>
  11. * Lead Tech Design <www.leadtechdesign.com>
  12. */
  13. #ifndef __CONFIG_H
  14. #define __CONFIG_H
  15. /*
  16. * SoC must be defined first, before hardware.h is included.
  17. * In this case SoC is defined in boards.cfg.
  18. */
  19. #include <asm/hardware.h>
  20. #include <linux/sizes.h>
  21. #if defined(CONFIG_SPL_BUILD)
  22. #define CONFIG_SYS_ICACHE_OFF
  23. #define CONFIG_SYS_DCACHE_OFF
  24. #endif
  25. /*
  26. * Warning: changing CONFIG_SYS_TEXT_BASE requires
  27. * adapting the initial boot program.
  28. * Since the linker has to swallow that define, we must use a pure
  29. * hex number here!
  30. */
  31. /* ARM asynchronous clock */
  32. #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
  33. #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
  34. /* Misc CPU related */
  35. #define CONFIG_ARCH_CPU_INIT
  36. #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  37. #define CONFIG_SETUP_MEMORY_TAGS
  38. #define CONFIG_INITRD_TAG
  39. #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
  40. /* general purpose I/O */
  41. #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
  42. #define CONFIG_AT91_GPIO
  43. #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
  44. /* serial console */
  45. #define CONFIG_ATMEL_USART
  46. #define CONFIG_USART_BASE ATMEL_BASE_DBGU
  47. #define CONFIG_USART_ID ATMEL_ID_SYS
  48. /*
  49. * SDRAM: 1 bank, min 32, max 128 MB
  50. * Initialized before u-boot gets started.
  51. */
  52. #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
  53. #define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M)
  54. /*
  55. * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
  56. * leaving the correct space for initial global data structure above
  57. * that address while providing maximum stack area below.
  58. */
  59. #define CONFIG_SYS_INIT_SP_ADDR \
  60. (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
  61. /* NAND flash */
  62. #ifdef CONFIG_CMD_NAND
  63. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  64. #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
  65. #define CONFIG_SYS_NAND_DBW_8
  66. #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
  67. #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
  68. #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
  69. #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
  70. #endif
  71. /* Ethernet */
  72. #define CONFIG_MACB
  73. #define CONFIG_RMII
  74. #define CONFIG_AT91_WANTS_COMMON_PHY
  75. /* USB */
  76. #if defined(CONFIG_BOARD_TAURUS)
  77. #define CONFIG_USB_ATMEL
  78. #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
  79. #define CONFIG_USB_OHCI_NEW
  80. #define CONFIG_SYS_USB_OHCI_CPU_INIT
  81. #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
  82. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
  83. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
  84. /* USB DFU support */
  85. #define CONFIG_USB_GADGET_AT91
  86. /* DFU class support */
  87. #define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
  88. #define DFU_MANIFEST_POLL_TIMEOUT 25000
  89. #endif
  90. /* SPI EEPROM */
  91. #define TAURUS_SPI_MASK (1 << 4)
  92. #define TAURUS_SPI_CS_PIN AT91_PIN_PA3
  93. #if defined(CONFIG_SPL_BUILD)
  94. /* SPL related */
  95. #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
  96. #define CONFIG_SF_DEFAULT_BUS 0
  97. #define CONFIG_SF_DEFAULT_SPEED 1000000
  98. #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
  99. #endif
  100. /* load address */
  101. #define CONFIG_SYS_LOAD_ADDR 0x22000000
  102. /* bootstrap in spi flash , u-boot + env + linux in nandflash */
  103. #define CONFIG_ENV_OFFSET 0x100000
  104. #define CONFIG_ENV_OFFSET_REDUND 0x180000
  105. #define CONFIG_ENV_SIZE (SZ_128K) /* 1 sector = 128 kB */
  106. #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
  107. /*
  108. * Size of malloc() pool
  109. */
  110. #define CONFIG_SYS_MALLOC_LEN \
  111. ROUND(3 * CONFIG_ENV_SIZE + SZ_4M, 0x1000)
  112. /* Defines for SPL */
  113. #define CONFIG_SPL_TEXT_BASE 0x0
  114. #define CONFIG_SPL_MAX_SIZE (31 * SZ_512)
  115. #define CONFIG_SPL_STACK (ATMEL_BASE_SRAM1 + SZ_16K)
  116. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
  117. CONFIG_SYS_MALLOC_LEN)
  118. #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
  119. #define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE
  120. #define CONFIG_SPL_BSS_MAX_SIZE (3 * SZ_512)
  121. #define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
  122. #define CONFIG_SYS_USE_NANDFLASH 1
  123. #define CONFIG_SPL_NAND_DRIVERS
  124. #define CONFIG_SPL_NAND_BASE
  125. #define CONFIG_SPL_NAND_ECC
  126. #define CONFIG_SPL_NAND_RAW_ONLY
  127. #define CONFIG_SPL_NAND_SOFTECC
  128. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
  129. #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
  130. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  131. #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  132. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  133. #define CONFIG_SYS_NAND_SIZE (256 * SZ_1M)
  134. #define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K
  135. #define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K)
  136. #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
  137. CONFIG_SYS_NAND_PAGE_SIZE)
  138. #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  139. #define CONFIG_SYS_NAND_ECCSIZE 256
  140. #define CONFIG_SYS_NAND_ECCBYTES 3
  141. #define CONFIG_SYS_NAND_OOBSIZE 64
  142. #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
  143. 48, 49, 50, 51, 52, 53, 54, 55, \
  144. 56, 57, 58, 59, 60, 61, 62, 63, }
  145. #define CONFIG_SPL_ATMEL_SIZE
  146. #define CONFIG_SYS_MASTER_CLOCK 132096000
  147. #define AT91_PLL_LOCK_TIMEOUT 1000000
  148. #define CONFIG_SYS_AT91_PLLA 0x202A3F01
  149. #define CONFIG_SYS_MCKR 0x1300
  150. #define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
  151. #define CONFIG_SYS_AT91_PLLB 0x10193F05
  152. #endif