at91sam9_wdt.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * [origin: Linux kernel drivers/watchdog/at91sam9_wdt.c]
  4. *
  5. * Watchdog driver for AT91SAM9x processors.
  6. *
  7. * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  8. * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
  9. */
  10. /*
  11. * The Watchdog Timer Mode Register can be only written to once. If the
  12. * timeout need to be set from U-Boot, be sure that the bootstrap doesn't
  13. * write to this register. Inform Linux to it too
  14. */
  15. #include <asm/io.h>
  16. #include <asm/arch/at91_wdt.h>
  17. #include <common.h>
  18. #include <dm.h>
  19. #include <errno.h>
  20. #include <wdt.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. /*
  23. * AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
  24. * use this to convert a watchdog
  25. * value from seconds.
  26. */
  27. #define WDT_SEC2TICKS(s) (((s) << 8) - 1)
  28. /* Hardware timeout in seconds */
  29. #define WDT_MAX_TIMEOUT 16
  30. #define WDT_MIN_TIMEOUT 0
  31. #define WDT_DEFAULT_TIMEOUT 2
  32. struct at91_wdt_priv {
  33. void __iomem *regs;
  34. u32 regval;
  35. u32 timeout;
  36. };
  37. /*
  38. * Set the watchdog time interval in 1/256Hz (write-once)
  39. * Counter is 12 bit.
  40. */
  41. static int at91_wdt_start(struct udevice *dev, u64 timeout_s, ulong flags)
  42. {
  43. struct at91_wdt_priv *priv = dev_get_priv(dev);
  44. u32 timeout = WDT_SEC2TICKS(timeout_s);
  45. if (timeout_s > WDT_MAX_TIMEOUT || timeout_s < WDT_MIN_TIMEOUT)
  46. timeout = priv->timeout;
  47. /* Check if disabled */
  48. if (readl(priv->regs + AT91_WDT_MR) & AT91_WDT_MR_WDDIS) {
  49. printf("sorry, watchdog is disabled\n");
  50. return -1;
  51. }
  52. /*
  53. * All counting occurs at SLOW_CLOCK / 128 = 256 Hz
  54. *
  55. * Since WDV is a 12-bit counter, the maximum period is
  56. * 4096 / 256 = 16 seconds.
  57. */
  58. priv->regval = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */
  59. | AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */
  60. | AT91_WDT_MR_WDD(0xfff) /* restart at any time */
  61. | AT91_WDT_MR_WDV(timeout); /* timer value */
  62. writel(priv->regval, priv->regs + AT91_WDT_MR);
  63. return 0;
  64. }
  65. static int at91_wdt_stop(struct udevice *dev)
  66. {
  67. struct at91_wdt_priv *priv = dev_get_priv(dev);
  68. /* Disable Watchdog Timer */
  69. priv->regval |= AT91_WDT_MR_WDDIS;
  70. writel(priv->regval, priv->regs + AT91_WDT_MR);
  71. return 0;
  72. }
  73. static int at91_wdt_reset(struct udevice *dev)
  74. {
  75. struct at91_wdt_priv *priv = dev_get_priv(dev);
  76. writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, priv->regs + AT91_WDT_CR);
  77. return 0;
  78. }
  79. static const struct wdt_ops at91_wdt_ops = {
  80. .start = at91_wdt_start,
  81. .stop = at91_wdt_stop,
  82. .reset = at91_wdt_reset,
  83. };
  84. static const struct udevice_id at91_wdt_ids[] = {
  85. { .compatible = "atmel,at91sam9260-wdt" },
  86. {}
  87. };
  88. static int at91_wdt_probe(struct udevice *dev)
  89. {
  90. struct at91_wdt_priv *priv = dev_get_priv(dev);
  91. priv->regs = dev_remap_addr(dev);
  92. if (!priv->regs)
  93. return -EINVAL;
  94. #ifdef CONFIG_AT91_HW_WDT_TIMEOUT
  95. priv->timeout = dev_read_u32_default(dev, "timeout-sec",
  96. WDT_DEFAULT_TIMEOUT);
  97. debug("%s: timeout %d", __func__, priv->timeout);
  98. #endif
  99. debug("%s: Probing wdt%u\n", __func__, dev->seq);
  100. return 0;
  101. }
  102. U_BOOT_DRIVER(at91_wdt) = {
  103. .name = "at91_wdt",
  104. .id = UCLASS_WDT,
  105. .of_match = at91_wdt_ids,
  106. .priv_auto_alloc_size = sizeof(struct at91_wdt_priv),
  107. .ops = &at91_wdt_ops,
  108. .probe = at91_wdt_probe,
  109. };