spl_at91.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 DENX Software Engineering
  4. * Heiko Schocher <hs@denx.de>
  5. *
  6. * Based on:
  7. * Copyright (C) 2013 Atmel Corporation
  8. * Bo Shen <voice.shen@atmel.com>
  9. */
  10. #include <common.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/at91_common.h>
  13. #include <asm/arch/at91sam9_matrix.h>
  14. #include <asm/arch/at91_pit.h>
  15. #include <asm/arch/at91_rstc.h>
  16. #include <asm/arch/at91_wdt.h>
  17. #include <asm/arch/clk.h>
  18. #include <spl.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. static void enable_ext_reset(void)
  21. {
  22. struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
  23. writel(AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN, &rstc->mr);
  24. }
  25. void lowlevel_clock_init(void)
  26. {
  27. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  28. if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) {
  29. /* Enable Main Oscillator */
  30. writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor);
  31. /* Wait until Main Oscillator is stable */
  32. while (!(readl(&pmc->sr) & AT91_PMC_MOSCS))
  33. ;
  34. }
  35. /* After stabilization, switch to Main Oscillator */
  36. if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) {
  37. unsigned long tmp;
  38. tmp = readl(&pmc->mckr);
  39. tmp &= ~AT91_PMC_CSS;
  40. tmp |= AT91_PMC_CSS_MAIN;
  41. writel(tmp, &pmc->mckr);
  42. while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
  43. ;
  44. tmp &= ~AT91_PMC_PRES;
  45. tmp |= AT91_PMC_PRES_1;
  46. writel(tmp, &pmc->mckr);
  47. while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
  48. ;
  49. }
  50. return;
  51. }
  52. void __weak matrix_init(void)
  53. {
  54. }
  55. void __weak at91_spl_board_init(void)
  56. {
  57. }
  58. void __weak spl_board_init(void)
  59. {
  60. }
  61. void board_init_f(ulong dummy)
  62. {
  63. lowlevel_clock_init();
  64. #if !defined(CONFIG_WDT_AT91)
  65. at91_disable_wdt();
  66. #endif
  67. /*
  68. * At this stage the main oscillator is supposed to be enabled
  69. * PCK = MCK = MOSC
  70. */
  71. at91_pllicpr_init(0x00);
  72. /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
  73. at91_plla_init(CONFIG_SYS_AT91_PLLA);
  74. /* PCK = PLLA = 2 * MCK */
  75. at91_mck_init(CONFIG_SYS_MCKR);
  76. /* Switch MCK on PLLA output */
  77. at91_mck_init(CONFIG_SYS_MCKR_CSS);
  78. #if defined(CONFIG_SYS_AT91_PLLB)
  79. /* Configure PLLB */
  80. at91_pllb_init(CONFIG_SYS_AT91_PLLB);
  81. #endif
  82. /* Enable External Reset */
  83. enable_ext_reset();
  84. /* Initialize matrix */
  85. matrix_init();
  86. gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK;
  87. /*
  88. * init timer long enough for using in spl.
  89. */
  90. timer_init();
  91. /* enable clocks for all PIOs */
  92. #if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
  93. at91_periph_clk_enable(ATMEL_ID_PIOAB);
  94. at91_periph_clk_enable(ATMEL_ID_PIOCD);
  95. #else
  96. at91_periph_clk_enable(ATMEL_ID_PIOA);
  97. at91_periph_clk_enable(ATMEL_ID_PIOB);
  98. at91_periph_clk_enable(ATMEL_ID_PIOC);
  99. #endif
  100. #if defined(CONFIG_SPL_SERIAL_SUPPORT)
  101. /* init console */
  102. at91_seriald_hw_init();
  103. preloader_console_init();
  104. #endif
  105. mem_init();
  106. at91_spl_board_init();
  107. }