mys_6ulx.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2020 Linumiz
  4. * Author: Parthiban Nallathambi <parthiban@linumiz.com>
  5. */
  6. #include <init.h>
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/crm_regs.h>
  9. #include <asm/arch/mx6-pins.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <asm/mach-imx/iomux-v3.h>
  12. #include <asm/mach-imx/mxc_i2c.h>
  13. #include <fsl_esdhc_imx.h>
  14. #include <linux/bitops.h>
  15. #include <miiphy.h>
  16. #include <netdev.h>
  17. #include <usb.h>
  18. #include <usb/ehci-ci.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. int dram_init(void)
  21. {
  22. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  23. return 0;
  24. }
  25. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  26. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  27. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \
  28. PAD_CTL_HYS)
  29. static iomux_v3_cfg_t const uart1_pads[] = {
  30. MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  31. MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  32. };
  33. static iomux_v3_cfg_t const uart5_pads[] = {
  34. MX6_PAD_UART5_TX_DATA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  35. MX6_PAD_UART5_RX_DATA__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  36. MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  37. MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  38. };
  39. static void setup_iomux_uart(void)
  40. {
  41. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  42. imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
  43. }
  44. #ifdef CONFIG_FEC_MXC
  45. static int setup_fec(void)
  46. {
  47. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  48. int ret;
  49. /*
  50. * Use 50M anatop loopback REF_CLK1 for ENET1,
  51. * clear gpr1[13], set gpr1[17].
  52. */
  53. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  54. IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
  55. ret = enable_fec_anatop_clock(0, ENET_50MHZ);
  56. if (ret)
  57. return ret;
  58. enable_enet_clk(1);
  59. return 0;
  60. }
  61. int board_phy_config(struct phy_device *phydev)
  62. {
  63. /*
  64. * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
  65. * 50 MHz RMII clock mode.
  66. */
  67. phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
  68. if (phydev->drv->config)
  69. phydev->drv->config(phydev);
  70. return 0;
  71. }
  72. #endif /* CONFIG_FEC_MXC */
  73. int board_early_init_f(void)
  74. {
  75. setup_iomux_uart();
  76. return 0;
  77. }
  78. int board_init(void)
  79. {
  80. /* Address of boot parameters */
  81. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  82. #ifdef CONFIG_FEC_MXC
  83. setup_fec();
  84. #endif
  85. return 0;
  86. }
  87. int checkboard(void)
  88. {
  89. u32 cpurev = get_cpu_rev();
  90. printf("Board: MYiR MYS-6ULX %s Single Board Computer\n",
  91. get_imx_type((cpurev & 0xFF000) >> 12));
  92. return 0;
  93. }