pm.h 1.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2015-2016 Intel Corp.
  4. * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
  5. * Copyright 2019 Google LLC
  6. */
  7. #ifndef _ASM_ARCH_PM_H
  8. #define _ASM_ARCH_PM_H
  9. #include <power/acpi_pmc.h>
  10. #define PMC_GPE_SW_31_0 0
  11. #define PMC_GPE_SW_63_32 1
  12. #define PMC_GPE_NW_31_0 3
  13. #define PMC_GPE_NW_63_32 4
  14. #define PMC_GPE_NW_95_64 5
  15. #define PMC_GPE_N_31_0 6
  16. #define PMC_GPE_N_63_32 7
  17. #define PMC_GPE_W_31_0 9
  18. #define IRQ_REG 0x106c
  19. #define SCI_IRQ_SHIFT 24
  20. #define SCI_IRQ_MASK (0xff << SCI_IRQ_SHIFT)
  21. #define SCIS_IRQ9 9
  22. #define SCIS_IRQ10 10
  23. #define SCIS_IRQ11 11
  24. #define SCIS_IRQ20 20
  25. #define SCIS_IRQ21 21
  26. #define SCIS_IRQ22 22
  27. #define SCIS_IRQ23 23
  28. /* P-state configuration */
  29. #define PSS_MAX_ENTRIES 8
  30. #define PSS_RATIO_STEP 2
  31. #define PSS_LATENCY_TRANSITION 10
  32. #define PSS_LATENCY_BUSMASTER 10
  33. #ifndef __ASSEMBLY__
  34. /* Track power state from reset to log events */
  35. struct __packed chipset_power_state {
  36. u16 pm1_sts;
  37. u16 pm1_en;
  38. u32 pm1_cnt;
  39. u32 gpe0_sts[GPE0_REG_MAX];
  40. u32 gpe0_en[GPE0_REG_MAX];
  41. u16 tco1_sts;
  42. u16 tco2_sts;
  43. u32 prsts;
  44. u32 gen_pmcon1;
  45. u32 gen_pmcon2;
  46. u32 gen_pmcon3;
  47. u32 prev_sleep_state;
  48. };
  49. #endif /* !__ASSEMBLY__ */
  50. #endif