zynq_spi.c 9.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 Xilinx, Inc.
  4. * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
  5. *
  6. * Xilinx Zynq PS SPI controller driver (master mode only)
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <malloc.h>
  11. #include <spi.h>
  12. #include <time.h>
  13. #include <asm/io.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
  16. #define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */
  17. #define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */
  18. #define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */
  19. #define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
  20. #define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */
  21. #define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
  22. #define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */
  23. #define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
  24. #define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
  25. #define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
  26. #define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
  27. #define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
  28. #define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
  29. #define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */
  30. #define ZYNQ_SPI_FIFO_DEPTH 128
  31. #ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
  32. #define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
  33. #endif
  34. /* zynq spi register set */
  35. struct zynq_spi_regs {
  36. u32 cr; /* 0x00 */
  37. u32 isr; /* 0x04 */
  38. u32 ier; /* 0x08 */
  39. u32 idr; /* 0x0C */
  40. u32 imr; /* 0x10 */
  41. u32 enr; /* 0x14 */
  42. u32 dr; /* 0x18 */
  43. u32 txdr; /* 0x1C */
  44. u32 rxdr; /* 0x20 */
  45. };
  46. /* zynq spi platform data */
  47. struct zynq_spi_platdata {
  48. struct zynq_spi_regs *regs;
  49. u32 frequency; /* input frequency */
  50. u32 speed_hz;
  51. uint deactivate_delay_us; /* Delay to wait after deactivate */
  52. uint activate_delay_us; /* Delay to wait after activate */
  53. };
  54. /* zynq spi priv */
  55. struct zynq_spi_priv {
  56. struct zynq_spi_regs *regs;
  57. u8 cs;
  58. u8 mode;
  59. ulong last_transaction_us; /* Time of last transaction end */
  60. u8 fifo_depth;
  61. u32 freq; /* required frequency */
  62. };
  63. static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
  64. {
  65. struct zynq_spi_platdata *plat = bus->platdata;
  66. const void *blob = gd->fdt_blob;
  67. int node = dev_of_offset(bus);
  68. plat->regs = (struct zynq_spi_regs *)devfdt_get_addr(bus);
  69. /* FIXME: Use 250MHz as a suitable default */
  70. plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
  71. 250000000);
  72. plat->deactivate_delay_us = fdtdec_get_int(blob, node,
  73. "spi-deactivate-delay", 0);
  74. plat->activate_delay_us = fdtdec_get_int(blob, node,
  75. "spi-activate-delay", 0);
  76. plat->speed_hz = plat->frequency / 2;
  77. debug("%s: regs=%p max-frequency=%d\n", __func__,
  78. plat->regs, plat->frequency);
  79. return 0;
  80. }
  81. static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
  82. {
  83. struct zynq_spi_regs *regs = priv->regs;
  84. u32 confr;
  85. /* Disable SPI */
  86. confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
  87. writel(~confr, &regs->enr);
  88. /* Disable Interrupts */
  89. writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->idr);
  90. /* Clear RX FIFO */
  91. while (readl(&regs->isr) &
  92. ZYNQ_SPI_IXR_RXNEMPTY_MASK)
  93. readl(&regs->rxdr);
  94. /* Clear Interrupts */
  95. writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->isr);
  96. /* Manual slave select and Auto start */
  97. confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
  98. ZYNQ_SPI_CR_MSTREN_MASK;
  99. confr &= ~ZYNQ_SPI_CR_MSA_MASK;
  100. writel(confr, &regs->cr);
  101. /* Enable SPI */
  102. writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
  103. }
  104. static int zynq_spi_probe(struct udevice *bus)
  105. {
  106. struct zynq_spi_platdata *plat = dev_get_platdata(bus);
  107. struct zynq_spi_priv *priv = dev_get_priv(bus);
  108. priv->regs = plat->regs;
  109. priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
  110. /* init the zynq spi hw */
  111. zynq_spi_init_hw(priv);
  112. return 0;
  113. }
  114. static void spi_cs_activate(struct udevice *dev)
  115. {
  116. struct udevice *bus = dev->parent;
  117. struct zynq_spi_platdata *plat = bus->platdata;
  118. struct zynq_spi_priv *priv = dev_get_priv(bus);
  119. struct zynq_spi_regs *regs = priv->regs;
  120. u32 cr;
  121. /* If it's too soon to do another transaction, wait */
  122. if (plat->deactivate_delay_us && priv->last_transaction_us) {
  123. ulong delay_us; /* The delay completed so far */
  124. delay_us = timer_get_us() - priv->last_transaction_us;
  125. if (delay_us < plat->deactivate_delay_us)
  126. udelay(plat->deactivate_delay_us - delay_us);
  127. }
  128. clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
  129. cr = readl(&regs->cr);
  130. /*
  131. * CS cal logic: CS[13:10]
  132. * xxx0 - cs0
  133. * xx01 - cs1
  134. * x011 - cs2
  135. */
  136. cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
  137. writel(cr, &regs->cr);
  138. if (plat->activate_delay_us)
  139. udelay(plat->activate_delay_us);
  140. }
  141. static void spi_cs_deactivate(struct udevice *dev)
  142. {
  143. struct udevice *bus = dev->parent;
  144. struct zynq_spi_platdata *plat = bus->platdata;
  145. struct zynq_spi_priv *priv = dev_get_priv(bus);
  146. struct zynq_spi_regs *regs = priv->regs;
  147. setbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
  148. /* Remember time of this transaction so we can honour the bus delay */
  149. if (plat->deactivate_delay_us)
  150. priv->last_transaction_us = timer_get_us();
  151. }
  152. static int zynq_spi_claim_bus(struct udevice *dev)
  153. {
  154. struct udevice *bus = dev->parent;
  155. struct zynq_spi_priv *priv = dev_get_priv(bus);
  156. struct zynq_spi_regs *regs = priv->regs;
  157. writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
  158. return 0;
  159. }
  160. static int zynq_spi_release_bus(struct udevice *dev)
  161. {
  162. struct udevice *bus = dev->parent;
  163. struct zynq_spi_priv *priv = dev_get_priv(bus);
  164. struct zynq_spi_regs *regs = priv->regs;
  165. u32 confr;
  166. confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
  167. writel(~confr, &regs->enr);
  168. return 0;
  169. }
  170. static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
  171. const void *dout, void *din, unsigned long flags)
  172. {
  173. struct udevice *bus = dev->parent;
  174. struct zynq_spi_priv *priv = dev_get_priv(bus);
  175. struct zynq_spi_regs *regs = priv->regs;
  176. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  177. u32 len = bitlen / 8;
  178. u32 tx_len = len, rx_len = len, tx_tvl;
  179. const u8 *tx_buf = dout;
  180. u8 *rx_buf = din, buf;
  181. u32 ts, status;
  182. debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
  183. bus->seq, slave_plat->cs, bitlen, len, flags);
  184. if (bitlen % 8) {
  185. debug("spi_xfer: Non byte aligned SPI transfer\n");
  186. return -1;
  187. }
  188. priv->cs = slave_plat->cs;
  189. if (flags & SPI_XFER_BEGIN)
  190. spi_cs_activate(dev);
  191. while (rx_len > 0) {
  192. /* Write the data into TX FIFO - tx threshold is fifo_depth */
  193. tx_tvl = 0;
  194. while ((tx_tvl < priv->fifo_depth) && tx_len) {
  195. if (tx_buf)
  196. buf = *tx_buf++;
  197. else
  198. buf = 0;
  199. writel(buf, &regs->txdr);
  200. tx_len--;
  201. tx_tvl++;
  202. }
  203. /* Check TX FIFO completion */
  204. ts = get_timer(0);
  205. status = readl(&regs->isr);
  206. while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
  207. if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) {
  208. printf("spi_xfer: Timeout! TX FIFO not full\n");
  209. return -1;
  210. }
  211. status = readl(&regs->isr);
  212. }
  213. /* Read the data from RX FIFO */
  214. status = readl(&regs->isr);
  215. while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
  216. buf = readl(&regs->rxdr);
  217. if (rx_buf)
  218. *rx_buf++ = buf;
  219. status = readl(&regs->isr);
  220. rx_len--;
  221. }
  222. }
  223. if (flags & SPI_XFER_END)
  224. spi_cs_deactivate(dev);
  225. return 0;
  226. }
  227. static int zynq_spi_set_speed(struct udevice *bus, uint speed)
  228. {
  229. struct zynq_spi_platdata *plat = bus->platdata;
  230. struct zynq_spi_priv *priv = dev_get_priv(bus);
  231. struct zynq_spi_regs *regs = priv->regs;
  232. uint32_t confr;
  233. u8 baud_rate_val = 0;
  234. if (speed > plat->frequency)
  235. speed = plat->frequency;
  236. /* Set the clock frequency */
  237. confr = readl(&regs->cr);
  238. if (speed == 0) {
  239. /* Set baudrate x8, if the freq is 0 */
  240. baud_rate_val = 0x2;
  241. } else if (plat->speed_hz != speed) {
  242. while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) &&
  243. ((plat->frequency /
  244. (2 << baud_rate_val)) > speed))
  245. baud_rate_val++;
  246. plat->speed_hz = speed / (2 << baud_rate_val);
  247. }
  248. confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
  249. confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);
  250. writel(confr, &regs->cr);
  251. priv->freq = speed;
  252. debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
  253. priv->regs, priv->freq);
  254. return 0;
  255. }
  256. static int zynq_spi_set_mode(struct udevice *bus, uint mode)
  257. {
  258. struct zynq_spi_priv *priv = dev_get_priv(bus);
  259. struct zynq_spi_regs *regs = priv->regs;
  260. uint32_t confr;
  261. /* Set the SPI Clock phase and polarities */
  262. confr = readl(&regs->cr);
  263. confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
  264. if (mode & SPI_CPHA)
  265. confr |= ZYNQ_SPI_CR_CPHA_MASK;
  266. if (mode & SPI_CPOL)
  267. confr |= ZYNQ_SPI_CR_CPOL_MASK;
  268. writel(confr, &regs->cr);
  269. priv->mode = mode;
  270. debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);
  271. return 0;
  272. }
  273. static const struct dm_spi_ops zynq_spi_ops = {
  274. .claim_bus = zynq_spi_claim_bus,
  275. .release_bus = zynq_spi_release_bus,
  276. .xfer = zynq_spi_xfer,
  277. .set_speed = zynq_spi_set_speed,
  278. .set_mode = zynq_spi_set_mode,
  279. };
  280. static const struct udevice_id zynq_spi_ids[] = {
  281. { .compatible = "xlnx,zynq-spi-r1p6" },
  282. { .compatible = "cdns,spi-r1p6" },
  283. { }
  284. };
  285. U_BOOT_DRIVER(zynq_spi) = {
  286. .name = "zynq_spi",
  287. .id = UCLASS_SPI,
  288. .of_match = zynq_spi_ids,
  289. .ops = &zynq_spi_ops,
  290. .ofdata_to_platdata = zynq_spi_ofdata_to_platdata,
  291. .platdata_auto_alloc_size = sizeof(struct zynq_spi_platdata),
  292. .priv_auto_alloc_size = sizeof(struct zynq_spi_priv),
  293. .probe = zynq_spi_probe,
  294. };