tegra210_qspi.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * NVIDIA Tegra210 QSPI controller driver
  4. *
  5. * (C) Copyright 2015 NVIDIA Corporation <www.nvidia.com>
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <time.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch-tegra/clk_rst.h>
  13. #include <spi.h>
  14. #include <fdtdec.h>
  15. #include "tegra_spi.h"
  16. DECLARE_GLOBAL_DATA_PTR;
  17. /* COMMAND1 */
  18. #define QSPI_CMD1_GO BIT(31)
  19. #define QSPI_CMD1_M_S BIT(30)
  20. #define QSPI_CMD1_MODE_MASK GENMASK(1,0)
  21. #define QSPI_CMD1_MODE_SHIFT 28
  22. #define QSPI_CMD1_CS_SEL_MASK GENMASK(1,0)
  23. #define QSPI_CMD1_CS_SEL_SHIFT 26
  24. #define QSPI_CMD1_CS_POL_INACTIVE0 BIT(22)
  25. #define QSPI_CMD1_CS_SW_HW BIT(21)
  26. #define QSPI_CMD1_CS_SW_VAL BIT(20)
  27. #define QSPI_CMD1_IDLE_SDA_MASK GENMASK(1,0)
  28. #define QSPI_CMD1_IDLE_SDA_SHIFT 18
  29. #define QSPI_CMD1_BIDIR BIT(17)
  30. #define QSPI_CMD1_LSBI_FE BIT(16)
  31. #define QSPI_CMD1_LSBY_FE BIT(15)
  32. #define QSPI_CMD1_BOTH_EN_BIT BIT(14)
  33. #define QSPI_CMD1_BOTH_EN_BYTE BIT(13)
  34. #define QSPI_CMD1_RX_EN BIT(12)
  35. #define QSPI_CMD1_TX_EN BIT(11)
  36. #define QSPI_CMD1_PACKED BIT(5)
  37. #define QSPI_CMD1_BITLEN_MASK GENMASK(4,0)
  38. #define QSPI_CMD1_BITLEN_SHIFT 0
  39. /* COMMAND2 */
  40. #define QSPI_CMD2_TX_CLK_TAP_DELAY BIT(6)
  41. #define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11,6)
  42. #define QSPI_CMD2_RX_CLK_TAP_DELAY BIT(0)
  43. #define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5,0)
  44. /* TRANSFER STATUS */
  45. #define QSPI_XFER_STS_RDY BIT(30)
  46. /* FIFO STATUS */
  47. #define QSPI_FIFO_STS_CS_INACTIVE BIT(31)
  48. #define QSPI_FIFO_STS_FRAME_END BIT(30)
  49. #define QSPI_FIFO_STS_RX_FIFO_FLUSH BIT(15)
  50. #define QSPI_FIFO_STS_TX_FIFO_FLUSH BIT(14)
  51. #define QSPI_FIFO_STS_ERR BIT(8)
  52. #define QSPI_FIFO_STS_TX_FIFO_OVF BIT(7)
  53. #define QSPI_FIFO_STS_TX_FIFO_UNR BIT(6)
  54. #define QSPI_FIFO_STS_RX_FIFO_OVF BIT(5)
  55. #define QSPI_FIFO_STS_RX_FIFO_UNR BIT(4)
  56. #define QSPI_FIFO_STS_TX_FIFO_FULL BIT(3)
  57. #define QSPI_FIFO_STS_TX_FIFO_EMPTY BIT(2)
  58. #define QSPI_FIFO_STS_RX_FIFO_FULL BIT(1)
  59. #define QSPI_FIFO_STS_RX_FIFO_EMPTY BIT(0)
  60. #define QSPI_TIMEOUT 1000
  61. struct qspi_regs {
  62. u32 command1; /* 000:QSPI_COMMAND1 register */
  63. u32 command2; /* 004:QSPI_COMMAND2 register */
  64. u32 timing1; /* 008:QSPI_CS_TIM1 register */
  65. u32 timing2; /* 00c:QSPI_CS_TIM2 register */
  66. u32 xfer_status;/* 010:QSPI_TRANS_STATUS register */
  67. u32 fifo_status;/* 014:QSPI_FIFO_STATUS register */
  68. u32 tx_data; /* 018:QSPI_TX_DATA register */
  69. u32 rx_data; /* 01c:QSPI_RX_DATA register */
  70. u32 dma_ctl; /* 020:QSPI_DMA_CTL register */
  71. u32 dma_blk; /* 024:QSPI_DMA_BLK register */
  72. u32 rsvd[56]; /* 028-107 reserved */
  73. u32 tx_fifo; /* 108:QSPI_FIFO1 register */
  74. u32 rsvd2[31]; /* 10c-187 reserved */
  75. u32 rx_fifo; /* 188:QSPI_FIFO2 register */
  76. u32 spare_ctl; /* 18c:QSPI_SPARE_CTRL register */
  77. };
  78. struct tegra210_qspi_priv {
  79. struct qspi_regs *regs;
  80. unsigned int freq;
  81. unsigned int mode;
  82. int periph_id;
  83. int valid;
  84. int last_transaction_us;
  85. };
  86. static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus)
  87. {
  88. struct tegra_spi_platdata *plat = bus->platdata;
  89. const void *blob = gd->fdt_blob;
  90. int node = dev_of_offset(bus);
  91. plat->base = devfdt_get_addr(bus);
  92. plat->periph_id = clock_decode_periph_id(bus);
  93. if (plat->periph_id == PERIPH_ID_NONE) {
  94. debug("%s: could not decode periph id %d\n", __func__,
  95. plat->periph_id);
  96. return -FDT_ERR_NOTFOUND;
  97. }
  98. /* Use 500KHz as a suitable default */
  99. plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
  100. 500000);
  101. plat->deactivate_delay_us = fdtdec_get_int(blob, node,
  102. "spi-deactivate-delay", 0);
  103. debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
  104. __func__, plat->base, plat->periph_id, plat->frequency,
  105. plat->deactivate_delay_us);
  106. return 0;
  107. }
  108. static int tegra210_qspi_probe(struct udevice *bus)
  109. {
  110. struct tegra_spi_platdata *plat = dev_get_platdata(bus);
  111. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  112. priv->regs = (struct qspi_regs *)plat->base;
  113. priv->last_transaction_us = timer_get_us();
  114. priv->freq = plat->frequency;
  115. priv->periph_id = plat->periph_id;
  116. /* Change SPI clock to correct frequency, PLLP_OUT0 source */
  117. clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
  118. return 0;
  119. }
  120. static int tegra210_qspi_claim_bus(struct udevice *bus)
  121. {
  122. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  123. struct qspi_regs *regs = priv->regs;
  124. /* Change SPI clock to correct frequency, PLLP_OUT0 source */
  125. clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
  126. debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));
  127. /* Set master mode and sw controlled CS */
  128. setbits_le32(&regs->command1, QSPI_CMD1_M_S | QSPI_CMD1_CS_SW_HW |
  129. (priv->mode << QSPI_CMD1_MODE_SHIFT));
  130. debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));
  131. return 0;
  132. }
  133. /**
  134. * Activate the CS by driving it LOW
  135. *
  136. * @param slave Pointer to spi_slave to which controller has to
  137. * communicate with
  138. */
  139. static void spi_cs_activate(struct udevice *dev)
  140. {
  141. struct udevice *bus = dev->parent;
  142. struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
  143. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  144. /* If it's too soon to do another transaction, wait */
  145. if (pdata->deactivate_delay_us &&
  146. priv->last_transaction_us) {
  147. ulong delay_us; /* The delay completed so far */
  148. delay_us = timer_get_us() - priv->last_transaction_us;
  149. if (delay_us < pdata->deactivate_delay_us)
  150. udelay(pdata->deactivate_delay_us - delay_us);
  151. }
  152. clrbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL);
  153. }
  154. /**
  155. * Deactivate the CS by driving it HIGH
  156. *
  157. * @param slave Pointer to spi_slave to which controller has to
  158. * communicate with
  159. */
  160. static void spi_cs_deactivate(struct udevice *dev)
  161. {
  162. struct udevice *bus = dev->parent;
  163. struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
  164. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  165. setbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL);
  166. /* Remember time of this transaction so we can honour the bus delay */
  167. if (pdata->deactivate_delay_us)
  168. priv->last_transaction_us = timer_get_us();
  169. debug("Deactivate CS, bus '%s'\n", bus->name);
  170. }
  171. static int tegra210_qspi_xfer(struct udevice *dev, unsigned int bitlen,
  172. const void *data_out, void *data_in,
  173. unsigned long flags)
  174. {
  175. struct udevice *bus = dev->parent;
  176. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  177. struct qspi_regs *regs = priv->regs;
  178. u32 reg, tmpdout, tmpdin = 0;
  179. const u8 *dout = data_out;
  180. u8 *din = data_in;
  181. int num_bytes, tm, ret;
  182. debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
  183. __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
  184. if (bitlen % 8)
  185. return -1;
  186. num_bytes = bitlen / 8;
  187. ret = 0;
  188. /* clear all error status bits */
  189. reg = readl(&regs->fifo_status);
  190. writel(reg, &regs->fifo_status);
  191. /* flush RX/TX FIFOs */
  192. setbits_le32(&regs->fifo_status,
  193. (QSPI_FIFO_STS_RX_FIFO_FLUSH |
  194. QSPI_FIFO_STS_TX_FIFO_FLUSH));
  195. tm = QSPI_TIMEOUT;
  196. while ((tm && readl(&regs->fifo_status) &
  197. (QSPI_FIFO_STS_RX_FIFO_FLUSH |
  198. QSPI_FIFO_STS_TX_FIFO_FLUSH))) {
  199. tm--;
  200. udelay(1);
  201. }
  202. if (!tm) {
  203. printf("%s: timeout during QSPI FIFO flush!\n",
  204. __func__);
  205. return -1;
  206. }
  207. /*
  208. * Notes:
  209. * 1. don't set LSBY_FE, so no need to swap bytes from/to TX/RX FIFOs;
  210. * 2. don't set RX_EN and TX_EN yet.
  211. * (SW needs to make sure that while programming the blk_size,
  212. * tx_en and rx_en bits must be zero)
  213. * [TODO] I (Yen Lin) have problems when both RX/TX EN bits are set
  214. * i.e., both dout and din are not NULL.
  215. */
  216. clrsetbits_le32(&regs->command1,
  217. (QSPI_CMD1_LSBI_FE | QSPI_CMD1_LSBY_FE |
  218. QSPI_CMD1_RX_EN | QSPI_CMD1_TX_EN),
  219. (spi_chip_select(dev) << QSPI_CMD1_CS_SEL_SHIFT));
  220. /* set xfer size to 1 block (32 bits) */
  221. writel(0, &regs->dma_blk);
  222. if (flags & SPI_XFER_BEGIN)
  223. spi_cs_activate(dev);
  224. /* handle data in 32-bit chunks */
  225. while (num_bytes > 0) {
  226. int bytes;
  227. tmpdout = 0;
  228. bytes = (num_bytes > 4) ? 4 : num_bytes;
  229. if (dout != NULL) {
  230. memcpy((void *)&tmpdout, (void *)dout, bytes);
  231. dout += bytes;
  232. num_bytes -= bytes;
  233. writel(tmpdout, &regs->tx_fifo);
  234. setbits_le32(&regs->command1, QSPI_CMD1_TX_EN);
  235. }
  236. if (din != NULL)
  237. setbits_le32(&regs->command1, QSPI_CMD1_RX_EN);
  238. /* clear ready bit */
  239. setbits_le32(&regs->xfer_status, QSPI_XFER_STS_RDY);
  240. clrsetbits_le32(&regs->command1,
  241. QSPI_CMD1_BITLEN_MASK << QSPI_CMD1_BITLEN_SHIFT,
  242. (bytes * 8 - 1) << QSPI_CMD1_BITLEN_SHIFT);
  243. /* Need to stabilize other reg bits before GO bit set.
  244. * As per the TRM:
  245. * "For successful operation at various freq combinations,
  246. * a minimum of 4-5 spi_clk cycle delay might be required
  247. * before enabling the PIO or DMA bits. The worst case delay
  248. * calculation can be done considering slowest qspi_clk as
  249. * 1MHz. Based on that 1us delay should be enough before
  250. * enabling PIO or DMA." Padded another 1us for safety.
  251. */
  252. udelay(2);
  253. setbits_le32(&regs->command1, QSPI_CMD1_GO);
  254. udelay(1);
  255. /*
  256. * Wait for SPI transmit FIFO to empty, or to time out.
  257. * The RX FIFO status will be read and cleared last
  258. */
  259. for (tm = 0; tm < QSPI_TIMEOUT; ++tm) {
  260. u32 fifo_status, xfer_status;
  261. xfer_status = readl(&regs->xfer_status);
  262. if (!(xfer_status & QSPI_XFER_STS_RDY))
  263. continue;
  264. fifo_status = readl(&regs->fifo_status);
  265. if (fifo_status & QSPI_FIFO_STS_ERR) {
  266. debug("%s: got a fifo error: ", __func__);
  267. if (fifo_status & QSPI_FIFO_STS_TX_FIFO_OVF)
  268. debug("tx FIFO overflow ");
  269. if (fifo_status & QSPI_FIFO_STS_TX_FIFO_UNR)
  270. debug("tx FIFO underrun ");
  271. if (fifo_status & QSPI_FIFO_STS_RX_FIFO_OVF)
  272. debug("rx FIFO overflow ");
  273. if (fifo_status & QSPI_FIFO_STS_RX_FIFO_UNR)
  274. debug("rx FIFO underrun ");
  275. if (fifo_status & QSPI_FIFO_STS_TX_FIFO_FULL)
  276. debug("tx FIFO full ");
  277. if (fifo_status & QSPI_FIFO_STS_TX_FIFO_EMPTY)
  278. debug("tx FIFO empty ");
  279. if (fifo_status & QSPI_FIFO_STS_RX_FIFO_FULL)
  280. debug("rx FIFO full ");
  281. if (fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)
  282. debug("rx FIFO empty ");
  283. debug("\n");
  284. break;
  285. }
  286. if (!(fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)) {
  287. tmpdin = readl(&regs->rx_fifo);
  288. if (din != NULL) {
  289. memcpy(din, &tmpdin, bytes);
  290. din += bytes;
  291. num_bytes -= bytes;
  292. }
  293. }
  294. break;
  295. }
  296. if (tm >= QSPI_TIMEOUT)
  297. ret = tm;
  298. /* clear ACK RDY, etc. bits */
  299. writel(readl(&regs->fifo_status), &regs->fifo_status);
  300. }
  301. if (flags & SPI_XFER_END)
  302. spi_cs_deactivate(dev);
  303. debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
  304. __func__, tmpdin, readl(&regs->fifo_status));
  305. if (ret) {
  306. printf("%s: timeout during SPI transfer, tm %d\n",
  307. __func__, ret);
  308. return -1;
  309. }
  310. return ret;
  311. }
  312. static int tegra210_qspi_set_speed(struct udevice *bus, uint speed)
  313. {
  314. struct tegra_spi_platdata *plat = bus->platdata;
  315. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  316. if (speed > plat->frequency)
  317. speed = plat->frequency;
  318. priv->freq = speed;
  319. debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
  320. return 0;
  321. }
  322. static int tegra210_qspi_set_mode(struct udevice *bus, uint mode)
  323. {
  324. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  325. priv->mode = mode;
  326. debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
  327. return 0;
  328. }
  329. static const struct dm_spi_ops tegra210_qspi_ops = {
  330. .claim_bus = tegra210_qspi_claim_bus,
  331. .xfer = tegra210_qspi_xfer,
  332. .set_speed = tegra210_qspi_set_speed,
  333. .set_mode = tegra210_qspi_set_mode,
  334. /*
  335. * cs_info is not needed, since we require all chip selects to be
  336. * in the device tree explicitly
  337. */
  338. };
  339. static const struct udevice_id tegra210_qspi_ids[] = {
  340. { .compatible = "nvidia,tegra210-qspi" },
  341. { }
  342. };
  343. U_BOOT_DRIVER(tegra210_qspi) = {
  344. .name = "tegra210-qspi",
  345. .id = UCLASS_SPI,
  346. .of_match = tegra210_qspi_ids,
  347. .ops = &tegra210_qspi_ops,
  348. .ofdata_to_platdata = tegra210_qspi_ofdata_to_platdata,
  349. .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
  350. .priv_auto_alloc_size = sizeof(struct tegra210_qspi_priv),
  351. .per_child_auto_alloc_size = sizeof(struct spi_slave),
  352. .probe = tegra210_qspi_probe,
  353. };