tegra20_slink.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * NVIDIA Tegra SPI-SLINK controller
  4. *
  5. * Copyright (c) 2010-2013 NVIDIA Corporation
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <time.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch-tegra/clk_rst.h>
  13. #include <spi.h>
  14. #include <fdtdec.h>
  15. #include "tegra_spi.h"
  16. DECLARE_GLOBAL_DATA_PTR;
  17. /* COMMAND */
  18. #define SLINK_CMD_ENB BIT(31)
  19. #define SLINK_CMD_GO BIT(30)
  20. #define SLINK_CMD_M_S BIT(28)
  21. #define SLINK_CMD_IDLE_SCLK_DRIVE_LOW (0 << 24)
  22. #define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH BIT(24)
  23. #define SLINK_CMD_IDLE_SCLK_PULL_LOW (2 << 24)
  24. #define SLINK_CMD_IDLE_SCLK_PULL_HIGH (3 << 24)
  25. #define SLINK_CMD_IDLE_SCLK_MASK (3 << 24)
  26. #define SLINK_CMD_CK_SDA BIT(21)
  27. #define SLINK_CMD_CS_POL BIT(13)
  28. #define SLINK_CMD_CS_VAL BIT(12)
  29. #define SLINK_CMD_CS_SOFT BIT(11)
  30. #define SLINK_CMD_BIT_LENGTH BIT(4)
  31. #define SLINK_CMD_BIT_LENGTH_MASK GENMASK(4, 0)
  32. /* COMMAND2 */
  33. #define SLINK_CMD2_TXEN BIT(30)
  34. #define SLINK_CMD2_RXEN BIT(31)
  35. #define SLINK_CMD2_SS_EN BIT(18)
  36. #define SLINK_CMD2_SS_EN_SHIFT 18
  37. #define SLINK_CMD2_SS_EN_MASK GENMASK(19, 18)
  38. #define SLINK_CMD2_CS_ACTIVE_BETWEEN BIT(17)
  39. /* STATUS */
  40. #define SLINK_STAT_BSY BIT(31)
  41. #define SLINK_STAT_RDY BIT(30)
  42. #define SLINK_STAT_ERR BIT(29)
  43. #define SLINK_STAT_RXF_FLUSH BIT(27)
  44. #define SLINK_STAT_TXF_FLUSH BIT(26)
  45. #define SLINK_STAT_RXF_OVF BIT(25)
  46. #define SLINK_STAT_TXF_UNR BIT(24)
  47. #define SLINK_STAT_RXF_EMPTY BIT(23)
  48. #define SLINK_STAT_RXF_FULL BIT(22)
  49. #define SLINK_STAT_TXF_EMPTY BIT(21)
  50. #define SLINK_STAT_TXF_FULL BIT(20)
  51. #define SLINK_STAT_TXF_OVF BIT(19)
  52. #define SLINK_STAT_RXF_UNR BIT(18)
  53. #define SLINK_STAT_CUR_BLKCNT BIT(15)
  54. /* STATUS2 */
  55. #define SLINK_STAT2_RXF_FULL_CNT BIT(16)
  56. #define SLINK_STAT2_TXF_FULL_CNT BIT(0)
  57. #define SPI_TIMEOUT 1000
  58. #define TEGRA_SPI_MAX_FREQ 52000000
  59. struct spi_regs {
  60. u32 command; /* SLINK_COMMAND_0 register */
  61. u32 command2; /* SLINK_COMMAND2_0 reg */
  62. u32 status; /* SLINK_STATUS_0 register */
  63. u32 reserved; /* Reserved offset 0C */
  64. u32 mas_data; /* SLINK_MAS_DATA_0 reg */
  65. u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */
  66. u32 dma_ctl; /* SLINK_DMA_CTL_0 register */
  67. u32 status2; /* SLINK_STATUS2_0 reg */
  68. u32 rsvd[56]; /* 0x20 to 0xFF reserved */
  69. u32 tx_fifo; /* SLINK_TX_FIFO_0 reg off 100h */
  70. u32 rsvd2[31]; /* 0x104 to 0x17F reserved */
  71. u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */
  72. };
  73. struct tegra30_spi_priv {
  74. struct spi_regs *regs;
  75. unsigned int freq;
  76. unsigned int mode;
  77. int periph_id;
  78. int valid;
  79. int last_transaction_us;
  80. };
  81. struct tegra_spi_slave {
  82. struct spi_slave slave;
  83. struct tegra30_spi_priv *ctrl;
  84. };
  85. static int tegra30_spi_ofdata_to_platdata(struct udevice *bus)
  86. {
  87. struct tegra_spi_platdata *plat = bus->platdata;
  88. const void *blob = gd->fdt_blob;
  89. int node = dev_of_offset(bus);
  90. plat->base = devfdt_get_addr(bus);
  91. plat->periph_id = clock_decode_periph_id(bus);
  92. if (plat->periph_id == PERIPH_ID_NONE) {
  93. debug("%s: could not decode periph id %d\n", __func__,
  94. plat->periph_id);
  95. return -FDT_ERR_NOTFOUND;
  96. }
  97. /* Use 500KHz as a suitable default */
  98. plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
  99. 500000);
  100. plat->deactivate_delay_us = fdtdec_get_int(blob, node,
  101. "spi-deactivate-delay", 0);
  102. debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
  103. __func__, plat->base, plat->periph_id, plat->frequency,
  104. plat->deactivate_delay_us);
  105. return 0;
  106. }
  107. static int tegra30_spi_probe(struct udevice *bus)
  108. {
  109. struct tegra_spi_platdata *plat = dev_get_platdata(bus);
  110. struct tegra30_spi_priv *priv = dev_get_priv(bus);
  111. priv->regs = (struct spi_regs *)plat->base;
  112. priv->last_transaction_us = timer_get_us();
  113. priv->freq = plat->frequency;
  114. priv->periph_id = plat->periph_id;
  115. /* Change SPI clock to correct frequency, PLLP_OUT0 source */
  116. clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
  117. priv->freq);
  118. return 0;
  119. }
  120. static int tegra30_spi_claim_bus(struct udevice *dev)
  121. {
  122. struct udevice *bus = dev->parent;
  123. struct tegra30_spi_priv *priv = dev_get_priv(bus);
  124. struct spi_regs *regs = priv->regs;
  125. u32 reg;
  126. /* Change SPI clock to correct frequency, PLLP_OUT0 source */
  127. clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
  128. priv->freq);
  129. /* Clear stale status here */
  130. reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \
  131. SLINK_STAT_RXF_UNR | SLINK_STAT_TXF_OVF;
  132. writel(reg, &regs->status);
  133. debug("%s: STATUS = %08x\n", __func__, readl(&regs->status));
  134. /* Set master mode and sw controlled CS */
  135. reg = readl(&regs->command);
  136. reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT;
  137. writel(reg, &regs->command);
  138. debug("%s: COMMAND = %08x\n", __func__, readl(&regs->command));
  139. return 0;
  140. }
  141. static void spi_cs_activate(struct udevice *dev)
  142. {
  143. struct udevice *bus = dev->parent;
  144. struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
  145. struct tegra30_spi_priv *priv = dev_get_priv(bus);
  146. /* If it's too soon to do another transaction, wait */
  147. if (pdata->deactivate_delay_us &&
  148. priv->last_transaction_us) {
  149. ulong delay_us; /* The delay completed so far */
  150. delay_us = timer_get_us() - priv->last_transaction_us;
  151. if (delay_us < pdata->deactivate_delay_us)
  152. udelay(pdata->deactivate_delay_us - delay_us);
  153. }
  154. /* CS is negated on Tegra, so drive a 1 to get a 0 */
  155. setbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
  156. }
  157. static void spi_cs_deactivate(struct udevice *dev)
  158. {
  159. struct udevice *bus = dev->parent;
  160. struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
  161. struct tegra30_spi_priv *priv = dev_get_priv(bus);
  162. /* CS is negated on Tegra, so drive a 0 to get a 1 */
  163. clrbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
  164. /* Remember time of this transaction so we can honour the bus delay */
  165. if (pdata->deactivate_delay_us)
  166. priv->last_transaction_us = timer_get_us();
  167. }
  168. static int tegra30_spi_xfer(struct udevice *dev, unsigned int bitlen,
  169. const void *data_out, void *data_in,
  170. unsigned long flags)
  171. {
  172. struct udevice *bus = dev->parent;
  173. struct tegra30_spi_priv *priv = dev_get_priv(bus);
  174. struct spi_regs *regs = priv->regs;
  175. u32 reg, tmpdout, tmpdin = 0;
  176. const u8 *dout = data_out;
  177. u8 *din = data_in;
  178. int num_bytes;
  179. int ret;
  180. debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
  181. __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
  182. if (bitlen % 8)
  183. return -1;
  184. num_bytes = bitlen / 8;
  185. ret = 0;
  186. reg = readl(&regs->status);
  187. writel(reg, &regs->status); /* Clear all SPI events via R/W */
  188. debug("%s entry: STATUS = %08x\n", __func__, reg);
  189. reg = readl(&regs->status2);
  190. writel(reg, &regs->status2); /* Clear all STATUS2 events via R/W */
  191. debug("%s entry: STATUS2 = %08x\n", __func__, reg);
  192. debug("%s entry: COMMAND = %08x\n", __func__, readl(&regs->command));
  193. clrsetbits_le32(&regs->command2, SLINK_CMD2_SS_EN_MASK,
  194. SLINK_CMD2_TXEN | SLINK_CMD2_RXEN |
  195. (spi_chip_select(dev) << SLINK_CMD2_SS_EN_SHIFT));
  196. debug("%s entry: COMMAND2 = %08x\n", __func__, readl(&regs->command2));
  197. if (flags & SPI_XFER_BEGIN)
  198. spi_cs_activate(dev);
  199. /* handle data in 32-bit chunks */
  200. while (num_bytes > 0) {
  201. int bytes;
  202. int is_read = 0;
  203. int tm, i;
  204. tmpdout = 0;
  205. bytes = (num_bytes > 4) ? 4 : num_bytes;
  206. if (dout != NULL) {
  207. for (i = 0; i < bytes; ++i)
  208. tmpdout = (tmpdout << 8) | dout[i];
  209. dout += bytes;
  210. }
  211. num_bytes -= bytes;
  212. clrsetbits_le32(&regs->command, SLINK_CMD_BIT_LENGTH_MASK,
  213. bytes * 8 - 1);
  214. writel(tmpdout, &regs->tx_fifo);
  215. setbits_le32(&regs->command, SLINK_CMD_GO);
  216. /*
  217. * Wait for SPI transmit FIFO to empty, or to time out.
  218. * The RX FIFO status will be read and cleared last
  219. */
  220. for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
  221. u32 status;
  222. status = readl(&regs->status);
  223. /* We can exit when we've had both RX and TX activity */
  224. if (is_read && (status & SLINK_STAT_TXF_EMPTY))
  225. break;
  226. if ((status & (SLINK_STAT_BSY | SLINK_STAT_RDY)) !=
  227. SLINK_STAT_RDY)
  228. tm++;
  229. else if (!(status & SLINK_STAT_RXF_EMPTY)) {
  230. tmpdin = readl(&regs->rx_fifo);
  231. is_read = 1;
  232. /* swap bytes read in */
  233. if (din != NULL) {
  234. for (i = bytes - 1; i >= 0; --i) {
  235. din[i] = tmpdin & 0xff;
  236. tmpdin >>= 8;
  237. }
  238. din += bytes;
  239. }
  240. }
  241. }
  242. if (tm >= SPI_TIMEOUT)
  243. ret = tm;
  244. /* clear ACK RDY, etc. bits */
  245. writel(readl(&regs->status), &regs->status);
  246. }
  247. if (flags & SPI_XFER_END)
  248. spi_cs_deactivate(dev);
  249. debug("%s: transfer ended. Value=%08x, status = %08x\n",
  250. __func__, tmpdin, readl(&regs->status));
  251. if (ret) {
  252. printf("%s: timeout during SPI transfer, tm %d\n",
  253. __func__, ret);
  254. return -1;
  255. }
  256. return 0;
  257. }
  258. static int tegra30_spi_set_speed(struct udevice *bus, uint speed)
  259. {
  260. struct tegra_spi_platdata *plat = bus->platdata;
  261. struct tegra30_spi_priv *priv = dev_get_priv(bus);
  262. if (speed > plat->frequency)
  263. speed = plat->frequency;
  264. priv->freq = speed;
  265. debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
  266. return 0;
  267. }
  268. static int tegra30_spi_set_mode(struct udevice *bus, uint mode)
  269. {
  270. struct tegra30_spi_priv *priv = dev_get_priv(bus);
  271. struct spi_regs *regs = priv->regs;
  272. u32 reg;
  273. reg = readl(&regs->command);
  274. /* Set CPOL and CPHA */
  275. reg &= ~(SLINK_CMD_IDLE_SCLK_MASK | SLINK_CMD_CK_SDA);
  276. if (mode & SPI_CPHA)
  277. reg |= SLINK_CMD_CK_SDA;
  278. if (mode & SPI_CPOL)
  279. reg |= SLINK_CMD_IDLE_SCLK_DRIVE_HIGH;
  280. else
  281. reg |= SLINK_CMD_IDLE_SCLK_DRIVE_LOW;
  282. writel(reg, &regs->command);
  283. priv->mode = mode;
  284. debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
  285. return 0;
  286. }
  287. static const struct dm_spi_ops tegra30_spi_ops = {
  288. .claim_bus = tegra30_spi_claim_bus,
  289. .xfer = tegra30_spi_xfer,
  290. .set_speed = tegra30_spi_set_speed,
  291. .set_mode = tegra30_spi_set_mode,
  292. /*
  293. * cs_info is not needed, since we require all chip selects to be
  294. * in the device tree explicitly
  295. */
  296. };
  297. static const struct udevice_id tegra30_spi_ids[] = {
  298. { .compatible = "nvidia,tegra20-slink" },
  299. { }
  300. };
  301. U_BOOT_DRIVER(tegra30_spi) = {
  302. .name = "tegra20_slink",
  303. .id = UCLASS_SPI,
  304. .of_match = tegra30_spi_ids,
  305. .ops = &tegra30_spi_ops,
  306. .ofdata_to_platdata = tegra30_spi_ofdata_to_platdata,
  307. .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
  308. .priv_auto_alloc_size = sizeof(struct tegra30_spi_priv),
  309. .probe = tegra30_spi_probe,
  310. };