tegra20_sflash.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2010-2013 NVIDIA Corporation
  4. * With help from the mpc8xxx SPI driver
  5. * With more help from omap3_spi SPI driver
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <time.h>
  11. #include <asm/io.h>
  12. #include <asm/gpio.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/pinmux.h>
  15. #include <asm/arch-tegra/clk_rst.h>
  16. #include <spi.h>
  17. #include <fdtdec.h>
  18. #include "tegra_spi.h"
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #define SPI_CMD_GO BIT(30)
  21. #define SPI_CMD_ACTIVE_SCLK_SHIFT 26
  22. #define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
  23. #define SPI_CMD_CK_SDA BIT(21)
  24. #define SPI_CMD_ACTIVE_SDA_SHIFT 18
  25. #define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
  26. #define SPI_CMD_CS_POL BIT(16)
  27. #define SPI_CMD_TXEN BIT(15)
  28. #define SPI_CMD_RXEN BIT(14)
  29. #define SPI_CMD_CS_VAL BIT(13)
  30. #define SPI_CMD_CS_SOFT BIT(12)
  31. #define SPI_CMD_CS_DELAY BIT(9)
  32. #define SPI_CMD_CS3_EN BIT(8)
  33. #define SPI_CMD_CS2_EN BIT(7)
  34. #define SPI_CMD_CS1_EN BIT(6)
  35. #define SPI_CMD_CS0_EN BIT(5)
  36. #define SPI_CMD_BIT_LENGTH BIT(4)
  37. #define SPI_CMD_BIT_LENGTH_MASK GENMASK(4, 0)
  38. #define SPI_STAT_BSY BIT(31)
  39. #define SPI_STAT_RDY BIT(30)
  40. #define SPI_STAT_RXF_FLUSH BIT(29)
  41. #define SPI_STAT_TXF_FLUSH BIT(28)
  42. #define SPI_STAT_RXF_UNR BIT(27)
  43. #define SPI_STAT_TXF_OVF BIT(26)
  44. #define SPI_STAT_RXF_EMPTY BIT(25)
  45. #define SPI_STAT_RXF_FULL BIT(24)
  46. #define SPI_STAT_TXF_EMPTY BIT(23)
  47. #define SPI_STAT_TXF_FULL BIT(22)
  48. #define SPI_STAT_SEL_TXRX_N BIT(16)
  49. #define SPI_STAT_CUR_BLKCNT BIT(15)
  50. #define SPI_TIMEOUT 1000
  51. #define TEGRA_SPI_MAX_FREQ 52000000
  52. struct spi_regs {
  53. u32 command; /* SPI_COMMAND_0 register */
  54. u32 status; /* SPI_STATUS_0 register */
  55. u32 rx_cmp; /* SPI_RX_CMP_0 register */
  56. u32 dma_ctl; /* SPI_DMA_CTL_0 register */
  57. u32 tx_fifo; /* SPI_TX_FIFO_0 register */
  58. u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */
  59. u32 rx_fifo; /* SPI_RX_FIFO_0 register */
  60. };
  61. struct tegra20_sflash_priv {
  62. struct spi_regs *regs;
  63. unsigned int freq;
  64. unsigned int mode;
  65. int periph_id;
  66. int valid;
  67. int last_transaction_us;
  68. };
  69. int tegra20_sflash_cs_info(struct udevice *bus, unsigned int cs,
  70. struct spi_cs_info *info)
  71. {
  72. /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
  73. if (cs != 0)
  74. return -EINVAL;
  75. else
  76. return 0;
  77. }
  78. static int tegra20_sflash_ofdata_to_platdata(struct udevice *bus)
  79. {
  80. struct tegra_spi_platdata *plat = bus->platdata;
  81. const void *blob = gd->fdt_blob;
  82. int node = dev_of_offset(bus);
  83. plat->base = devfdt_get_addr(bus);
  84. plat->periph_id = clock_decode_periph_id(bus);
  85. if (plat->periph_id == PERIPH_ID_NONE) {
  86. debug("%s: could not decode periph id %d\n", __func__,
  87. plat->periph_id);
  88. return -FDT_ERR_NOTFOUND;
  89. }
  90. /* Use 500KHz as a suitable default */
  91. plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
  92. 500000);
  93. plat->deactivate_delay_us = fdtdec_get_int(blob, node,
  94. "spi-deactivate-delay", 0);
  95. debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
  96. __func__, plat->base, plat->periph_id, plat->frequency,
  97. plat->deactivate_delay_us);
  98. return 0;
  99. }
  100. static int tegra20_sflash_probe(struct udevice *bus)
  101. {
  102. struct tegra_spi_platdata *plat = dev_get_platdata(bus);
  103. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  104. priv->regs = (struct spi_regs *)plat->base;
  105. priv->last_transaction_us = timer_get_us();
  106. priv->freq = plat->frequency;
  107. priv->periph_id = plat->periph_id;
  108. /* Change SPI clock to correct frequency, PLLP_OUT0 source */
  109. clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
  110. priv->freq);
  111. return 0;
  112. }
  113. static int tegra20_sflash_claim_bus(struct udevice *dev)
  114. {
  115. struct udevice *bus = dev->parent;
  116. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  117. struct spi_regs *regs = priv->regs;
  118. u32 reg;
  119. /* Change SPI clock to correct frequency, PLLP_OUT0 source */
  120. clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
  121. priv->freq);
  122. /* Clear stale status here */
  123. reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
  124. SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
  125. writel(reg, &regs->status);
  126. debug("%s: STATUS = %08x\n", __func__, readl(&regs->status));
  127. /*
  128. * Use sw-controlled CS, so we can clock in data after ReadID, etc.
  129. */
  130. reg = (priv->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
  131. if (priv->mode & 2)
  132. reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
  133. clrsetbits_le32(&regs->command, SPI_CMD_ACTIVE_SCLK_MASK |
  134. SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
  135. debug("%s: COMMAND = %08x\n", __func__, readl(&regs->command));
  136. /*
  137. * SPI pins on Tegra20 are muxed - change pinmux later due to UART
  138. * issue.
  139. */
  140. pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
  141. pinmux_tristate_disable(PMUX_PINGRP_LSPI);
  142. pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
  143. return 0;
  144. }
  145. static void spi_cs_activate(struct udevice *dev)
  146. {
  147. struct udevice *bus = dev->parent;
  148. struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
  149. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  150. /* If it's too soon to do another transaction, wait */
  151. if (pdata->deactivate_delay_us &&
  152. priv->last_transaction_us) {
  153. ulong delay_us; /* The delay completed so far */
  154. delay_us = timer_get_us() - priv->last_transaction_us;
  155. if (delay_us < pdata->deactivate_delay_us)
  156. udelay(pdata->deactivate_delay_us - delay_us);
  157. }
  158. /* CS is negated on Tegra, so drive a 1 to get a 0 */
  159. setbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
  160. }
  161. static void spi_cs_deactivate(struct udevice *dev)
  162. {
  163. struct udevice *bus = dev->parent;
  164. struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
  165. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  166. /* CS is negated on Tegra, so drive a 0 to get a 1 */
  167. clrbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
  168. /* Remember time of this transaction so we can honour the bus delay */
  169. if (pdata->deactivate_delay_us)
  170. priv->last_transaction_us = timer_get_us();
  171. }
  172. static int tegra20_sflash_xfer(struct udevice *dev, unsigned int bitlen,
  173. const void *data_out, void *data_in,
  174. unsigned long flags)
  175. {
  176. struct udevice *bus = dev->parent;
  177. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  178. struct spi_regs *regs = priv->regs;
  179. u32 reg, tmpdout, tmpdin = 0;
  180. const u8 *dout = data_out;
  181. u8 *din = data_in;
  182. int num_bytes;
  183. int ret;
  184. debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
  185. __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
  186. if (bitlen % 8)
  187. return -1;
  188. num_bytes = bitlen / 8;
  189. ret = 0;
  190. reg = readl(&regs->status);
  191. writel(reg, &regs->status); /* Clear all SPI events via R/W */
  192. debug("spi_xfer entry: STATUS = %08x\n", reg);
  193. reg = readl(&regs->command);
  194. reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
  195. writel(reg, &regs->command);
  196. debug("spi_xfer: COMMAND = %08x\n", readl(&regs->command));
  197. if (flags & SPI_XFER_BEGIN)
  198. spi_cs_activate(dev);
  199. /* handle data in 32-bit chunks */
  200. while (num_bytes > 0) {
  201. int bytes;
  202. int is_read = 0;
  203. int tm, i;
  204. tmpdout = 0;
  205. bytes = (num_bytes > 4) ? 4 : num_bytes;
  206. if (dout != NULL) {
  207. for (i = 0; i < bytes; ++i)
  208. tmpdout = (tmpdout << 8) | dout[i];
  209. }
  210. num_bytes -= bytes;
  211. if (dout)
  212. dout += bytes;
  213. clrsetbits_le32(&regs->command, SPI_CMD_BIT_LENGTH_MASK,
  214. bytes * 8 - 1);
  215. writel(tmpdout, &regs->tx_fifo);
  216. setbits_le32(&regs->command, SPI_CMD_GO);
  217. /*
  218. * Wait for SPI transmit FIFO to empty, or to time out.
  219. * The RX FIFO status will be read and cleared last
  220. */
  221. for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
  222. u32 status;
  223. status = readl(&regs->status);
  224. /* We can exit when we've had both RX and TX activity */
  225. if (is_read && (status & SPI_STAT_TXF_EMPTY))
  226. break;
  227. if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
  228. SPI_STAT_RDY)
  229. tm++;
  230. else if (!(status & SPI_STAT_RXF_EMPTY)) {
  231. tmpdin = readl(&regs->rx_fifo);
  232. is_read = 1;
  233. /* swap bytes read in */
  234. if (din != NULL) {
  235. for (i = bytes - 1; i >= 0; --i) {
  236. din[i] = tmpdin & 0xff;
  237. tmpdin >>= 8;
  238. }
  239. din += bytes;
  240. }
  241. }
  242. }
  243. if (tm >= SPI_TIMEOUT)
  244. ret = tm;
  245. /* clear ACK RDY, etc. bits */
  246. writel(readl(&regs->status), &regs->status);
  247. }
  248. if (flags & SPI_XFER_END)
  249. spi_cs_deactivate(dev);
  250. debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
  251. tmpdin, readl(&regs->status));
  252. if (ret) {
  253. printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);
  254. return -1;
  255. }
  256. return 0;
  257. }
  258. static int tegra20_sflash_set_speed(struct udevice *bus, uint speed)
  259. {
  260. struct tegra_spi_platdata *plat = bus->platdata;
  261. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  262. if (speed > plat->frequency)
  263. speed = plat->frequency;
  264. priv->freq = speed;
  265. debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
  266. return 0;
  267. }
  268. static int tegra20_sflash_set_mode(struct udevice *bus, uint mode)
  269. {
  270. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  271. priv->mode = mode;
  272. debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
  273. return 0;
  274. }
  275. static const struct dm_spi_ops tegra20_sflash_ops = {
  276. .claim_bus = tegra20_sflash_claim_bus,
  277. .xfer = tegra20_sflash_xfer,
  278. .set_speed = tegra20_sflash_set_speed,
  279. .set_mode = tegra20_sflash_set_mode,
  280. .cs_info = tegra20_sflash_cs_info,
  281. };
  282. static const struct udevice_id tegra20_sflash_ids[] = {
  283. { .compatible = "nvidia,tegra20-sflash" },
  284. { }
  285. };
  286. U_BOOT_DRIVER(tegra20_sflash) = {
  287. .name = "tegra20_sflash",
  288. .id = UCLASS_SPI,
  289. .of_match = tegra20_sflash_ids,
  290. .ops = &tegra20_sflash_ops,
  291. .ofdata_to_platdata = tegra20_sflash_ofdata_to_platdata,
  292. .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
  293. .priv_auto_alloc_size = sizeof(struct tegra20_sflash_priv),
  294. .probe = tegra20_sflash_probe,
  295. };