rk_spi.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * spi driver for rockchip
  4. *
  5. * (C) 2019 Theobroma Systems Design und Consulting GmbH
  6. *
  7. * (C) Copyright 2015 Google, Inc
  8. *
  9. * (C) Copyright 2008-2013 Rockchip Electronics
  10. * Peter, Software Engineering, <superpeter.cai@gmail.com>.
  11. */
  12. #include <common.h>
  13. #include <clk.h>
  14. #include <dm.h>
  15. #include <dt-structs.h>
  16. #include <errno.h>
  17. #include <spi.h>
  18. #include <time.h>
  19. #include <linux/errno.h>
  20. #include <asm/io.h>
  21. #include <asm/arch-rockchip/clock.h>
  22. #include <asm/arch-rockchip/periph.h>
  23. #include <dm/pinctrl.h>
  24. #include "rk_spi.h"
  25. /* Change to 1 to output registers at the start of each transaction */
  26. #define DEBUG_RK_SPI 0
  27. struct rockchip_spi_params {
  28. /* RXFIFO overruns and TXFIFO underruns stop the master clock */
  29. bool master_manages_fifo;
  30. };
  31. struct rockchip_spi_platdata {
  32. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  33. struct dtd_rockchip_rk3288_spi of_plat;
  34. #endif
  35. s32 frequency; /* Default clock frequency, -1 for none */
  36. fdt_addr_t base;
  37. uint deactivate_delay_us; /* Delay to wait after deactivate */
  38. uint activate_delay_us; /* Delay to wait after activate */
  39. };
  40. struct rockchip_spi_priv {
  41. struct rockchip_spi *regs;
  42. struct clk clk;
  43. unsigned int max_freq;
  44. unsigned int mode;
  45. ulong last_transaction_us; /* Time of last transaction end */
  46. unsigned int speed_hz;
  47. unsigned int last_speed_hz;
  48. uint input_rate;
  49. };
  50. #define SPI_FIFO_DEPTH 32
  51. static void rkspi_dump_regs(struct rockchip_spi *regs)
  52. {
  53. debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
  54. debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
  55. debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
  56. debug("ser: \t\t0x%08x\n", readl(&regs->ser));
  57. debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
  58. debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
  59. debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
  60. debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
  61. debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
  62. debug("sr: \t\t0x%08x\n", readl(&regs->sr));
  63. debug("imr: \t\t0x%08x\n", readl(&regs->imr));
  64. debug("isr: \t\t0x%08x\n", readl(&regs->isr));
  65. debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
  66. debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
  67. debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
  68. }
  69. static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
  70. {
  71. writel(enable ? 1 : 0, &regs->enr);
  72. }
  73. static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
  74. {
  75. /*
  76. * We should try not to exceed the speed requested by the caller:
  77. * when selecting a divider, we need to make sure we round up.
  78. */
  79. uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
  80. /* The baudrate register (BAUDR) is defined as a 32bit register where
  81. * the upper 16bit are reserved and having 'Fsclk_out' in the lower
  82. * 16bits with 'Fsclk_out' defined as follows:
  83. *
  84. * Fsclk_out = Fspi_clk/ SCKDV
  85. * Where SCKDV is any even value between 2 and 65534.
  86. */
  87. if (clk_div > 0xfffe) {
  88. clk_div = 0xfffe;
  89. debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n",
  90. __func__, speed, priv->input_rate / clk_div);
  91. }
  92. /* Round up to the next even 16bit number */
  93. clk_div = (clk_div + 1) & 0xfffe;
  94. debug("spi speed %u, div %u\n", speed, clk_div);
  95. clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
  96. priv->last_speed_hz = speed;
  97. }
  98. static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
  99. {
  100. unsigned long start;
  101. start = get_timer(0);
  102. while (readl(&regs->sr) & SR_BUSY) {
  103. if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
  104. debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
  105. return -ETIMEDOUT;
  106. }
  107. }
  108. return 0;
  109. }
  110. static void spi_cs_activate(struct udevice *dev, uint cs)
  111. {
  112. struct udevice *bus = dev->parent;
  113. struct rockchip_spi_platdata *plat = bus->platdata;
  114. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  115. struct rockchip_spi *regs = priv->regs;
  116. /* If it's too soon to do another transaction, wait */
  117. if (plat->deactivate_delay_us && priv->last_transaction_us) {
  118. ulong delay_us; /* The delay completed so far */
  119. delay_us = timer_get_us() - priv->last_transaction_us;
  120. if (delay_us < plat->deactivate_delay_us) {
  121. ulong additional_delay_us =
  122. plat->deactivate_delay_us - delay_us;
  123. debug("%s: delaying by %ld us\n",
  124. __func__, additional_delay_us);
  125. udelay(additional_delay_us);
  126. }
  127. }
  128. debug("activate cs%u\n", cs);
  129. writel(1 << cs, &regs->ser);
  130. if (plat->activate_delay_us)
  131. udelay(plat->activate_delay_us);
  132. }
  133. static void spi_cs_deactivate(struct udevice *dev, uint cs)
  134. {
  135. struct udevice *bus = dev->parent;
  136. struct rockchip_spi_platdata *plat = bus->platdata;
  137. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  138. struct rockchip_spi *regs = priv->regs;
  139. debug("deactivate cs%u\n", cs);
  140. writel(0, &regs->ser);
  141. /* Remember time of this transaction so we can honour the bus delay */
  142. if (plat->deactivate_delay_us)
  143. priv->last_transaction_us = timer_get_us();
  144. }
  145. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  146. static int conv_of_platdata(struct udevice *dev)
  147. {
  148. struct rockchip_spi_platdata *plat = dev->platdata;
  149. struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
  150. struct rockchip_spi_priv *priv = dev_get_priv(dev);
  151. int ret;
  152. plat->base = dtplat->reg[0];
  153. plat->frequency = 20000000;
  154. ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
  155. if (ret < 0)
  156. return ret;
  157. dev->req_seq = 0;
  158. return 0;
  159. }
  160. #endif
  161. static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
  162. {
  163. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  164. struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
  165. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  166. int ret;
  167. plat->base = dev_read_addr(bus);
  168. ret = clk_get_by_index(bus, 0, &priv->clk);
  169. if (ret < 0) {
  170. debug("%s: Could not get clock for %s: %d\n", __func__,
  171. bus->name, ret);
  172. return ret;
  173. }
  174. plat->frequency =
  175. dev_read_u32_default(bus, "spi-max-frequency", 50000000);
  176. plat->deactivate_delay_us =
  177. dev_read_u32_default(bus, "spi-deactivate-delay", 0);
  178. plat->activate_delay_us =
  179. dev_read_u32_default(bus, "spi-activate-delay", 0);
  180. debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
  181. __func__, (uint)plat->base, plat->frequency,
  182. plat->deactivate_delay_us);
  183. #endif
  184. return 0;
  185. }
  186. static int rockchip_spi_calc_modclk(ulong max_freq)
  187. {
  188. /*
  189. * While this is not strictly correct for the RK3368, as the
  190. * GPLL will be 576MHz, things will still work, as the
  191. * clk_set_rate(...) implementation in our clock-driver will
  192. * chose the next closest rate not exceeding what we request
  193. * based on the output of this function.
  194. */
  195. unsigned div;
  196. const unsigned long gpll_hz = 594000000UL;
  197. /*
  198. * We need to find an input clock that provides at least twice
  199. * the maximum frequency and can be generated from the assumed
  200. * speed of GPLL (594MHz) using an integer divider.
  201. *
  202. * To give us more achievable bitrates at higher speeds (these
  203. * are generated by dividing by an even 16-bit integer from
  204. * this frequency), we try to have an input frequency of at
  205. * least 4x our max_freq.
  206. */
  207. div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
  208. return gpll_hz / div;
  209. }
  210. static int rockchip_spi_probe(struct udevice *bus)
  211. {
  212. struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
  213. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  214. int ret;
  215. debug("%s: probe\n", __func__);
  216. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  217. ret = conv_of_platdata(bus);
  218. if (ret)
  219. return ret;
  220. #endif
  221. priv->regs = (struct rockchip_spi *)plat->base;
  222. priv->last_transaction_us = timer_get_us();
  223. priv->max_freq = plat->frequency;
  224. /* Clamp the value from the DTS against any hardware limits */
  225. if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
  226. priv->max_freq = ROCKCHIP_SPI_MAX_RATE;
  227. /* Find a module-input clock that fits with the max_freq setting */
  228. ret = clk_set_rate(&priv->clk,
  229. rockchip_spi_calc_modclk(priv->max_freq));
  230. if (ret < 0) {
  231. debug("%s: Failed to set clock: %d\n", __func__, ret);
  232. return ret;
  233. }
  234. priv->input_rate = ret;
  235. debug("%s: rate = %u\n", __func__, priv->input_rate);
  236. return 0;
  237. }
  238. static int rockchip_spi_claim_bus(struct udevice *dev)
  239. {
  240. struct udevice *bus = dev->parent;
  241. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  242. struct rockchip_spi *regs = priv->regs;
  243. uint ctrlr0;
  244. /* Disable the SPI hardware */
  245. rkspi_enable_chip(regs, false);
  246. if (priv->speed_hz != priv->last_speed_hz)
  247. rkspi_set_clk(priv, priv->speed_hz);
  248. /* Operation Mode */
  249. ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
  250. /* Data Frame Size */
  251. ctrlr0 |= DFS_8BIT << DFS_SHIFT;
  252. /* set SPI mode 0..3 */
  253. if (priv->mode & SPI_CPOL)
  254. ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
  255. if (priv->mode & SPI_CPHA)
  256. ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
  257. /* Chip Select Mode */
  258. ctrlr0 |= CSM_KEEP << CSM_SHIFT;
  259. /* SSN to Sclk_out delay */
  260. ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
  261. /* Serial Endian Mode */
  262. ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
  263. /* First Bit Mode */
  264. ctrlr0 |= FBM_MSB << FBM_SHIFT;
  265. /* Byte and Halfword Transform */
  266. ctrlr0 |= HALF_WORD_OFF << HALF_WORD_TX_SHIFT;
  267. /* Rxd Sample Delay */
  268. ctrlr0 |= 0 << RXDSD_SHIFT;
  269. /* Frame Format */
  270. ctrlr0 |= FRF_SPI << FRF_SHIFT;
  271. /* Tx and Rx mode */
  272. ctrlr0 |= TMOD_TR << TMOD_SHIFT;
  273. writel(ctrlr0, &regs->ctrlr0);
  274. return 0;
  275. }
  276. static int rockchip_spi_release_bus(struct udevice *dev)
  277. {
  278. struct udevice *bus = dev->parent;
  279. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  280. rkspi_enable_chip(priv->regs, false);
  281. return 0;
  282. }
  283. static inline int rockchip_spi_16bit_reader(struct udevice *dev,
  284. u8 **din, int *len)
  285. {
  286. struct udevice *bus = dev->parent;
  287. const struct rockchip_spi_params * const data =
  288. (void *)dev_get_driver_data(bus);
  289. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  290. struct rockchip_spi *regs = priv->regs;
  291. const u32 saved_ctrlr0 = readl(&regs->ctrlr0);
  292. #if defined(DEBUG)
  293. u32 statistics_rxlevels[33] = { };
  294. #endif
  295. u32 frames = *len / 2;
  296. u8 *in = (u8 *)(*din);
  297. u32 max_chunk_size = SPI_FIFO_DEPTH;
  298. if (!frames)
  299. return 0;
  300. /*
  301. * If we know that the hardware will manage RXFIFO overruns
  302. * (i.e. stop the SPI clock until there's space in the FIFO),
  303. * we the allow largest possible chunk size that can be
  304. * represented in CTRLR1.
  305. */
  306. if (data && data->master_manages_fifo)
  307. max_chunk_size = 0x10000;
  308. // rockchip_spi_configure(dev, mode, size)
  309. rkspi_enable_chip(regs, false);
  310. clrsetbits_le32(&regs->ctrlr0,
  311. TMOD_MASK << TMOD_SHIFT,
  312. TMOD_RO << TMOD_SHIFT);
  313. /* 16bit data frame size */
  314. clrsetbits_le32(&regs->ctrlr0, DFS_MASK, DFS_16BIT);
  315. /* Update caller's context */
  316. const u32 bytes_to_process = 2 * frames;
  317. *din += bytes_to_process;
  318. *len -= bytes_to_process;
  319. /* Process our frames */
  320. while (frames) {
  321. u32 chunk_size = min(frames, max_chunk_size);
  322. frames -= chunk_size;
  323. writew(chunk_size - 1, &regs->ctrlr1);
  324. rkspi_enable_chip(regs, true);
  325. do {
  326. u32 rx_level = readw(&regs->rxflr);
  327. #if defined(DEBUG)
  328. statistics_rxlevels[rx_level]++;
  329. #endif
  330. chunk_size -= rx_level;
  331. while (rx_level--) {
  332. u16 val = readw(regs->rxdr);
  333. *in++ = val & 0xff;
  334. *in++ = val >> 8;
  335. }
  336. } while (chunk_size);
  337. rkspi_enable_chip(regs, false);
  338. }
  339. #if defined(DEBUG)
  340. debug("%s: observed rx_level during processing:\n", __func__);
  341. for (int i = 0; i <= 32; ++i)
  342. if (statistics_rxlevels[i])
  343. debug("\t%2d: %d\n", i, statistics_rxlevels[i]);
  344. #endif
  345. /* Restore the original transfer setup and return error-free. */
  346. writel(saved_ctrlr0, &regs->ctrlr0);
  347. return 0;
  348. }
  349. static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
  350. const void *dout, void *din, unsigned long flags)
  351. {
  352. struct udevice *bus = dev->parent;
  353. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  354. struct rockchip_spi *regs = priv->regs;
  355. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  356. int len = bitlen >> 3;
  357. const u8 *out = dout;
  358. u8 *in = din;
  359. int toread, towrite;
  360. int ret = 0;
  361. debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
  362. len, flags);
  363. if (DEBUG_RK_SPI)
  364. rkspi_dump_regs(regs);
  365. /* Assert CS before transfer */
  366. if (flags & SPI_XFER_BEGIN)
  367. spi_cs_activate(dev, slave_plat->cs);
  368. /*
  369. * To ensure fast loading of firmware images (e.g. full U-Boot
  370. * stage, ATF, Linux kernel) from SPI flash, we optimise the
  371. * case of read-only transfers by using the full 16bits of each
  372. * FIFO element.
  373. */
  374. if (!out)
  375. ret = rockchip_spi_16bit_reader(dev, &in, &len);
  376. /* This is the original 8bit reader/writer code */
  377. while (len > 0) {
  378. int todo = min(len, 0x10000);
  379. rkspi_enable_chip(regs, false);
  380. writel(todo - 1, &regs->ctrlr1);
  381. rkspi_enable_chip(regs, true);
  382. toread = todo;
  383. towrite = todo;
  384. while (toread || towrite) {
  385. u32 status = readl(&regs->sr);
  386. if (towrite && !(status & SR_TF_FULL)) {
  387. writel(out ? *out++ : 0, regs->txdr);
  388. towrite--;
  389. }
  390. if (toread && !(status & SR_RF_EMPT)) {
  391. u32 byte = readl(regs->rxdr);
  392. if (in)
  393. *in++ = byte;
  394. toread--;
  395. }
  396. }
  397. /*
  398. * In case that there's a transmit-component, we need to wait
  399. * until the control goes idle before we can disable the SPI
  400. * control logic (as this will implictly flush the FIFOs).
  401. */
  402. if (out) {
  403. ret = rkspi_wait_till_not_busy(regs);
  404. if (ret)
  405. break;
  406. }
  407. len -= todo;
  408. }
  409. /* Deassert CS after transfer */
  410. if (flags & SPI_XFER_END)
  411. spi_cs_deactivate(dev, slave_plat->cs);
  412. rkspi_enable_chip(regs, false);
  413. return ret;
  414. }
  415. static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
  416. {
  417. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  418. /* Clamp to the maximum frequency specified in the DTS */
  419. if (speed > priv->max_freq)
  420. speed = priv->max_freq;
  421. priv->speed_hz = speed;
  422. return 0;
  423. }
  424. static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
  425. {
  426. struct rockchip_spi_priv *priv = dev_get_priv(bus);
  427. priv->mode = mode;
  428. return 0;
  429. }
  430. static const struct dm_spi_ops rockchip_spi_ops = {
  431. .claim_bus = rockchip_spi_claim_bus,
  432. .release_bus = rockchip_spi_release_bus,
  433. .xfer = rockchip_spi_xfer,
  434. .set_speed = rockchip_spi_set_speed,
  435. .set_mode = rockchip_spi_set_mode,
  436. /*
  437. * cs_info is not needed, since we require all chip selects to be
  438. * in the device tree explicitly
  439. */
  440. };
  441. const struct rockchip_spi_params rk3399_spi_params = {
  442. .master_manages_fifo = true,
  443. };
  444. static const struct udevice_id rockchip_spi_ids[] = {
  445. { .compatible = "rockchip,rk3288-spi" },
  446. { .compatible = "rockchip,rk3368-spi",
  447. .data = (ulong)&rk3399_spi_params },
  448. { .compatible = "rockchip,rk3399-spi",
  449. .data = (ulong)&rk3399_spi_params },
  450. { }
  451. };
  452. U_BOOT_DRIVER(rockchip_spi) = {
  453. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  454. .name = "rockchip_rk3288_spi",
  455. #else
  456. .name = "rockchip_spi",
  457. #endif
  458. .id = UCLASS_SPI,
  459. .of_match = rockchip_spi_ids,
  460. .ops = &rockchip_spi_ops,
  461. .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
  462. .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
  463. .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
  464. .probe = rockchip_spi_probe,
  465. };