exynos_spi.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012 SAMSUNG Electronics
  4. * Padmavathi Venna <padma.v@samsung.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <malloc.h>
  10. #include <spi.h>
  11. #include <fdtdec.h>
  12. #include <time.h>
  13. #include <asm/arch/clk.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/cpu.h>
  16. #include <asm/arch/gpio.h>
  17. #include <asm/arch/pinmux.h>
  18. #include <asm/arch/spi.h>
  19. #include <asm/io.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. struct exynos_spi_platdata {
  22. enum periph_id periph_id;
  23. s32 frequency; /* Default clock frequency, -1 for none */
  24. struct exynos_spi *regs;
  25. uint deactivate_delay_us; /* Delay to wait after deactivate */
  26. };
  27. struct exynos_spi_priv {
  28. struct exynos_spi *regs;
  29. unsigned int freq; /* Default frequency */
  30. unsigned int mode;
  31. enum periph_id periph_id; /* Peripheral ID for this device */
  32. unsigned int fifo_size;
  33. int skip_preamble;
  34. ulong last_transaction_us; /* Time of last transaction end */
  35. };
  36. /**
  37. * Flush spi tx, rx fifos and reset the SPI controller
  38. *
  39. * @param regs Pointer to SPI registers
  40. */
  41. static void spi_flush_fifo(struct exynos_spi *regs)
  42. {
  43. clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
  44. clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
  45. setbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
  46. }
  47. static void spi_get_fifo_levels(struct exynos_spi *regs,
  48. int *rx_lvl, int *tx_lvl)
  49. {
  50. uint32_t spi_sts = readl(&regs->spi_sts);
  51. *rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
  52. *tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
  53. }
  54. /**
  55. * If there's something to transfer, do a software reset and set a
  56. * transaction size.
  57. *
  58. * @param regs SPI peripheral registers
  59. * @param count Number of bytes to transfer
  60. * @param step Number of bytes to transfer in each packet (1 or 4)
  61. */
  62. static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
  63. {
  64. debug("%s: regs=%p, count=%d, step=%d\n", __func__, regs, count, step);
  65. /* For word address we need to swap bytes */
  66. if (step == 4) {
  67. setbits_le32(&regs->mode_cfg,
  68. SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
  69. count /= 4;
  70. setbits_le32(&regs->swap_cfg, SPI_TX_SWAP_EN | SPI_RX_SWAP_EN |
  71. SPI_TX_BYTE_SWAP | SPI_RX_BYTE_SWAP |
  72. SPI_TX_HWORD_SWAP | SPI_RX_HWORD_SWAP);
  73. } else {
  74. /* Select byte access and clear the swap configuration */
  75. clrbits_le32(&regs->mode_cfg,
  76. SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
  77. writel(0, &regs->swap_cfg);
  78. }
  79. assert(count && count < (1 << 16));
  80. setbits_le32(&regs->ch_cfg, SPI_CH_RST);
  81. clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
  82. writel(count | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
  83. }
  84. static int spi_rx_tx(struct exynos_spi_priv *priv, int todo,
  85. void **dinp, void const **doutp, unsigned long flags)
  86. {
  87. struct exynos_spi *regs = priv->regs;
  88. uchar *rxp = *dinp;
  89. const uchar *txp = *doutp;
  90. int rx_lvl, tx_lvl;
  91. uint out_bytes, in_bytes;
  92. int toread;
  93. unsigned start = get_timer(0);
  94. int stopping;
  95. int step;
  96. out_bytes = in_bytes = todo;
  97. stopping = priv->skip_preamble && (flags & SPI_XFER_END) &&
  98. !(priv->mode & SPI_SLAVE);
  99. /*
  100. * Try to transfer words if we can. This helps read performance at
  101. * SPI clock speeds above about 20MHz.
  102. */
  103. step = 1;
  104. if (!((todo | (uintptr_t)rxp | (uintptr_t)txp) & 3) &&
  105. !priv->skip_preamble)
  106. step = 4;
  107. /*
  108. * If there's something to send, do a software reset and set a
  109. * transaction size.
  110. */
  111. spi_request_bytes(regs, todo, step);
  112. /*
  113. * Bytes are transmitted/received in pairs. Wait to receive all the
  114. * data because then transmission will be done as well.
  115. */
  116. toread = in_bytes;
  117. while (in_bytes) {
  118. int temp;
  119. /* Keep the fifos full/empty. */
  120. spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl);
  121. /*
  122. * Don't completely fill the txfifo, since we don't want our
  123. * rxfifo to overflow, and it may already contain data.
  124. */
  125. while (tx_lvl < priv->fifo_size/2 && out_bytes) {
  126. if (!txp)
  127. temp = -1;
  128. else if (step == 4)
  129. temp = *(uint32_t *)txp;
  130. else
  131. temp = *txp;
  132. writel(temp, &regs->tx_data);
  133. out_bytes -= step;
  134. if (txp)
  135. txp += step;
  136. tx_lvl += step;
  137. }
  138. if (rx_lvl >= step) {
  139. while (rx_lvl >= step) {
  140. temp = readl(&regs->rx_data);
  141. if (priv->skip_preamble) {
  142. if (temp == SPI_PREAMBLE_END_BYTE) {
  143. priv->skip_preamble = 0;
  144. stopping = 0;
  145. }
  146. } else {
  147. if (rxp || stopping) {
  148. if (step == 4)
  149. *(uint32_t *)rxp = temp;
  150. else
  151. *rxp = temp;
  152. rxp += step;
  153. }
  154. in_bytes -= step;
  155. }
  156. toread -= step;
  157. rx_lvl -= step;
  158. }
  159. } else if (!toread) {
  160. /*
  161. * We have run out of input data, but haven't read
  162. * enough bytes after the preamble yet. Read some more,
  163. * and make sure that we transmit dummy bytes too, to
  164. * keep things going.
  165. */
  166. assert(!out_bytes);
  167. out_bytes = in_bytes;
  168. toread = in_bytes;
  169. txp = NULL;
  170. spi_request_bytes(regs, toread, step);
  171. }
  172. if (priv->skip_preamble && get_timer(start) > 100) {
  173. debug("SPI timeout: in_bytes=%d, out_bytes=%d, ",
  174. in_bytes, out_bytes);
  175. return -ETIMEDOUT;
  176. }
  177. }
  178. *dinp = rxp;
  179. *doutp = txp;
  180. return 0;
  181. }
  182. /**
  183. * Activate the CS by driving it LOW
  184. *
  185. * @param slave Pointer to spi_slave to which controller has to
  186. * communicate with
  187. */
  188. static void spi_cs_activate(struct udevice *dev)
  189. {
  190. struct udevice *bus = dev->parent;
  191. struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
  192. struct exynos_spi_priv *priv = dev_get_priv(bus);
  193. /* If it's too soon to do another transaction, wait */
  194. if (pdata->deactivate_delay_us &&
  195. priv->last_transaction_us) {
  196. ulong delay_us; /* The delay completed so far */
  197. delay_us = timer_get_us() - priv->last_transaction_us;
  198. if (delay_us < pdata->deactivate_delay_us)
  199. udelay(pdata->deactivate_delay_us - delay_us);
  200. }
  201. clrbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
  202. debug("Activate CS, bus '%s'\n", bus->name);
  203. priv->skip_preamble = priv->mode & SPI_PREAMBLE;
  204. }
  205. /**
  206. * Deactivate the CS by driving it HIGH
  207. *
  208. * @param slave Pointer to spi_slave to which controller has to
  209. * communicate with
  210. */
  211. static void spi_cs_deactivate(struct udevice *dev)
  212. {
  213. struct udevice *bus = dev->parent;
  214. struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
  215. struct exynos_spi_priv *priv = dev_get_priv(bus);
  216. setbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
  217. /* Remember time of this transaction so we can honour the bus delay */
  218. if (pdata->deactivate_delay_us)
  219. priv->last_transaction_us = timer_get_us();
  220. debug("Deactivate CS, bus '%s'\n", bus->name);
  221. }
  222. static int exynos_spi_ofdata_to_platdata(struct udevice *bus)
  223. {
  224. struct exynos_spi_platdata *plat = bus->platdata;
  225. const void *blob = gd->fdt_blob;
  226. int node = dev_of_offset(bus);
  227. plat->regs = (struct exynos_spi *)devfdt_get_addr(bus);
  228. plat->periph_id = pinmux_decode_periph_id(blob, node);
  229. if (plat->periph_id == PERIPH_ID_NONE) {
  230. debug("%s: Invalid peripheral ID %d\n", __func__,
  231. plat->periph_id);
  232. return -FDT_ERR_NOTFOUND;
  233. }
  234. /* Use 500KHz as a suitable default */
  235. plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
  236. 500000);
  237. plat->deactivate_delay_us = fdtdec_get_int(blob, node,
  238. "spi-deactivate-delay", 0);
  239. debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
  240. __func__, plat->regs, plat->periph_id, plat->frequency,
  241. plat->deactivate_delay_us);
  242. return 0;
  243. }
  244. static int exynos_spi_probe(struct udevice *bus)
  245. {
  246. struct exynos_spi_platdata *plat = dev_get_platdata(bus);
  247. struct exynos_spi_priv *priv = dev_get_priv(bus);
  248. priv->regs = plat->regs;
  249. if (plat->periph_id == PERIPH_ID_SPI1 ||
  250. plat->periph_id == PERIPH_ID_SPI2)
  251. priv->fifo_size = 64;
  252. else
  253. priv->fifo_size = 256;
  254. priv->skip_preamble = 0;
  255. priv->last_transaction_us = timer_get_us();
  256. priv->freq = plat->frequency;
  257. priv->periph_id = plat->periph_id;
  258. return 0;
  259. }
  260. static int exynos_spi_claim_bus(struct udevice *dev)
  261. {
  262. struct udevice *bus = dev->parent;
  263. struct exynos_spi_priv *priv = dev_get_priv(bus);
  264. exynos_pinmux_config(priv->periph_id, PINMUX_FLAG_NONE);
  265. spi_flush_fifo(priv->regs);
  266. writel(SPI_FB_DELAY_180, &priv->regs->fb_clk);
  267. return 0;
  268. }
  269. static int exynos_spi_release_bus(struct udevice *dev)
  270. {
  271. struct udevice *bus = dev->parent;
  272. struct exynos_spi_priv *priv = dev_get_priv(bus);
  273. spi_flush_fifo(priv->regs);
  274. return 0;
  275. }
  276. static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
  277. const void *dout, void *din, unsigned long flags)
  278. {
  279. struct udevice *bus = dev->parent;
  280. struct exynos_spi_priv *priv = dev_get_priv(bus);
  281. int upto, todo;
  282. int bytelen;
  283. int ret = 0;
  284. /* spi core configured to do 8 bit transfers */
  285. if (bitlen % 8) {
  286. debug("Non byte aligned SPI transfer.\n");
  287. return -1;
  288. }
  289. /* Start the transaction, if necessary. */
  290. if ((flags & SPI_XFER_BEGIN))
  291. spi_cs_activate(dev);
  292. /*
  293. * Exynos SPI limits each transfer to 65535 transfers. To keep
  294. * things simple, allow a maximum of 65532 bytes. We could allow
  295. * more in word mode, but the performance difference is small.
  296. */
  297. bytelen = bitlen / 8;
  298. for (upto = 0; !ret && upto < bytelen; upto += todo) {
  299. todo = min(bytelen - upto, (1 << 16) - 4);
  300. ret = spi_rx_tx(priv, todo, &din, &dout, flags);
  301. if (ret)
  302. break;
  303. }
  304. /* Stop the transaction, if necessary. */
  305. if ((flags & SPI_XFER_END) && !(priv->mode & SPI_SLAVE)) {
  306. spi_cs_deactivate(dev);
  307. if (priv->skip_preamble) {
  308. assert(!priv->skip_preamble);
  309. debug("Failed to complete premable transaction\n");
  310. ret = -1;
  311. }
  312. }
  313. return ret;
  314. }
  315. static int exynos_spi_set_speed(struct udevice *bus, uint speed)
  316. {
  317. struct exynos_spi_platdata *plat = bus->platdata;
  318. struct exynos_spi_priv *priv = dev_get_priv(bus);
  319. int ret;
  320. if (speed > plat->frequency)
  321. speed = plat->frequency;
  322. ret = set_spi_clk(priv->periph_id, speed);
  323. if (ret)
  324. return ret;
  325. priv->freq = speed;
  326. debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
  327. return 0;
  328. }
  329. static int exynos_spi_set_mode(struct udevice *bus, uint mode)
  330. {
  331. struct exynos_spi_priv *priv = dev_get_priv(bus);
  332. uint32_t reg;
  333. reg = readl(&priv->regs->ch_cfg);
  334. reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
  335. if (mode & SPI_CPHA)
  336. reg |= SPI_CH_CPHA_B;
  337. if (mode & SPI_CPOL)
  338. reg |= SPI_CH_CPOL_L;
  339. writel(reg, &priv->regs->ch_cfg);
  340. priv->mode = mode;
  341. debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
  342. return 0;
  343. }
  344. static const struct dm_spi_ops exynos_spi_ops = {
  345. .claim_bus = exynos_spi_claim_bus,
  346. .release_bus = exynos_spi_release_bus,
  347. .xfer = exynos_spi_xfer,
  348. .set_speed = exynos_spi_set_speed,
  349. .set_mode = exynos_spi_set_mode,
  350. /*
  351. * cs_info is not needed, since we require all chip selects to be
  352. * in the device tree explicitly
  353. */
  354. };
  355. static const struct udevice_id exynos_spi_ids[] = {
  356. { .compatible = "samsung,exynos-spi" },
  357. { }
  358. };
  359. U_BOOT_DRIVER(exynos_spi) = {
  360. .name = "exynos_spi",
  361. .id = UCLASS_SPI,
  362. .of_match = exynos_spi_ids,
  363. .ops = &exynos_spi_ops,
  364. .ofdata_to_platdata = exynos_spi_ofdata_to_platdata,
  365. .platdata_auto_alloc_size = sizeof(struct exynos_spi_platdata),
  366. .priv_auto_alloc_size = sizeof(struct exynos_spi_priv),
  367. .probe = exynos_spi_probe,
  368. };