ath79_spi.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
  4. */
  5. #include <common.h>
  6. #include <spi.h>
  7. #include <dm.h>
  8. #include <div64.h>
  9. #include <errno.h>
  10. #include <time.h>
  11. #include <asm/io.h>
  12. #include <asm/addrspace.h>
  13. #include <asm/types.h>
  14. #include <dm/pinctrl.h>
  15. #include <mach/ar71xx_regs.h>
  16. /* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */
  17. #define ATH79_SPI_CLK_DIV(x) (((x) >> 1) - 1)
  18. #define ATH79_SPI_RRW_DELAY_FACTOR 12000
  19. #define ATH79_SPI_MHZ (1000 * 1000)
  20. struct ath79_spi_priv {
  21. void __iomem *regs;
  22. u32 rrw_delay;
  23. };
  24. static void spi_cs_activate(struct udevice *dev)
  25. {
  26. struct udevice *bus = dev_get_parent(dev);
  27. struct ath79_spi_priv *priv = dev_get_priv(bus);
  28. writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS);
  29. writel(AR71XX_SPI_IOC_CS_ALL, priv->regs + AR71XX_SPI_REG_IOC);
  30. }
  31. static void spi_cs_deactivate(struct udevice *dev)
  32. {
  33. struct udevice *bus = dev_get_parent(dev);
  34. struct ath79_spi_priv *priv = dev_get_priv(bus);
  35. writel(AR71XX_SPI_IOC_CS_ALL, priv->regs + AR71XX_SPI_REG_IOC);
  36. writel(0, priv->regs + AR71XX_SPI_REG_FS);
  37. }
  38. static int ath79_spi_claim_bus(struct udevice *dev)
  39. {
  40. return 0;
  41. }
  42. static int ath79_spi_release_bus(struct udevice *dev)
  43. {
  44. return 0;
  45. }
  46. static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen,
  47. const void *dout, void *din, unsigned long flags)
  48. {
  49. struct udevice *bus = dev_get_parent(dev);
  50. struct ath79_spi_priv *priv = dev_get_priv(bus);
  51. struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
  52. u8 *rx = din;
  53. const u8 *tx = dout;
  54. u8 curbyte, curbitlen, restbits;
  55. u32 bytes = bitlen / 8;
  56. u32 out, in;
  57. u64 tick;
  58. if (flags & SPI_XFER_BEGIN)
  59. spi_cs_activate(dev);
  60. restbits = (bitlen % 8);
  61. if (restbits)
  62. bytes++;
  63. out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs));
  64. while (bytes > 0) {
  65. bytes--;
  66. curbyte = 0;
  67. if (tx)
  68. curbyte = *tx++;
  69. if (restbits && !bytes) {
  70. curbitlen = restbits;
  71. curbyte <<= 8 - restbits;
  72. } else {
  73. curbitlen = 8;
  74. }
  75. for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) {
  76. if (curbyte & 0x80)
  77. out |= AR71XX_SPI_IOC_DO;
  78. else
  79. out &= ~(AR71XX_SPI_IOC_DO);
  80. writel(out, priv->regs + AR71XX_SPI_REG_IOC);
  81. /* delay for low level */
  82. if (priv->rrw_delay) {
  83. tick = get_ticks() + priv->rrw_delay;
  84. while (get_ticks() < tick)
  85. /*NOP*/;
  86. }
  87. writel(out | AR71XX_SPI_IOC_CLK,
  88. priv->regs + AR71XX_SPI_REG_IOC);
  89. /* delay for high level */
  90. if (priv->rrw_delay) {
  91. tick = get_ticks() + priv->rrw_delay;
  92. while (get_ticks() < tick)
  93. /*NOP*/;
  94. }
  95. curbyte <<= 1;
  96. }
  97. if (!bytes)
  98. writel(out, priv->regs + AR71XX_SPI_REG_IOC);
  99. in = readl(priv->regs + AR71XX_SPI_REG_RDS);
  100. if (rx) {
  101. if (restbits && !bytes)
  102. *rx++ = (in << (8 - restbits));
  103. else
  104. *rx++ = in;
  105. }
  106. }
  107. if (flags & SPI_XFER_END)
  108. spi_cs_deactivate(dev);
  109. return 0;
  110. }
  111. static int ath79_spi_set_speed(struct udevice *bus, uint speed)
  112. {
  113. struct ath79_spi_priv *priv = dev_get_priv(bus);
  114. u32 val, div = 0;
  115. u64 time;
  116. if (speed)
  117. div = get_bus_freq(0) / speed;
  118. if (div > 63)
  119. div = 63;
  120. if (div < 5)
  121. div = 5;
  122. /* calculate delay */
  123. time = get_tbclk();
  124. do_div(time, speed / 2);
  125. val = get_bus_freq(0) / ATH79_SPI_MHZ;
  126. val = ATH79_SPI_RRW_DELAY_FACTOR / val;
  127. if (time > val)
  128. priv->rrw_delay = time - val + 1;
  129. else
  130. priv->rrw_delay = 0;
  131. writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS);
  132. clrsetbits_be32(priv->regs + AR71XX_SPI_REG_CTRL,
  133. AR71XX_SPI_CTRL_DIV_MASK,
  134. ATH79_SPI_CLK_DIV(div));
  135. writel(0, priv->regs + AR71XX_SPI_REG_FS);
  136. return 0;
  137. }
  138. static int ath79_spi_set_mode(struct udevice *bus, uint mode)
  139. {
  140. return 0;
  141. }
  142. static int ath79_spi_probe(struct udevice *bus)
  143. {
  144. struct ath79_spi_priv *priv = dev_get_priv(bus);
  145. fdt_addr_t addr;
  146. addr = devfdt_get_addr(bus);
  147. if (addr == FDT_ADDR_T_NONE)
  148. return -EINVAL;
  149. priv->regs = map_physmem(addr,
  150. AR71XX_SPI_SIZE,
  151. MAP_NOCACHE);
  152. /* Init SPI Hardware, disable remap, set clock */
  153. writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS);
  154. writel(AR71XX_SPI_CTRL_RD | ATH79_SPI_CLK_DIV(8),
  155. priv->regs + AR71XX_SPI_REG_CTRL);
  156. writel(0, priv->regs + AR71XX_SPI_REG_FS);
  157. return 0;
  158. }
  159. static int ath79_cs_info(struct udevice *bus, uint cs,
  160. struct spi_cs_info *info)
  161. {
  162. /* Always allow activity on CS 0/1/2 */
  163. if (cs >= 3)
  164. return -EINVAL;
  165. return 0;
  166. }
  167. static const struct dm_spi_ops ath79_spi_ops = {
  168. .claim_bus = ath79_spi_claim_bus,
  169. .release_bus = ath79_spi_release_bus,
  170. .xfer = ath79_spi_xfer,
  171. .set_speed = ath79_spi_set_speed,
  172. .set_mode = ath79_spi_set_mode,
  173. .cs_info = ath79_cs_info,
  174. };
  175. static const struct udevice_id ath79_spi_ids[] = {
  176. { .compatible = "qca,ar7100-spi" },
  177. {}
  178. };
  179. U_BOOT_DRIVER(ath79_spi) = {
  180. .name = "ath79_spi",
  181. .id = UCLASS_SPI,
  182. .of_match = ath79_spi_ids,
  183. .ops = &ath79_spi_ops,
  184. .priv_auto_alloc_size = sizeof(struct ath79_spi_priv),
  185. .probe = ath79_spi_probe,
  186. };