bcm2835_sdhci.c 6.9 KB

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  1. /*
  2. * This code was extracted from:
  3. * git://github.com/gonzoua/u-boot-pi.git master
  4. * and hence presumably (C) 2012 Oleksandr Tymoshenko
  5. *
  6. * Tweaks for U-Boot upstreaming
  7. * (C) 2012 Stephen Warren
  8. *
  9. * Portions (e.g. read/write macros, concepts for back-to-back register write
  10. * timing workarounds) obviously extracted from the Linux kernel at:
  11. * https://github.com/raspberrypi/linux.git rpi-3.6.y
  12. *
  13. * The Linux kernel code has the following (c) and license, which is hence
  14. * propagated to Oleksandr's tree and here:
  15. *
  16. * Support for SDHCI device on 2835
  17. * Based on sdhci-bcm2708.c (c) 2010 Broadcom
  18. *
  19. * This program is free software; you can redistribute it and/or modify
  20. * it under the terms of the GNU General Public License version 2 as
  21. * published by the Free Software Foundation.
  22. *
  23. * This program is distributed in the hope that it will be useful,
  24. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  26. * GNU General Public License for more details.
  27. *
  28. * You should have received a copy of the GNU General Public License
  29. * along with this program; if not, write to the Free Software
  30. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  31. */
  32. /* Supports:
  33. * SDHCI platform device - Arasan SD controller in BCM2708
  34. *
  35. * Inspired by sdhci-pci.c, by Pierre Ossman
  36. */
  37. #include <common.h>
  38. #include <dm.h>
  39. #include <malloc.h>
  40. #include <memalign.h>
  41. #include <sdhci.h>
  42. #include <time.h>
  43. #include <asm/arch/msg.h>
  44. #include <asm/arch/mbox.h>
  45. #include <mach/sdhci.h>
  46. #include <mach/timer.h>
  47. /* 400KHz is max freq for card ID etc. Use that as min */
  48. #define MIN_FREQ 400000
  49. #define SDHCI_BUFFER 0x20
  50. struct bcm2835_sdhci_plat {
  51. struct mmc_config cfg;
  52. struct mmc mmc;
  53. };
  54. struct bcm2835_sdhci_host {
  55. struct sdhci_host host;
  56. uint twoticks_delay;
  57. ulong last_write;
  58. };
  59. static inline struct bcm2835_sdhci_host *to_bcm(struct sdhci_host *host)
  60. {
  61. return (struct bcm2835_sdhci_host *)host;
  62. }
  63. static inline void bcm2835_sdhci_raw_writel(struct sdhci_host *host, u32 val,
  64. int reg)
  65. {
  66. struct bcm2835_sdhci_host *bcm_host = to_bcm(host);
  67. /*
  68. * The Arasan has a bugette whereby it may lose the content of
  69. * successive writes to registers that are within two SD-card clock
  70. * cycles of each other (a clock domain crossing problem).
  71. * It seems, however, that the data register does not have this problem.
  72. * (Which is just as well - otherwise we'd have to nobble the DMA engine
  73. * too)
  74. */
  75. if (reg != SDHCI_BUFFER) {
  76. while (timer_get_us() - bcm_host->last_write <
  77. bcm_host->twoticks_delay)
  78. ;
  79. }
  80. writel(val, host->ioaddr + reg);
  81. bcm_host->last_write = timer_get_us();
  82. }
  83. static inline u32 bcm2835_sdhci_raw_readl(struct sdhci_host *host, int reg)
  84. {
  85. return readl(host->ioaddr + reg);
  86. }
  87. static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
  88. {
  89. bcm2835_sdhci_raw_writel(host, val, reg);
  90. }
  91. static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
  92. {
  93. static u32 shadow;
  94. u32 oldval = (reg == SDHCI_COMMAND) ? shadow :
  95. bcm2835_sdhci_raw_readl(host, reg & ~3);
  96. u32 word_num = (reg >> 1) & 1;
  97. u32 word_shift = word_num * 16;
  98. u32 mask = 0xffff << word_shift;
  99. u32 newval = (oldval & ~mask) | (val << word_shift);
  100. if (reg == SDHCI_TRANSFER_MODE)
  101. shadow = newval;
  102. else
  103. bcm2835_sdhci_raw_writel(host, newval, reg & ~3);
  104. }
  105. static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
  106. {
  107. u32 oldval = bcm2835_sdhci_raw_readl(host, reg & ~3);
  108. u32 byte_num = reg & 3;
  109. u32 byte_shift = byte_num * 8;
  110. u32 mask = 0xff << byte_shift;
  111. u32 newval = (oldval & ~mask) | (val << byte_shift);
  112. bcm2835_sdhci_raw_writel(host, newval, reg & ~3);
  113. }
  114. static u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
  115. {
  116. u32 val = bcm2835_sdhci_raw_readl(host, reg);
  117. return val;
  118. }
  119. static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg)
  120. {
  121. u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3));
  122. u32 word_num = (reg >> 1) & 1;
  123. u32 word_shift = word_num * 16;
  124. u32 word = (val >> word_shift) & 0xffff;
  125. return word;
  126. }
  127. static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg)
  128. {
  129. u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3));
  130. u32 byte_num = reg & 3;
  131. u32 byte_shift = byte_num * 8;
  132. u32 byte = (val >> byte_shift) & 0xff;
  133. return byte;
  134. }
  135. static const struct sdhci_ops bcm2835_ops = {
  136. .write_l = bcm2835_sdhci_writel,
  137. .write_w = bcm2835_sdhci_writew,
  138. .write_b = bcm2835_sdhci_writeb,
  139. .read_l = bcm2835_sdhci_readl,
  140. .read_w = bcm2835_sdhci_readw,
  141. .read_b = bcm2835_sdhci_readb,
  142. };
  143. static int bcm2835_sdhci_bind(struct udevice *dev)
  144. {
  145. struct bcm2835_sdhci_plat *plat = dev_get_platdata(dev);
  146. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  147. }
  148. static int bcm2835_sdhci_probe(struct udevice *dev)
  149. {
  150. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  151. struct bcm2835_sdhci_plat *plat = dev_get_platdata(dev);
  152. struct bcm2835_sdhci_host *priv = dev_get_priv(dev);
  153. struct sdhci_host *host = &priv->host;
  154. fdt_addr_t base;
  155. int emmc_freq;
  156. int ret;
  157. int clock_id = (int)dev_get_driver_data(dev);
  158. base = devfdt_get_addr(dev);
  159. if (base == FDT_ADDR_T_NONE)
  160. return -EINVAL;
  161. ret = bcm2835_get_mmc_clock(clock_id);
  162. if (ret < 0) {
  163. debug("%s: Failed to set MMC clock (err=%d)\n", __func__, ret);
  164. return ret;
  165. }
  166. emmc_freq = ret;
  167. /*
  168. * See the comments in bcm2835_sdhci_raw_writel().
  169. *
  170. * This should probably be dynamically calculated based on the actual
  171. * frequency. However, this is the longest we'll have to wait, and
  172. * doesn't seem to slow access down too much, so the added complexity
  173. * doesn't seem worth it for now.
  174. *
  175. * 1/MIN_FREQ is (max) time per tick of eMMC clock.
  176. * 2/MIN_FREQ is time for two ticks.
  177. * Multiply by 1000000 to get uS per two ticks.
  178. * +1 for hack rounding.
  179. */
  180. priv->twoticks_delay = ((2 * 1000000) / MIN_FREQ) + 1;
  181. priv->last_write = 0;
  182. host->name = dev->name;
  183. host->ioaddr = (void *)base;
  184. host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B |
  185. SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT;
  186. host->max_clk = emmc_freq;
  187. host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  188. host->ops = &bcm2835_ops;
  189. host->mmc = &plat->mmc;
  190. host->mmc->dev = dev;
  191. ret = sdhci_setup_cfg(&plat->cfg, host, emmc_freq, MIN_FREQ);
  192. if (ret) {
  193. debug("%s: Failed to setup SDHCI (err=%d)\n", __func__, ret);
  194. return ret;
  195. }
  196. upriv->mmc = &plat->mmc;
  197. host->mmc->priv = host;
  198. return sdhci_probe(dev);
  199. }
  200. static const struct udevice_id bcm2835_sdhci_match[] = {
  201. {
  202. .compatible = "brcm,bcm2835-sdhci",
  203. .data = BCM2835_MBOX_CLOCK_ID_EMMC
  204. },
  205. {
  206. .compatible = "brcm,bcm2711-emmc2",
  207. .data = BCM2835_MBOX_CLOCK_ID_EMMC2
  208. },
  209. { /* sentinel */ }
  210. };
  211. U_BOOT_DRIVER(sdhci_cdns) = {
  212. .name = "sdhci-bcm2835",
  213. .id = UCLASS_MMC,
  214. .of_match = bcm2835_sdhci_match,
  215. .bind = bcm2835_sdhci_bind,
  216. .probe = bcm2835_sdhci_probe,
  217. .priv_auto_alloc_size = sizeof(struct bcm2835_sdhci_host),
  218. .platdata_auto_alloc_size = sizeof(struct bcm2835_sdhci_plat),
  219. .ops = &sdhci_ops,
  220. };