tegra186_bpmp.c 5.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2016, NVIDIA CORPORATION.
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <time.h>
  8. #include <dm/lists.h>
  9. #include <dm/root.h>
  10. #include <mailbox.h>
  11. #include <misc.h>
  12. #include <asm/arch-tegra/bpmp_abi.h>
  13. #include <asm/arch-tegra/ivc.h>
  14. #define BPMP_IVC_FRAME_COUNT 1
  15. #define BPMP_IVC_FRAME_SIZE 128
  16. #define BPMP_FLAG_DO_ACK BIT(0)
  17. #define BPMP_FLAG_RING_DOORBELL BIT(1)
  18. DECLARE_GLOBAL_DATA_PTR;
  19. struct tegra186_bpmp {
  20. struct mbox_chan mbox;
  21. struct tegra_ivc ivc;
  22. };
  23. static int tegra186_bpmp_call(struct udevice *dev, int mrq, void *tx_msg,
  24. int tx_size, void *rx_msg, int rx_size)
  25. {
  26. struct tegra186_bpmp *priv = dev_get_priv(dev);
  27. int ret, err;
  28. void *ivc_frame;
  29. struct mrq_request *req;
  30. struct mrq_response *resp;
  31. ulong start_time;
  32. debug("%s(dev=%p, mrq=%u, tx_msg=%p, tx_size=%d, rx_msg=%p, rx_size=%d) (priv=%p)\n",
  33. __func__, dev, mrq, tx_msg, tx_size, rx_msg, rx_size, priv);
  34. if ((tx_size > BPMP_IVC_FRAME_SIZE) || (rx_size > BPMP_IVC_FRAME_SIZE))
  35. return -EINVAL;
  36. ret = tegra_ivc_write_get_next_frame(&priv->ivc, &ivc_frame);
  37. if (ret) {
  38. pr_err("tegra_ivc_write_get_next_frame() failed: %d\n", ret);
  39. return ret;
  40. }
  41. req = ivc_frame;
  42. req->mrq = mrq;
  43. req->flags = BPMP_FLAG_DO_ACK | BPMP_FLAG_RING_DOORBELL;
  44. memcpy(req + 1, tx_msg, tx_size);
  45. ret = tegra_ivc_write_advance(&priv->ivc);
  46. if (ret) {
  47. pr_err("tegra_ivc_write_advance() failed: %d\n", ret);
  48. return ret;
  49. }
  50. start_time = timer_get_us();
  51. for (;;) {
  52. ret = tegra_ivc_channel_notified(&priv->ivc);
  53. if (ret) {
  54. pr_err("tegra_ivc_channel_notified() failed: %d\n", ret);
  55. return ret;
  56. }
  57. ret = tegra_ivc_read_get_next_frame(&priv->ivc, &ivc_frame);
  58. if (!ret)
  59. break;
  60. /* Timeout 20ms; roughly 10x current max observed duration */
  61. if ((timer_get_us() - start_time) > 20 * 1000) {
  62. pr_err("tegra_ivc_read_get_next_frame() timed out (%d)\n",
  63. ret);
  64. return -ETIMEDOUT;
  65. }
  66. }
  67. resp = ivc_frame;
  68. err = resp->err;
  69. if (!err && rx_msg && rx_size)
  70. memcpy(rx_msg, resp + 1, rx_size);
  71. ret = tegra_ivc_read_advance(&priv->ivc);
  72. if (ret) {
  73. pr_err("tegra_ivc_write_advance() failed: %d\n", ret);
  74. return ret;
  75. }
  76. if (err) {
  77. pr_err("BPMP responded with error %d\n", err);
  78. /* err isn't a U-Boot error code, so don't that */
  79. return -EIO;
  80. }
  81. return rx_size;
  82. }
  83. /**
  84. * The BPMP exposes multiple different services. We create a sub-device for
  85. * each separate type of service, since each device must be of the appropriate
  86. * UCLASS.
  87. */
  88. static int tegra186_bpmp_bind(struct udevice *dev)
  89. {
  90. int ret;
  91. struct udevice *child;
  92. debug("%s(dev=%p)\n", __func__, dev);
  93. ret = device_bind_driver_to_node(dev, "tegra186_clk", "tegra186_clk",
  94. dev_ofnode(dev), &child);
  95. if (ret)
  96. return ret;
  97. ret = device_bind_driver_to_node(dev, "tegra186_reset",
  98. "tegra186_reset", dev_ofnode(dev),
  99. &child);
  100. if (ret)
  101. return ret;
  102. ret = device_bind_driver_to_node(dev, "tegra186_power_domain",
  103. "tegra186_power_domain",
  104. dev_ofnode(dev), &child);
  105. if (ret)
  106. return ret;
  107. ret = dm_scan_fdt_dev(dev);
  108. if (ret)
  109. return ret;
  110. return 0;
  111. }
  112. static ulong tegra186_bpmp_get_shmem(struct udevice *dev, int index)
  113. {
  114. int ret;
  115. struct fdtdec_phandle_args args;
  116. fdt_addr_t reg;
  117. ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev),
  118. "shmem", NULL, 0, index, &args);
  119. if (ret < 0) {
  120. pr_err("fdtdec_parse_phandle_with_args() failed: %d\n", ret);
  121. return ret;
  122. }
  123. reg = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, args.node,
  124. "reg", 0, NULL, true);
  125. if (reg == FDT_ADDR_T_NONE) {
  126. pr_err("fdtdec_get_addr_size_auto_noparent() failed\n");
  127. return -ENODEV;
  128. }
  129. return reg;
  130. }
  131. static void tegra186_bpmp_ivc_notify(struct tegra_ivc *ivc)
  132. {
  133. struct tegra186_bpmp *priv =
  134. container_of(ivc, struct tegra186_bpmp, ivc);
  135. int ret;
  136. ret = mbox_send(&priv->mbox, NULL);
  137. if (ret)
  138. pr_err("mbox_send() failed: %d\n", ret);
  139. }
  140. static int tegra186_bpmp_probe(struct udevice *dev)
  141. {
  142. struct tegra186_bpmp *priv = dev_get_priv(dev);
  143. int ret;
  144. ulong tx_base, rx_base, start_time;
  145. debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv);
  146. ret = mbox_get_by_index(dev, 0, &priv->mbox);
  147. if (ret) {
  148. pr_err("mbox_get_by_index() failed: %d\n", ret);
  149. return ret;
  150. }
  151. tx_base = tegra186_bpmp_get_shmem(dev, 0);
  152. if (IS_ERR_VALUE(tx_base)) {
  153. pr_err("tegra186_bpmp_get_shmem failed for tx_base\n");
  154. return tx_base;
  155. }
  156. rx_base = tegra186_bpmp_get_shmem(dev, 1);
  157. if (IS_ERR_VALUE(rx_base)) {
  158. pr_err("tegra186_bpmp_get_shmem failed for rx_base\n");
  159. return rx_base;
  160. }
  161. debug("shmem: rx=%lx, tx=%lx\n", rx_base, tx_base);
  162. ret = tegra_ivc_init(&priv->ivc, rx_base, tx_base, BPMP_IVC_FRAME_COUNT,
  163. BPMP_IVC_FRAME_SIZE, tegra186_bpmp_ivc_notify);
  164. if (ret) {
  165. pr_err("tegra_ivc_init() failed: %d\n", ret);
  166. return ret;
  167. }
  168. tegra_ivc_channel_reset(&priv->ivc);
  169. start_time = timer_get_us();
  170. for (;;) {
  171. ret = tegra_ivc_channel_notified(&priv->ivc);
  172. if (!ret)
  173. break;
  174. /* Timeout 100ms */
  175. if ((timer_get_us() - start_time) > 100 * 1000) {
  176. pr_err("Initial IVC reset timed out (%d)\n", ret);
  177. ret = -ETIMEDOUT;
  178. goto err_free_mbox;
  179. }
  180. }
  181. return 0;
  182. err_free_mbox:
  183. mbox_free(&priv->mbox);
  184. return ret;
  185. }
  186. static int tegra186_bpmp_remove(struct udevice *dev)
  187. {
  188. struct tegra186_bpmp *priv = dev_get_priv(dev);
  189. debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv);
  190. mbox_free(&priv->mbox);
  191. return 0;
  192. }
  193. static struct misc_ops tegra186_bpmp_ops = {
  194. .call = tegra186_bpmp_call,
  195. };
  196. static const struct udevice_id tegra186_bpmp_ids[] = {
  197. { .compatible = "nvidia,tegra186-bpmp" },
  198. { }
  199. };
  200. U_BOOT_DRIVER(tegra186_bpmp) = {
  201. .name = "tegra186_bpmp",
  202. .id = UCLASS_MISC,
  203. .of_match = tegra186_bpmp_ids,
  204. .bind = tegra186_bpmp_bind,
  205. .probe = tegra186_bpmp_probe,
  206. .remove = tegra186_bpmp_remove,
  207. .ops = &tegra186_bpmp_ops,
  208. .priv_auto_alloc_size = sizeof(struct tegra186_bpmp),
  209. };