clock.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. /* Tegra SoC common clock control functions */
  6. #include <common.h>
  7. #include <div64.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <time.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/tegra.h>
  14. #include <asm/arch-tegra/ap.h>
  15. #include <asm/arch-tegra/clk_rst.h>
  16. #include <asm/arch-tegra/pmc.h>
  17. #include <asm/arch-tegra/timer.h>
  18. /*
  19. * This is our record of the current clock rate of each clock. We don't
  20. * fill all of these in since we are only really interested in clocks which
  21. * we use as parents.
  22. */
  23. static unsigned pll_rate[CLOCK_ID_COUNT];
  24. /*
  25. * The oscillator frequency is fixed to one of four set values. Based on this
  26. * the other clocks are set up appropriately.
  27. */
  28. static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
  29. 13000000,
  30. 19200000,
  31. 12000000,
  32. 26000000,
  33. 38400000,
  34. 48000000,
  35. };
  36. /* return 1 if a peripheral ID is in range */
  37. #define clock_type_id_isvalid(id) ((id) >= 0 && \
  38. (id) < CLOCK_TYPE_COUNT)
  39. char pllp_valid = 1; /* PLLP is set up correctly */
  40. /* return 1 if a periphc_internal_id is in range */
  41. #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
  42. (id) < PERIPHC_COUNT)
  43. /* number of clock outputs of a PLL */
  44. static const u8 pll_num_clkouts[] = {
  45. 1, /* PLLC */
  46. 1, /* PLLM */
  47. 4, /* PLLP */
  48. 1, /* PLLA */
  49. 0, /* PLLU */
  50. 0, /* PLLD */
  51. };
  52. int clock_get_osc_bypass(void)
  53. {
  54. struct clk_rst_ctlr *clkrst =
  55. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  56. u32 reg;
  57. reg = readl(&clkrst->crc_osc_ctrl);
  58. return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
  59. }
  60. /* Returns a pointer to the registers of the given pll */
  61. static struct clk_pll *get_pll(enum clock_id clkid)
  62. {
  63. struct clk_rst_ctlr *clkrst =
  64. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  65. assert(clock_id_is_pll(clkid));
  66. if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
  67. debug("%s: Invalid PLL %d\n", __func__, clkid);
  68. return NULL;
  69. }
  70. return &clkrst->crc_pll[clkid];
  71. }
  72. __weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
  73. {
  74. return NULL;
  75. }
  76. int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
  77. u32 *divp, u32 *cpcon, u32 *lfcon)
  78. {
  79. struct clk_pll *pll = get_pll(clkid);
  80. struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
  81. u32 data;
  82. assert(clkid != CLOCK_ID_USB);
  83. /* Safety check, adds to code size but is small */
  84. if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
  85. return -1;
  86. data = readl(&pll->pll_base);
  87. *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask;
  88. *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask;
  89. *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask;
  90. data = readl(&pll->pll_misc);
  91. /* NOTE: On T210, cpcon/lfcon no longer exist, moved to KCP/KVCO */
  92. *cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask;
  93. *lfcon = (data >> pllinfo->kvco_shift) & pllinfo->kvco_mask;
  94. return 0;
  95. }
  96. unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
  97. u32 divp, u32 cpcon, u32 lfcon)
  98. {
  99. struct clk_pll *pll = NULL;
  100. struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
  101. struct clk_pll_simple *simple_pll = NULL;
  102. u32 misc_data, data;
  103. if (clkid < (enum clock_id)TEGRA_CLK_PLLS) {
  104. pll = get_pll(clkid);
  105. } else {
  106. simple_pll = clock_get_simple_pll(clkid);
  107. if (!simple_pll) {
  108. debug("%s: Uknown simple PLL %d\n", __func__, clkid);
  109. return 0;
  110. }
  111. }
  112. /*
  113. * pllinfo has the m/n/p and kcp/kvco mask and shift
  114. * values for all of the PLLs used in U-Boot, with any
  115. * SoC differences accounted for.
  116. *
  117. * Preserve EN_LOCKDET, etc.
  118. */
  119. if (pll)
  120. misc_data = readl(&pll->pll_misc);
  121. else
  122. misc_data = readl(&simple_pll->pll_misc);
  123. misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
  124. misc_data |= cpcon << pllinfo->kcp_shift;
  125. misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift);
  126. misc_data |= lfcon << pllinfo->kvco_shift;
  127. data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift);
  128. data |= divp << pllinfo->p_shift;
  129. data |= (1 << PLL_ENABLE_SHIFT); /* BYPASS s/b 0 already */
  130. if (pll) {
  131. writel(misc_data, &pll->pll_misc);
  132. writel(data, &pll->pll_base);
  133. } else {
  134. writel(misc_data, &simple_pll->pll_misc);
  135. writel(data, &simple_pll->pll_base);
  136. }
  137. /* calculate the stable time */
  138. return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
  139. }
  140. void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
  141. unsigned divisor)
  142. {
  143. u32 *reg = get_periph_source_reg(periph_id);
  144. u32 value;
  145. value = readl(reg);
  146. value &= ~OUT_CLK_SOURCE_31_30_MASK;
  147. value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
  148. value &= ~OUT_CLK_DIVISOR_MASK;
  149. value |= divisor << OUT_CLK_DIVISOR_SHIFT;
  150. writel(value, reg);
  151. }
  152. int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
  153. unsigned source)
  154. {
  155. u32 *reg = get_periph_source_reg(periph_id);
  156. switch (mux_bits) {
  157. case MASK_BITS_31_30:
  158. clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
  159. source << OUT_CLK_SOURCE_31_30_SHIFT);
  160. break;
  161. case MASK_BITS_31_29:
  162. clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
  163. source << OUT_CLK_SOURCE_31_29_SHIFT);
  164. break;
  165. case MASK_BITS_31_28:
  166. clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
  167. source << OUT_CLK_SOURCE_31_28_SHIFT);
  168. break;
  169. default:
  170. return -1;
  171. }
  172. return 0;
  173. }
  174. static int clock_ll_get_source_bits(enum periph_id periph_id, int mux_bits)
  175. {
  176. u32 *reg = get_periph_source_reg(periph_id);
  177. u32 val = readl(reg);
  178. switch (mux_bits) {
  179. case MASK_BITS_31_30:
  180. val >>= OUT_CLK_SOURCE_31_30_SHIFT;
  181. val &= OUT_CLK_SOURCE_31_30_MASK;
  182. return val;
  183. case MASK_BITS_31_29:
  184. val >>= OUT_CLK_SOURCE_31_29_SHIFT;
  185. val &= OUT_CLK_SOURCE_31_29_MASK;
  186. return val;
  187. case MASK_BITS_31_28:
  188. val >>= OUT_CLK_SOURCE_31_28_SHIFT;
  189. val &= OUT_CLK_SOURCE_31_28_MASK;
  190. return val;
  191. default:
  192. return -1;
  193. }
  194. }
  195. void clock_ll_set_source(enum periph_id periph_id, unsigned source)
  196. {
  197. clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source);
  198. }
  199. /**
  200. * Given the parent's rate and the required rate for the children, this works
  201. * out the peripheral clock divider to use, in 7.1 binary format.
  202. *
  203. * @param divider_bits number of divider bits (8 or 16)
  204. * @param parent_rate clock rate of parent clock in Hz
  205. * @param rate required clock rate for this clock
  206. * @return divider which should be used
  207. */
  208. static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
  209. unsigned long rate)
  210. {
  211. u64 divider = parent_rate * 2;
  212. unsigned max_divider = 1 << divider_bits;
  213. divider += rate - 1;
  214. do_div(divider, rate);
  215. if ((s64)divider - 2 < 0)
  216. return 0;
  217. if ((s64)divider - 2 >= max_divider)
  218. return -1;
  219. return divider - 2;
  220. }
  221. int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
  222. {
  223. struct clk_pll *pll = get_pll(clkid);
  224. int data = 0, div = 0, offset = 0;
  225. if (!clock_id_is_pll(clkid))
  226. return -1;
  227. if (pllout + 1 > pll_num_clkouts[clkid])
  228. return -1;
  229. div = clk_get_divider(8, pll_rate[clkid], rate);
  230. if (div < 0)
  231. return -1;
  232. /* out2 and out4 are in the high part of the register */
  233. if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
  234. offset = 16;
  235. data = (div << PLL_OUT_RATIO_SHIFT) |
  236. PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
  237. clrsetbits_le32(&pll->pll_out[pllout >> 1],
  238. PLL_OUT_RATIO_MASK << offset, data << offset);
  239. return 0;
  240. }
  241. /**
  242. * Given the parent's rate and the divider in 7.1 format, this works out the
  243. * resulting peripheral clock rate.
  244. *
  245. * @param parent_rate clock rate of parent clock in Hz
  246. * @param divider which should be used in 7.1 format
  247. * @return effective clock rate of peripheral
  248. */
  249. static unsigned long get_rate_from_divider(unsigned long parent_rate,
  250. int divider)
  251. {
  252. u64 rate;
  253. rate = (u64)parent_rate * 2;
  254. do_div(rate, divider + 2);
  255. return rate;
  256. }
  257. unsigned long clock_get_periph_rate(enum periph_id periph_id,
  258. enum clock_id parent)
  259. {
  260. u32 *reg = get_periph_source_reg(periph_id);
  261. unsigned parent_rate = pll_rate[parent];
  262. int div = (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT;
  263. switch (periph_id) {
  264. case PERIPH_ID_UART1:
  265. case PERIPH_ID_UART2:
  266. case PERIPH_ID_UART3:
  267. case PERIPH_ID_UART4:
  268. case PERIPH_ID_UART5:
  269. #ifdef CONFIG_TEGRA20
  270. /* There's no divider for these clocks in this SoC. */
  271. return parent_rate;
  272. #else
  273. /*
  274. * This undoes the +2 in get_rate_from_divider() which I
  275. * believe is incorrect. Ideally we would fix
  276. * get_rate_from_divider(), but... Removing the +2 from
  277. * get_rate_from_divider() would probably require remove the -2
  278. * from the tail of clk_get_divider() since I believe that's
  279. * only there to invert get_rate_from_divider()'s +2. Observe
  280. * how find_best_divider() uses those two functions together.
  281. * However, doing so breaks other stuff, such as Seaboard's
  282. * display, likely due to clock_set_pllout()'s call to
  283. * clk_get_divider(). Attempting to fix that by making
  284. * clock_set_pllout() subtract 2 from clk_get_divider()'s
  285. * return value doesn't help. In summary this clock driver is
  286. * quite broken but I'm afraid I have no idea how to fix it
  287. * without completely replacing it.
  288. *
  289. * Be careful to avoid a divide by zero error.
  290. */
  291. if (div >= 1)
  292. div -= 2;
  293. break;
  294. #endif
  295. default:
  296. break;
  297. }
  298. return get_rate_from_divider(parent_rate, div);
  299. }
  300. /**
  301. * Find the best available 7.1 format divisor given a parent clock rate and
  302. * required child clock rate. This function assumes that a second-stage
  303. * divisor is available which can divide by powers of 2 from 1 to 256.
  304. *
  305. * @param divider_bits number of divider bits (8 or 16)
  306. * @param parent_rate clock rate of parent clock in Hz
  307. * @param rate required clock rate for this clock
  308. * @param extra_div value for the second-stage divisor (not set if this
  309. * function returns -1.
  310. * @return divider which should be used, or -1 if nothing is valid
  311. *
  312. */
  313. static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
  314. unsigned long rate, int *extra_div)
  315. {
  316. int shift;
  317. int best_divider = -1;
  318. int best_error = rate;
  319. /* try dividers from 1 to 256 and find closest match */
  320. for (shift = 0; shift <= 8 && best_error > 0; shift++) {
  321. unsigned divided_parent = parent_rate >> shift;
  322. int divider = clk_get_divider(divider_bits, divided_parent,
  323. rate);
  324. unsigned effective_rate = get_rate_from_divider(divided_parent,
  325. divider);
  326. int error = rate - effective_rate;
  327. /* Given a valid divider, look for the lowest error */
  328. if (divider != -1 && error < best_error) {
  329. best_error = error;
  330. *extra_div = 1 << shift;
  331. best_divider = divider;
  332. }
  333. }
  334. /* return what we found - *extra_div will already be set */
  335. return best_divider;
  336. }
  337. /**
  338. * Adjust peripheral PLL to use the given divider and source.
  339. *
  340. * @param periph_id peripheral to adjust
  341. * @param source Source number (0-3 or 0-7)
  342. * @param mux_bits Number of mux bits (2 or 4)
  343. * @param divider Required divider in 7.1 or 15.1 format
  344. * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
  345. * for this peripheral)
  346. */
  347. static int adjust_periph_pll(enum periph_id periph_id, int source,
  348. int mux_bits, unsigned divider)
  349. {
  350. u32 *reg = get_periph_source_reg(periph_id);
  351. clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
  352. divider << OUT_CLK_DIVISOR_SHIFT);
  353. udelay(1);
  354. /* work out the source clock and set it */
  355. if (source < 0)
  356. return -1;
  357. clock_ll_set_source_bits(periph_id, mux_bits, source);
  358. udelay(2);
  359. return 0;
  360. }
  361. enum clock_id clock_get_periph_parent(enum periph_id periph_id)
  362. {
  363. int err, mux_bits, divider_bits, type;
  364. int source;
  365. err = get_periph_clock_info(periph_id, &mux_bits, &divider_bits, &type);
  366. if (err)
  367. return CLOCK_ID_NONE;
  368. source = clock_ll_get_source_bits(periph_id, mux_bits);
  369. return get_periph_clock_id(periph_id, source);
  370. }
  371. unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
  372. enum clock_id parent, unsigned rate, int *extra_div)
  373. {
  374. unsigned effective_rate;
  375. int mux_bits, divider_bits, source;
  376. int divider;
  377. int xdiv = 0;
  378. /* work out the source clock and set it */
  379. source = get_periph_clock_source(periph_id, parent, &mux_bits,
  380. &divider_bits);
  381. divider = find_best_divider(divider_bits, pll_rate[parent],
  382. rate, &xdiv);
  383. if (extra_div)
  384. *extra_div = xdiv;
  385. assert(divider >= 0);
  386. if (adjust_periph_pll(periph_id, source, mux_bits, divider))
  387. return -1U;
  388. debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
  389. get_periph_source_reg(periph_id),
  390. readl(get_periph_source_reg(periph_id)));
  391. /* Check what we ended up with. This shouldn't matter though */
  392. effective_rate = clock_get_periph_rate(periph_id, parent);
  393. if (extra_div)
  394. effective_rate /= *extra_div;
  395. if (rate != effective_rate)
  396. debug("Requested clock rate %u not honored (got %u)\n",
  397. rate, effective_rate);
  398. return effective_rate;
  399. }
  400. unsigned clock_start_periph_pll(enum periph_id periph_id,
  401. enum clock_id parent, unsigned rate)
  402. {
  403. unsigned effective_rate;
  404. reset_set_enable(periph_id, 1);
  405. clock_enable(periph_id);
  406. udelay(2);
  407. effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
  408. NULL);
  409. reset_set_enable(periph_id, 0);
  410. return effective_rate;
  411. }
  412. void clock_enable(enum periph_id clkid)
  413. {
  414. clock_set_enable(clkid, 1);
  415. }
  416. void clock_disable(enum periph_id clkid)
  417. {
  418. clock_set_enable(clkid, 0);
  419. }
  420. void reset_periph(enum periph_id periph_id, int us_delay)
  421. {
  422. /* Put peripheral into reset */
  423. reset_set_enable(periph_id, 1);
  424. udelay(us_delay);
  425. /* Remove reset */
  426. reset_set_enable(periph_id, 0);
  427. udelay(us_delay);
  428. }
  429. void reset_cmplx_set_enable(int cpu, int which, int reset)
  430. {
  431. struct clk_rst_ctlr *clkrst =
  432. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  433. u32 mask;
  434. /* Form the mask, which depends on the cpu chosen (2 or 4) */
  435. assert(cpu >= 0 && cpu < MAX_NUM_CPU);
  436. mask = which << cpu;
  437. /* either enable or disable those reset for that CPU */
  438. if (reset)
  439. writel(mask, &clkrst->crc_cpu_cmplx_set);
  440. else
  441. writel(mask, &clkrst->crc_cpu_cmplx_clr);
  442. }
  443. unsigned int __weak clk_m_get_rate(unsigned int parent_rate)
  444. {
  445. return parent_rate;
  446. }
  447. unsigned clock_get_rate(enum clock_id clkid)
  448. {
  449. struct clk_pll *pll;
  450. u32 base, divm;
  451. u64 parent_rate, rate;
  452. struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
  453. parent_rate = osc_freq[clock_get_osc_freq()];
  454. if (clkid == CLOCK_ID_OSC)
  455. return parent_rate;
  456. if (clkid == CLOCK_ID_CLK_M)
  457. return clk_m_get_rate(parent_rate);
  458. pll = get_pll(clkid);
  459. if (!pll)
  460. return 0;
  461. base = readl(&pll->pll_base);
  462. rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask);
  463. divm = (base >> pllinfo->m_shift) & pllinfo->m_mask;
  464. /*
  465. * PLLU uses p_mask/p_shift for VCO on all but T210,
  466. * T210 uses normal DIVP. Handled in pllinfo table.
  467. */
  468. #ifdef CONFIG_TEGRA210
  469. /*
  470. * PLLP's primary output (pllP_out0) on T210 is the VCO, and divp is
  471. * not applied. pllP_out2 does have divp applied. All other pllP_outN
  472. * are divided down from pllP_out0. We only support pllP_out0 in
  473. * U-Boot at the time of writing this comment.
  474. */
  475. if (clkid != CLOCK_ID_PERIPH)
  476. #endif
  477. divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask;
  478. do_div(rate, divm);
  479. return rate;
  480. }
  481. /**
  482. * Set the output frequency you want for each PLL clock.
  483. * PLL output frequencies are programmed by setting their N, M and P values.
  484. * The governing equations are:
  485. * VCO = (Fi / m) * n, Fo = VCO / (2^p)
  486. * where Fo is the output frequency from the PLL.
  487. * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
  488. * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
  489. * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
  490. *
  491. * @param n PLL feedback divider(DIVN)
  492. * @param m PLL input divider(DIVN)
  493. * @param p post divider(DIVP)
  494. * @param cpcon base PLL charge pump(CPCON)
  495. * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
  496. * be overridden), 1 if PLL is already correct
  497. */
  498. int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
  499. {
  500. u32 base_reg, misc_reg;
  501. struct clk_pll *pll;
  502. struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
  503. pll = get_pll(clkid);
  504. base_reg = readl(&pll->pll_base);
  505. /* Set BYPASS, m, n and p to PLL_BASE */
  506. base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift);
  507. base_reg |= m << pllinfo->m_shift;
  508. base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift);
  509. base_reg |= n << pllinfo->n_shift;
  510. base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift);
  511. base_reg |= p << pllinfo->p_shift;
  512. if (clkid == CLOCK_ID_PERIPH) {
  513. /*
  514. * If the PLL is already set up, check that it is correct
  515. * and record this info for clock_verify() to check.
  516. */
  517. if (base_reg & PLL_BASE_OVRRIDE_MASK) {
  518. base_reg |= PLL_ENABLE_MASK;
  519. if (base_reg != readl(&pll->pll_base))
  520. pllp_valid = 0;
  521. return pllp_valid ? 1 : -1;
  522. }
  523. base_reg |= PLL_BASE_OVRRIDE_MASK;
  524. }
  525. base_reg |= PLL_BYPASS_MASK;
  526. writel(base_reg, &pll->pll_base);
  527. /* Set cpcon (KCP) to PLL_MISC */
  528. misc_reg = readl(&pll->pll_misc);
  529. misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
  530. misc_reg |= cpcon << pllinfo->kcp_shift;
  531. writel(misc_reg, &pll->pll_misc);
  532. /* Enable PLL */
  533. base_reg |= PLL_ENABLE_MASK;
  534. writel(base_reg, &pll->pll_base);
  535. /* Disable BYPASS */
  536. base_reg &= ~PLL_BYPASS_MASK;
  537. writel(base_reg, &pll->pll_base);
  538. return 0;
  539. }
  540. void clock_ll_start_uart(enum periph_id periph_id)
  541. {
  542. /* Assert UART reset and enable clock */
  543. reset_set_enable(periph_id, 1);
  544. clock_enable(periph_id);
  545. clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
  546. /* wait for 2us */
  547. udelay(2);
  548. /* De-assert reset to UART */
  549. reset_set_enable(periph_id, 0);
  550. }
  551. #if CONFIG_IS_ENABLED(OF_CONTROL)
  552. int clock_decode_periph_id(struct udevice *dev)
  553. {
  554. enum periph_id id;
  555. u32 cell[2];
  556. int err;
  557. err = dev_read_u32_array(dev, "clocks", cell, ARRAY_SIZE(cell));
  558. if (err)
  559. return -1;
  560. id = clk_id_to_periph_id(cell[1]);
  561. assert(clock_periph_id_isvalid(id));
  562. return id;
  563. }
  564. #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
  565. int clock_verify(void)
  566. {
  567. struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
  568. u32 reg = readl(&pll->pll_base);
  569. if (!pllp_valid) {
  570. printf("Warning: PLLP %x is not correct\n", reg);
  571. return -1;
  572. }
  573. debug("PLLP %x is correct\n", reg);
  574. return 0;
  575. }
  576. void clock_init(void)
  577. {
  578. int i;
  579. pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
  580. pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
  581. pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
  582. pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB);
  583. pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY);
  584. pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
  585. pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
  586. pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
  587. pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M);
  588. debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
  589. debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]);
  590. debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
  591. debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
  592. debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
  593. debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]);
  594. debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
  595. debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
  596. for (i = 0; periph_clk_init_table[i].periph_id != -1; i++) {
  597. enum periph_id periph_id;
  598. enum clock_id parent;
  599. int source, mux_bits, divider_bits;
  600. periph_id = periph_clk_init_table[i].periph_id;
  601. parent = periph_clk_init_table[i].parent_clock_id;
  602. source = get_periph_clock_source(periph_id, parent, &mux_bits,
  603. &divider_bits);
  604. clock_ll_set_source_bits(periph_id, mux_bits, source);
  605. }
  606. }
  607. static void set_avp_clock_source(u32 src)
  608. {
  609. struct clk_rst_ctlr *clkrst =
  610. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  611. u32 val;
  612. val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
  613. (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
  614. (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
  615. (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
  616. (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
  617. writel(val, &clkrst->crc_sclk_brst_pol);
  618. udelay(3);
  619. }
  620. /*
  621. * This function is useful on Tegra30, and any later SoCs that have compatible
  622. * PLLP configuration registers.
  623. * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c
  624. */
  625. void tegra30_set_up_pllp(void)
  626. {
  627. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  628. u32 reg;
  629. /*
  630. * Based on the Tegra TRM, the system clock (which is the AVP clock) can
  631. * run up to 275MHz. On power on, the default sytem clock source is set
  632. * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
  633. * 408MHz which is beyond system clock's upper limit.
  634. *
  635. * The fix is to set the system clock to CLK_M before initializing PLLP,
  636. * and then switch back to PLLP_OUT4, which has an appropriate divider
  637. * configured, after PLLP has been configured
  638. */
  639. set_avp_clock_source(SCLK_SOURCE_CLKM);
  640. /*
  641. * PLLP output frequency set to 408Mhz
  642. * PLLC output frequency set to 228Mhz
  643. */
  644. switch (clock_get_osc_freq()) {
  645. case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
  646. clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
  647. clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
  648. break;
  649. case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
  650. clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
  651. clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
  652. break;
  653. case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
  654. clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
  655. clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
  656. break;
  657. case CLOCK_OSC_FREQ_19_2:
  658. default:
  659. /*
  660. * These are not supported. It is too early to print a
  661. * message and the UART likely won't work anyway due to the
  662. * oscillator being wrong.
  663. */
  664. break;
  665. }
  666. /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
  667. /* OUT1, 2 */
  668. /* Assert RSTN before enable */
  669. reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
  670. writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
  671. /* Set divisor and reenable */
  672. reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
  673. | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
  674. | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
  675. | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
  676. writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
  677. /* OUT3, 4 */
  678. /* Assert RSTN before enable */
  679. reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
  680. writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
  681. /* Set divisor and reenable */
  682. reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
  683. | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
  684. | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
  685. | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
  686. writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
  687. set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
  688. }
  689. int clock_external_output(int clk_id)
  690. {
  691. u32 val;
  692. if (clk_id >= 1 && clk_id <= 3) {
  693. val = tegra_pmc_readl(offsetof(struct pmc_ctlr,
  694. pmc_clk_out_cntrl));
  695. val |= 1 << (2 + (clk_id - 1) * 8);
  696. tegra_pmc_writel(val,
  697. offsetof(struct pmc_ctlr,
  698. pmc_clk_out_cntrl));
  699. } else {
  700. printf("%s: Unknown output clock id %d\n", __func__, clk_id);
  701. return -EINVAL;
  702. }
  703. return 0;
  704. }
  705. __weak bool clock_early_init_done(void)
  706. {
  707. return true;
  708. }