p2wi.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Sunxi A31 Power Management Unit
  4. *
  5. * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
  6. * http://linux-sunxi.org
  7. *
  8. * Based on sun6i sources and earlier U-Boot Allwinner A10 SPL work
  9. *
  10. * (C) Copyright 2006-2013
  11. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  12. * Berg Xing <bergxing@allwinnertech.com>
  13. * Tom Cubie <tangliang@allwinnertech.com>
  14. */
  15. #include <common.h>
  16. #include <errno.h>
  17. #include <time.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/cpu.h>
  20. #include <asm/arch/gpio.h>
  21. #include <asm/arch/p2wi.h>
  22. #include <asm/arch/prcm.h>
  23. #include <asm/arch/clock.h>
  24. #include <asm/arch/sys_proto.h>
  25. void p2wi_init(void)
  26. {
  27. struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
  28. /* Enable p2wi and PIO clk, and de-assert their resets */
  29. prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
  30. sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
  31. sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
  32. /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
  33. writel(P2WI_CTRL_RESET, &p2wi->ctrl);
  34. sdelay(0x100);
  35. writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
  36. &p2wi->cc);
  37. }
  38. int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
  39. {
  40. struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
  41. unsigned long tmo = timer_get_us() + 1000000;
  42. writel(P2WI_PM_DEV_ADDR(slave_addr) |
  43. P2WI_PM_CTRL_ADDR(ctrl_reg) |
  44. P2WI_PM_INIT_DATA(init_data) |
  45. P2WI_PM_INIT_SEND,
  46. &p2wi->pm);
  47. while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) {
  48. if (timer_get_us() > tmo)
  49. return -ETIME;
  50. }
  51. return 0;
  52. }
  53. static int p2wi_await_trans(void)
  54. {
  55. struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
  56. unsigned long tmo = timer_get_us() + 1000000;
  57. int ret;
  58. u8 reg;
  59. while (1) {
  60. reg = readl(&p2wi->status);
  61. if (reg & P2WI_STAT_TRANS_ERR) {
  62. ret = -EIO;
  63. break;
  64. }
  65. if (reg & P2WI_STAT_TRANS_DONE) {
  66. ret = 0;
  67. break;
  68. }
  69. if (timer_get_us() > tmo) {
  70. ret = -ETIME;
  71. break;
  72. }
  73. }
  74. writel(reg, &p2wi->status); /* Clear status bits */
  75. return ret;
  76. }
  77. int p2wi_read(const u8 addr, u8 *data)
  78. {
  79. struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
  80. int ret;
  81. writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
  82. writel(P2WI_DATA_NUM_BYTES(1) |
  83. P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes);
  84. writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
  85. writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
  86. ret = p2wi_await_trans();
  87. *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK;
  88. return ret;
  89. }
  90. int p2wi_write(const u8 addr, u8 data)
  91. {
  92. struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
  93. writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
  94. writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);
  95. writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes);
  96. writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
  97. writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
  98. return p2wi_await_trans();
  99. }