clock_manager_gen5.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
  4. */
  5. #include <common.h>
  6. #include <time.h>
  7. #include <asm/io.h>
  8. #include <dm.h>
  9. #include <asm/arch/clock_manager.h>
  10. #include <wait_bit.h>
  11. static const struct socfpga_clock_manager *clock_manager_base =
  12. (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
  13. /*
  14. * function to write the bypass register which requires a poll of the
  15. * busy bit
  16. */
  17. static void cm_write_bypass(u32 val)
  18. {
  19. writel(val, &clock_manager_base->bypass);
  20. cm_wait_for_fsm();
  21. }
  22. /* function to write the ctrl register which requires a poll of the busy bit */
  23. static void cm_write_ctrl(u32 val)
  24. {
  25. writel(val, &clock_manager_base->ctrl);
  26. cm_wait_for_fsm();
  27. }
  28. /* function to write a clock register that has phase information */
  29. static int cm_write_with_phase(u32 value, const void *reg_address, u32 mask)
  30. {
  31. int ret;
  32. /* poll until phase is zero */
  33. ret = wait_for_bit_le32(reg_address, mask, false, 20000, false);
  34. if (ret)
  35. return ret;
  36. writel(value, reg_address);
  37. return wait_for_bit_le32(reg_address, mask, false, 20000, false);
  38. }
  39. /*
  40. * Setup clocks while making no assumptions about previous state of the clocks.
  41. *
  42. * Start by being paranoid and gate all sw managed clocks
  43. * Put all plls in bypass
  44. * Put all plls VCO registers back to reset value (bandgap power down).
  45. * Put peripheral and main pll src to reset value to avoid glitch.
  46. * Delay 5 us.
  47. * Deassert bandgap power down and set numerator and denominator
  48. * Start 7 us timer.
  49. * set internal dividers
  50. * Wait for 7 us timer.
  51. * Enable plls
  52. * Set external dividers while plls are locking
  53. * Wait for pll lock
  54. * Assert/deassert outreset all.
  55. * Take all pll's out of bypass
  56. * Clear safe mode
  57. * set source main and peripheral clocks
  58. * Ungate clocks
  59. */
  60. int cm_basic_init(const struct cm_config * const cfg)
  61. {
  62. unsigned long end;
  63. int ret;
  64. /* Start by being paranoid and gate all sw managed clocks */
  65. /*
  66. * We need to disable nandclk
  67. * and then do another apb access before disabling
  68. * gatting off the rest of the periperal clocks.
  69. */
  70. writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
  71. readl(&clock_manager_base->per_pll.en),
  72. &clock_manager_base->per_pll.en);
  73. /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
  74. writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
  75. CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
  76. CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
  77. CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
  78. CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
  79. CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
  80. &clock_manager_base->main_pll.en);
  81. writel(0, &clock_manager_base->sdr_pll.en);
  82. /* now we can gate off the rest of the peripheral clocks */
  83. writel(0, &clock_manager_base->per_pll.en);
  84. /* Put all plls in bypass */
  85. cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
  86. CLKMGR_BYPASS_MAINPLL);
  87. /* Put all plls VCO registers back to reset value. */
  88. writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
  89. ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
  90. &clock_manager_base->main_pll.vco);
  91. writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
  92. ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
  93. &clock_manager_base->per_pll.vco);
  94. writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
  95. ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
  96. &clock_manager_base->sdr_pll.vco);
  97. /*
  98. * The clocks to the flash devices and the L4_MAIN clocks can
  99. * glitch when coming out of safe mode if their source values
  100. * are different from their reset value. So the trick it to
  101. * put them back to their reset state, and change input
  102. * after exiting safe mode but before ungating the clocks.
  103. */
  104. writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
  105. &clock_manager_base->per_pll.src);
  106. writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
  107. &clock_manager_base->main_pll.l4src);
  108. /* read back for the required 5 us delay. */
  109. readl(&clock_manager_base->main_pll.vco);
  110. readl(&clock_manager_base->per_pll.vco);
  111. readl(&clock_manager_base->sdr_pll.vco);
  112. /*
  113. * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
  114. * with numerator and denominator.
  115. */
  116. writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
  117. writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
  118. writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
  119. /*
  120. * Time starts here. Must wait 7 us from
  121. * BGPWRDN_SET(0) to VCO_ENABLE_SET(1).
  122. */
  123. end = timer_get_us() + 7;
  124. /* main mpu */
  125. writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
  126. /* altera group mpuclk */
  127. writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
  128. /* main main clock */
  129. writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
  130. /* main for dbg */
  131. writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
  132. /* main for cfgs2fuser0clk */
  133. writel(cfg->cfg2fuser0clk,
  134. &clock_manager_base->main_pll.cfgs2fuser0clk);
  135. /* Peri emac0 50 MHz default to RMII */
  136. writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
  137. /* Peri emac1 50 MHz default to RMII */
  138. writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
  139. /* Peri QSPI */
  140. writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
  141. writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
  142. /* Peri pernandsdmmcclk */
  143. writel(cfg->mainnandsdmmcclk,
  144. &clock_manager_base->main_pll.mainnandsdmmcclk);
  145. writel(cfg->pernandsdmmcclk,
  146. &clock_manager_base->per_pll.pernandsdmmcclk);
  147. /* Peri perbaseclk */
  148. writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
  149. /* Peri s2fuser1clk */
  150. writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
  151. /* 7 us must have elapsed before we can enable the VCO */
  152. while (timer_get_us() < end)
  153. ;
  154. /* Enable vco */
  155. /* main pll vco */
  156. writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
  157. &clock_manager_base->main_pll.vco);
  158. /* periferal pll */
  159. writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
  160. &clock_manager_base->per_pll.vco);
  161. /* sdram pll vco */
  162. writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
  163. &clock_manager_base->sdr_pll.vco);
  164. /* L3 MP and L3 SP */
  165. writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
  166. writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
  167. writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
  168. /* L4 MP, L4 SP, can0, and can1 */
  169. writel(cfg->perdiv, &clock_manager_base->per_pll.div);
  170. writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
  171. cm_wait_for_lock(LOCKED_MASK);
  172. /* write the sdram clock counters before toggling outreset all */
  173. writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
  174. &clock_manager_base->sdr_pll.ddrdqsclk);
  175. writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
  176. &clock_manager_base->sdr_pll.ddr2xdqsclk);
  177. writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
  178. &clock_manager_base->sdr_pll.ddrdqclk);
  179. writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
  180. &clock_manager_base->sdr_pll.s2fuser2clk);
  181. /*
  182. * after locking, but before taking out of bypass
  183. * assert/deassert outresetall
  184. */
  185. u32 mainvco = readl(&clock_manager_base->main_pll.vco);
  186. /* assert main outresetall */
  187. writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
  188. &clock_manager_base->main_pll.vco);
  189. u32 periphvco = readl(&clock_manager_base->per_pll.vco);
  190. /* assert pheriph outresetall */
  191. writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
  192. &clock_manager_base->per_pll.vco);
  193. /* assert sdram outresetall */
  194. writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
  195. CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
  196. &clock_manager_base->sdr_pll.vco);
  197. /* deassert main outresetall */
  198. writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
  199. &clock_manager_base->main_pll.vco);
  200. /* deassert pheriph outresetall */
  201. writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
  202. &clock_manager_base->per_pll.vco);
  203. /* deassert sdram outresetall */
  204. writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
  205. &clock_manager_base->sdr_pll.vco);
  206. /*
  207. * now that we've toggled outreset all, all the clocks
  208. * are aligned nicely; so we can change any phase.
  209. */
  210. ret = cm_write_with_phase(cfg->ddrdqsclk,
  211. &clock_manager_base->sdr_pll.ddrdqsclk,
  212. CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
  213. if (ret)
  214. return ret;
  215. /* SDRAM DDR2XDQSCLK */
  216. ret = cm_write_with_phase(cfg->ddr2xdqsclk,
  217. &clock_manager_base->sdr_pll.ddr2xdqsclk,
  218. CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
  219. if (ret)
  220. return ret;
  221. ret = cm_write_with_phase(cfg->ddrdqclk,
  222. &clock_manager_base->sdr_pll.ddrdqclk,
  223. CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
  224. if (ret)
  225. return ret;
  226. ret = cm_write_with_phase(cfg->s2fuser2clk,
  227. &clock_manager_base->sdr_pll.s2fuser2clk,
  228. CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
  229. if (ret)
  230. return ret;
  231. /* Take all three PLLs out of bypass when safe mode is cleared. */
  232. cm_write_bypass(0);
  233. /* clear safe mode */
  234. cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
  235. /*
  236. * now that safe mode is clear with clocks gated
  237. * it safe to change the source mux for the flashes the the L4_MAIN
  238. */
  239. writel(cfg->persrc, &clock_manager_base->per_pll.src);
  240. writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
  241. /* Now ungate non-hw-managed clocks */
  242. writel(~0, &clock_manager_base->main_pll.en);
  243. writel(~0, &clock_manager_base->per_pll.en);
  244. writel(~0, &clock_manager_base->sdr_pll.en);
  245. /* Clear the loss of lock bits (write 1 to clear) */
  246. writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
  247. CLKMGR_INTER_MAINPLLLOST_MASK,
  248. &clock_manager_base->inter);
  249. return 0;
  250. }
  251. static unsigned int cm_get_main_vco_clk_hz(void)
  252. {
  253. u32 reg, clock;
  254. /* get the main VCO clock */
  255. reg = readl(&clock_manager_base->main_pll.vco);
  256. clock = cm_get_osc_clk_hz(1);
  257. clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
  258. CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
  259. clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
  260. CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
  261. return clock;
  262. }
  263. static unsigned int cm_get_per_vco_clk_hz(void)
  264. {
  265. u32 reg, clock = 0;
  266. /* identify PER PLL clock source */
  267. reg = readl(&clock_manager_base->per_pll.vco);
  268. reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
  269. CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
  270. if (reg == CLKMGR_VCO_SSRC_EOSC1)
  271. clock = cm_get_osc_clk_hz(1);
  272. else if (reg == CLKMGR_VCO_SSRC_EOSC2)
  273. clock = cm_get_osc_clk_hz(2);
  274. else if (reg == CLKMGR_VCO_SSRC_F2S)
  275. clock = cm_get_f2s_per_ref_clk_hz();
  276. /* get the PER VCO clock */
  277. reg = readl(&clock_manager_base->per_pll.vco);
  278. clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
  279. CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
  280. clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
  281. CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
  282. return clock;
  283. }
  284. unsigned long cm_get_mpu_clk_hz(void)
  285. {
  286. u32 reg, clock;
  287. clock = cm_get_main_vco_clk_hz();
  288. /* get the MPU clock */
  289. reg = readl(&clock_manager_base->altera.mpuclk);
  290. clock /= (reg + 1);
  291. reg = readl(&clock_manager_base->main_pll.mpuclk);
  292. clock /= (reg + 1);
  293. return clock;
  294. }
  295. unsigned long cm_get_sdram_clk_hz(void)
  296. {
  297. u32 reg, clock = 0;
  298. /* identify SDRAM PLL clock source */
  299. reg = readl(&clock_manager_base->sdr_pll.vco);
  300. reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
  301. CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
  302. if (reg == CLKMGR_VCO_SSRC_EOSC1)
  303. clock = cm_get_osc_clk_hz(1);
  304. else if (reg == CLKMGR_VCO_SSRC_EOSC2)
  305. clock = cm_get_osc_clk_hz(2);
  306. else if (reg == CLKMGR_VCO_SSRC_F2S)
  307. clock = cm_get_f2s_sdr_ref_clk_hz();
  308. /* get the SDRAM VCO clock */
  309. reg = readl(&clock_manager_base->sdr_pll.vco);
  310. clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
  311. CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
  312. clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
  313. CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
  314. /* get the SDRAM (DDR_DQS) clock */
  315. reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
  316. reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
  317. CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
  318. clock /= (reg + 1);
  319. return clock;
  320. }
  321. unsigned int cm_get_l4_sp_clk_hz(void)
  322. {
  323. u32 reg, clock = 0;
  324. /* identify the source of L4 SP clock */
  325. reg = readl(&clock_manager_base->main_pll.l4src);
  326. reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
  327. CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
  328. if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
  329. clock = cm_get_main_vco_clk_hz();
  330. /* get the clock prior L4 SP divider (main clk) */
  331. reg = readl(&clock_manager_base->altera.mainclk);
  332. clock /= (reg + 1);
  333. reg = readl(&clock_manager_base->main_pll.mainclk);
  334. clock /= (reg + 1);
  335. } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
  336. clock = cm_get_per_vco_clk_hz();
  337. /* get the clock prior L4 SP divider (periph_base_clk) */
  338. reg = readl(&clock_manager_base->per_pll.perbaseclk);
  339. clock /= (reg + 1);
  340. }
  341. /* get the L4 SP clock which supplied to UART */
  342. reg = readl(&clock_manager_base->main_pll.maindiv);
  343. reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
  344. CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
  345. clock = clock / (1 << reg);
  346. return clock;
  347. }
  348. unsigned int cm_get_mmc_controller_clk_hz(void)
  349. {
  350. u32 reg, clock = 0;
  351. /* identify the source of MMC clock */
  352. reg = readl(&clock_manager_base->per_pll.src);
  353. reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
  354. CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
  355. if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
  356. clock = cm_get_f2s_per_ref_clk_hz();
  357. } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
  358. clock = cm_get_main_vco_clk_hz();
  359. /* get the SDMMC clock */
  360. reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
  361. clock /= (reg + 1);
  362. } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
  363. clock = cm_get_per_vco_clk_hz();
  364. /* get the SDMMC clock */
  365. reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
  366. clock /= (reg + 1);
  367. }
  368. /* further divide by 4 as we have fixed divider at wrapper */
  369. clock /= 4;
  370. return clock;
  371. }
  372. unsigned int cm_get_qspi_controller_clk_hz(void)
  373. {
  374. u32 reg, clock = 0;
  375. /* identify the source of QSPI clock */
  376. reg = readl(&clock_manager_base->per_pll.src);
  377. reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
  378. CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
  379. if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
  380. clock = cm_get_f2s_per_ref_clk_hz();
  381. } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
  382. clock = cm_get_main_vco_clk_hz();
  383. /* get the qspi clock */
  384. reg = readl(&clock_manager_base->main_pll.mainqspiclk);
  385. clock /= (reg + 1);
  386. } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
  387. clock = cm_get_per_vco_clk_hz();
  388. /* get the qspi clock */
  389. reg = readl(&clock_manager_base->per_pll.perqspiclk);
  390. clock /= (reg + 1);
  391. }
  392. return clock;
  393. }
  394. unsigned int cm_get_spi_controller_clk_hz(void)
  395. {
  396. u32 reg, clock = 0;
  397. clock = cm_get_per_vco_clk_hz();
  398. /* get the clock prior L4 SP divider (periph_base_clk) */
  399. reg = readl(&clock_manager_base->per_pll.perbaseclk);
  400. clock /= (reg + 1);
  401. return clock;
  402. }
  403. /* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
  404. int dw_spi_get_clk(struct udevice *bus, ulong *rate)
  405. {
  406. *rate = cm_get_spi_controller_clk_hz();
  407. return 0;
  408. }
  409. void cm_print_clock_quick_summary(void)
  410. {
  411. printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
  412. printf("DDR %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
  413. printf("EOSC1 %8d kHz\n", cm_get_osc_clk_hz(1) / 1000);
  414. printf("EOSC2 %8d kHz\n", cm_get_osc_clk_hz(2) / 1000);
  415. printf("F2S_SDR_REF %8d kHz\n", cm_get_f2s_sdr_ref_clk_hz() / 1000);
  416. printf("F2S_PER_REF %8d kHz\n", cm_get_f2s_per_ref_clk_hz() / 1000);
  417. printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
  418. printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
  419. printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
  420. printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
  421. }