fsp-m.txt 9.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327
  1. * Intel FSP-M configuration
  2. Several Intel platforms require the execution of the Intel FSP (Firmware
  3. Support Package) for initialization. The FSP consists of multiple parts, one
  4. of which is the FSP-M (Memory initialization phase).
  5. This binding applies to the FSP-M for the Intel Apollo Lake SoC.
  6. The FSP-M is available on Github [1].
  7. For detailed information on the FSP-M parameters see the documentation in
  8. FSP/ApolloLakeFspBinPkg/Docs [2].
  9. The properties of this binding are all optional. If no properties are set the
  10. values of the FSP-M are used.
  11. [1] https://github.com/IntelFsp/FSP
  12. [2] https://github.com/IntelFsp/FSP/tree/master/ApolloLakeFspBinPkg/Docs
  13. Optional properties:
  14. - fspm,training-delay: Time taken to train DDR memory if there is no cached MRC
  15. data, in seconds. This is used to show a message if possible. For Chromebook
  16. Coral this is typically 21 seconds. For an APL board with 1GB of RAM, it may
  17. be only 6 seconds.
  18. - fspm,serial-debug-port-address: Debug Serial Port Base address
  19. - fspm,serial-debug-port-type: Debug Serial Port Type
  20. 0: NONE
  21. 1: I/O
  22. 2: MMIO (default)
  23. - fspm,serial-debug-port-device: Serial Port Debug Device
  24. 0: SOC UART0
  25. 1: SOC UART1
  26. 2: SOC UART2 (default)
  27. 3: External Device
  28. - fspm,serial-debug-port-stride-size: Debug Serial Port Stride Size
  29. 0: 1
  30. 2: 4 (default)
  31. - fspm,mrc-fast-boot: Memory Fast Boot
  32. - fspm,igd: Integrated Graphics Device
  33. - fspm,igd-dvmt50-pre-alloc: DVMT Pre-Allocated
  34. 0x02: 64 MB (default)
  35. 0x03: 96 MB
  36. 0x04: 128 MB
  37. 0x05: 160 MB
  38. 0x06: 192 MB
  39. 0x07: 224 MB
  40. 0x08: 256 MB
  41. 0x09: 288 MB
  42. 0x0A: 320 MB
  43. 0x0B: 352 MB
  44. 0x0C: 384 MB
  45. 0x0D: 416 MB
  46. 0x0E: 448 MB
  47. 0x0F: 480 MB
  48. 0x10: 512 MB
  49. - fspm,aperture-size: Aperture Size
  50. 0x1: 128 MB (default)
  51. 0x2: 256 MB
  52. 0x3: 512 MB
  53. - fspm,gtt-size: GTT Size
  54. 0x1: 2 MB
  55. 0x2: 4 MB
  56. 0x3: 8 MB (default)
  57. - fspm,primary-video-adaptor: Primary Display
  58. 0x0: AUTO (default)
  59. 0x2: IGD
  60. 0x3: PCI
  61. - fspm,package: Package
  62. 0x0: SODIMM (default)
  63. 0x1: BGA
  64. 0x2: BGA mirrored (LPDDR3 only)
  65. 0x3: SODIMM/UDIMM with Rank 1 Mirrored (DDR3L)
  66. - fspm,profile: Profile
  67. 0x01: WIO2_800_7_8_8
  68. 0x02: WIO2_1066_9_10_10
  69. 0x03: LPDDR3_1066_8_10_10
  70. 0x04: LPDDR3_1333_10_12_12
  71. 0x05: LPDDR3_1600_12_15_15
  72. 0x06: LPDDR3_1866_14_17_17
  73. 0x07: LPDDR3_2133_16_20_20
  74. 0x08: LPDDR4_1066_10_10_10
  75. 0x09: LPDDR4_1600_14_15_15
  76. 0x0A: LPDDR4_2133_20_20_20
  77. 0x0B: LPDDR4_2400_24_22_22
  78. 0x0C: LPDDR4_2666_24_24_24
  79. 0x0D: LPDDR4_2933_28_27_27
  80. 0x0E: LPDDR4_3200_28_29_29
  81. 0x0F: DDR3_1066_6_6_6
  82. 0x10: DDR3_1066_7_7_7
  83. 0x11: DDR3_1066_8_8_8
  84. 0x12: DDR3_1333_7_7_7
  85. 0x13: DDR3_1333_8_8_8
  86. 0x14: DDR3_1333_9_9_9
  87. 0x15: DDR3_1333_10_10_10
  88. 0x16: DDR3_1600_8_8_8
  89. 0x17: DDR3_1600_9_9_9
  90. 0x18: DDR3_1600_10_10_10
  91. 0x19: DDR3_1600_11_11_11 (default)
  92. 0x1A: DDR3_1866_10_10_10
  93. 0x1B: DDR3_1866_11_11_11
  94. 0x1C: DDR3_1866_12_12_12
  95. 0x1D: DDR3_1866_13_13_13
  96. 0x1E: DDR3_2133_11_11_11
  97. 0x1F: DDR3_2133_12_12_12
  98. 0x20: DDR3_2133_13_13_13
  99. 0x21: DDR3_2133_14_14_14
  100. 0x22: DDR4_1333_10_10_10
  101. 0x23: DDR4_1600_10_10_10
  102. 0x24: DDR4_1600_11_11_11
  103. 0x25: DDR4_1600_12_12_12
  104. 0x26: DDR4_1866_12_12_12
  105. 0x27: DDR4_1866_13_13_13
  106. 0x28: DDR4_1866_14_14_14
  107. 0x29: DDR4_2133_14_14_14
  108. 0x2A: DDR4_2133_15_15_15
  109. 0x2B: DDR4_2133_16_16_16
  110. 0x2C: DDR4_2400_15_15_15
  111. 0x2D: DDR4_2400_16_16_16
  112. 0x2E: DDR4_2400_17_17_17
  113. 0x2F: DDR4_2400_18_18_18
  114. - fspm,memory-down: Memory Down
  115. 0x0: No (default)
  116. 0x1: Yes
  117. 0x2: 1MD+SODIMM (for DDR3L only) ACRD
  118. 0x3: 1x32 LPDDR4
  119. - fspm,ddr3l-page-size: DDR3LPageSize
  120. 0x1: 1KB (default)
  121. 0x2: 2KB
  122. - fspm,ddr3-lasr: DDR3LASR
  123. - fspm,scrambler-support: ScramblerSupport
  124. - fspm,interleaved-mode: InterleavedMode
  125. - fspm,channel-hash-mask: ChannelHashMask
  126. - fspm,fspm,slice-hash-mask: SliceHashMask
  127. - fspm,channels-slices-enable: ChannelsSlices
  128. - fspm,min-ref-rate2x-enable: MinRefRate2x
  129. - fspm,dual-rank-support-enable: DualRankSupport
  130. - fspm,rmt-mode: RmtMode
  131. - fspm,memory-size-limit: MemorySizeLimit
  132. - fspm,low-memory-max-value: LowMemoryMaxValue
  133. - fspm,high-memory-max-value: HighMemoryMaxValue
  134. - fspm,disable-fast-boot: FastBoot
  135. - fspm,dimm0-spd-address: DIMM0 SPD Address
  136. - fspm,dimm1-spd-address: DIMM1 SPD Address
  137. - fspm,chX-rank-enable: Must be set to enable rank (X = 0-3)
  138. - fspm,chX-device-width: DRAM device width per DRAM channel (X = 0-3)
  139. 0: x8
  140. 1: x16
  141. 2: x32
  142. 3: x64
  143. - fspm,chX-dram-density: Must specify the DRAM device density (X = 0-3)
  144. 0: 4Gb
  145. 1: 6Gb
  146. 2: 8Gb
  147. 3: 12Gb
  148. 4: 16Gb
  149. 5: 2Gb
  150. - fspm,chX-option: Channel options (X = 0-3)
  151. - fspm,chX-odt-config: Channel Odt Config (X = 0-3)
  152. - fspm,chX-mode2-n: Force 2N Mode (X = 0-3)
  153. 0x0: Auto
  154. 0x1: Force 2N CMD Timing Mode
  155. - fspm,chX-odt-levels: Channel Odt Levels (X = 0-3)
  156. 0: ODT Connected to SoC
  157. 1: ODT held high
  158. - fspm,rmt-check-run: RmtCheckRun
  159. - fspm,rmt-margin-check-scale-high-threshold: RmtMarginCheckScaleHighThreshold
  160. - fspm,ch-bit-swizzling: Bit_swizzling
  161. - fspm,msg-level-mask: MsgLevelMask
  162. - fspm,pre-mem-gpio-table-pin-num: PreMem GPIO Pin Number for each table
  163. - fspm,pre-mem-gpio-table-ptr: PreMem GPIO Table Pointer
  164. - fspm,pre-mem-gpio-table-entry-num: PreMem GPIO Table Entry Number
  165. - fspm,enhance-port8xh-decoding: Enhance the port 8xh decoding
  166. - fspm,spd-write-enable: SPD Data Write
  167. - fspm,mrc-data-saving: MRC Training Data Saving
  168. - fspm,oem-loading-base: OEM File Loading Address
  169. - fspm,oem-file-name: OEM File Name to Load
  170. - fspm,mrc-boot-data-ptr:
  171. - fspm,emmc-trace-len: eMMC Trace Length
  172. 0x0: Long
  173. 0x1: Short
  174. - fspm,skip-cse-rbp: Skip CSE RBP to support zero sized IBB
  175. - fspm,npk-en: Npk Enable
  176. 0: Disable
  177. 1: Enable
  178. 2: Debugger
  179. 3: Auto (default)
  180. - fspm,fw-trace-en: FW Trace Enable
  181. - fspm,fw-trace-destination: FW Trace Destination
  182. 1: NPK_TRACE_TO_MEMORY
  183. 2: NPK_TRACE_TO_DCI
  184. 3: NPK_TRACE_TO_BSSB
  185. 4: NPK_TRACE_TO_PTI (default)
  186. - fspm,recover-dump: NPK Recovery Dump
  187. - fspm,msc0-wrap: Memory Region 0 Buffer WrapAround
  188. 0: n0-warp
  189. 1: n1-warp (default)
  190. - fspm,msc1-wrap: Memory Region 1 Buffer WrapAround
  191. 0: n0-warp
  192. 1: n1-warp (default)
  193. - fspm,msc0-size: Memory Region 0 Buffer Size
  194. 0: 0MB (default)
  195. 1: 1MB
  196. 2: 8MB
  197. 3: 64MB
  198. 4: 128MB
  199. 5: 256MB
  200. 6: 512MB
  201. 7: 1GB
  202. - fspm,msc1-size: Memory Region 1 Buffer Size
  203. 0: 0MB (default)
  204. 1: 1MB
  205. 2: 8MB
  206. 3: 64MB
  207. 4: 128MB
  208. 5: 256MB
  209. 6: 512MB
  210. 7: 1GB
  211. - fspm,pti-mode: PTI Mode
  212. 0: 0ff
  213. 1: x4 (default)
  214. 2: x8
  215. 3: x12
  216. 4: x16
  217. - fspm,pti-training: PTI Training
  218. 0: off (default)
  219. 1-6: 1-6
  220. - fspm,pti-speed:
  221. 0: full
  222. 1: half
  223. 2: quarter (default)
  224. - fspm,punit-mlvl: Punit Message Level
  225. 0:
  226. 1: (default)
  227. 2-4: 2-4
  228. - fspm,pmc-mlvl: PMC Message Level
  229. 0:
  230. 1: (default)
  231. 2-4: 2-4
  232. - fspm,sw-trace-en: SW Trace Enable
  233. - fspm,periodic-retraining-disable: Periodic Retraining Disable
  234. - fspm,enable-reset-system: Enable Reset System
  235. - fspm,enable-s3-heci2: Enable HECI2 in S3 resume path
  236. - fspm,variable-nvs-buffer-ptr:
  237. - fspm,start-timer-ticker-of-pfet-assert: PCIE SLOT Power Enable Assert Time - PFET
  238. - fspm,rt-en: Real Time Enabling
  239. - fspm,skip-pcie-power-sequence: Skip Pcie Power Sequence
  240. Example:
  241. &host_bridge {
  242. fspm,package = <PACKAGE_BGA>;
  243. fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>;
  244. fspm,memory-down = <MEMORY_DOWN_YES>;
  245. fspm,scrambler-support = <1>;
  246. fspm,interleaved-mode = <INTERLEAVED_MODE_ENABLE>;
  247. fspm,channel-hash-mask = <0x36>;
  248. fspm,slice-hash-mask = <0x9>;
  249. fspm,low-memory-max-value = <2048>;
  250. fspm,ch0-rank-enable = <1>;
  251. fspm,ch0-device-width = <CHX_DEVICE_WIDTH_X16>;
  252. fspm,ch0-dram-density = <CHX_DEVICE_DENSITY_8GB>;
  253. fspm,ch0-option = <(CHX_OPTION_RANK_INTERLEAVING |
  254. CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
  255. fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
  256. fspm,ch1-rank-enable = <1>;
  257. fspm,ch1-device-width = <CHX_DEVICE_WIDTH_X16>;
  258. fspm,ch1-dram-density = <CHX_DEVICE_DENSITY_8GB>;
  259. fspm,ch1-option = <(CHX_OPTION_RANK_INTERLEAVING |
  260. CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
  261. fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
  262. fspm,ch2-rank-enable = <1>;
  263. fspm,ch2-device-width = <CHX_DEVICE_WIDTH_X16>;
  264. fspm,ch2-dram-density = <CHX_DEVICE_DENSITY_8GB>;
  265. fspm,ch2-option = <(CHX_OPTION_RANK_INTERLEAVING |
  266. CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
  267. fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
  268. fspm,ch3-rank-enable = <1>;
  269. fspm,ch3-device-width = <CHX_DEVICE_WIDTH_X16>;
  270. fspm,ch3-dram-density = <CHX_DEVICE_DENSITY_8GB>;
  271. fspm,ch3-option = <(CHX_OPTION_RANK_INTERLEAVING |
  272. CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
  273. fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
  274. fspm,fspm,skip-cse-rbp = <1>;
  275. fspm,ch-bit-swizzling = /bits/ 8 <
  276. /* LP4_PHYS_CH0A */
  277. /* DQA[0:7] pins of LPDDR4 module */
  278. 6 7 5 4 3 1 0 2
  279. /* DQA[8:15] pins of LPDDR4 module */
  280. 12 10 11 13 14 8 9 15
  281. /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
  282. 16 22 23 20 18 17 19 21
  283. /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
  284. 30 28 29 25 24 26 27 31
  285. /* LP4_PHYS_CH0B */
  286. /* DQA[0:7] pins of LPDDR4 module */
  287. 7 3 5 2 6 0 1 4
  288. /* DQA[8:15] pins of LPDDR4 module */
  289. 9 14 12 13 10 11 8 15
  290. /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
  291. 20 22 23 16 19 17 18 21
  292. /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
  293. 28 24 26 27 29 30 31 25
  294. /* LP4_PHYS_CH1A */
  295. /* DQA[0:7] pins of LPDDR4 module */
  296. 2 1 6 7 5 4 3 0
  297. /* DQA[8:15] pins of LPDDR4 module */
  298. 11 10 8 9 12 15 13 14
  299. /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
  300. 17 23 19 16 21 22 20 18
  301. /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
  302. 31 29 26 25 28 27 24 30
  303. /* LP4_PHYS_CH1B */
  304. /* DQA[0:7] pins of LPDDR4 module */
  305. 4 3 7 5 6 1 0 2
  306. /* DQA[8:15] pins of LPDDR4 module */
  307. 15 9 8 11 14 13 12 10
  308. /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
  309. 20 23 22 21 18 19 16 17
  310. /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
  311. 25 28 30 31 26 27 24 29>;
  312. };